KR19980084664A - Internal power supply voltage generation circuit of semiconductor memory device - Google Patents

Abstract

The present invention relates to an internal power supply voltage generation circuit of a semiconductor device, comprising: a comparison unit configured to receive a power supply voltage and an internal supply power supply voltage from an external device, and to compare the output power supply voltages with each other; An output control unit controlling a voltage supplied to an output terminal in response to the comparison signal; A first discharge part and a second discharge part connected in parallel between the comparator and ground, wherein the first discharge part flows a current of the comparator part to ground according to a reference voltage applied from the outside; A first detection unit detecting whether a memory device operating in the standby mode is operated, and generating a first detection signal according to the detected state; Second detection means for deactivating the first control signal in the standby mode and generating a second detection signal when the pulse signal is activated; And a current discharge control unit for allowing the second discharge unit to flow a current of the comparator to ground while the second detection signal is an active period. Therefore, the internal power supply voltage generation circuit of the present invention detects that the control signal generated in synchronization with the row address strobe signal in the standby mode is inactivated, and that the pulse signal generated in synchronization with the column address strobe signal is activated, thereby providing an internal power supply voltage. By controlling the amount of current discharged from the circuit, it is possible to quickly recover the dip of the internal power supply voltage caused by the peripheral circuit operated in the standby mode, and to provide a stable internal power supply voltage when the standby mode is switched to the active mode. have.

Description

Internal power supply voltage generation circuit of semiconductor memory device

The present invention relates to an internal power supply voltage generator circuit, and more particularly, to an internal power supply voltage generator circuit for a semiconductor device operated in a standby mode.

Recently, in order to improve the degree of integration of semiconductor memory devices, miniaturization and low power operation of devices have been required. Therefore, the use of the stepped down internal power supply voltage of the external power supply voltage has been recognized as an important problem. However, when the semiconductor memory device becomes very high density, problems such as punch through between the source and the drain of the MOS transistors and deterioration of the gate oxide film of the transistors if the externally applied voltage (for example, 5V) is used as it is. Happens. Therefore, in order to solve the above problem, an internal power supply voltage generation circuit for converting the external power supply voltage into an internal power supply voltage (for example, 3V to 4V) has been used.

In general, when the semiconductor memory is in the standby mode, there should be no elements that consume the internal power supply voltage. In practice, however, some driving circuits of the other power supply voltage devices are operated to stabilize the operation of the semiconductor memory device. Also, as some peripheral circuits operate, the semiconductor memory device continues to draw current even in the standby mode, which causes the internal power supply voltage to drop. In order to compensate for the internal power supply voltage dropped due to the current consumed in the standby mode of the semiconductor memory device, the operation of another dependent internal power supply device operated in the standby mode is detected to enhance the driving capability of the internal power supply device. . However, it was not possible to fully compensate for the current consumed when some peripheral circuitry in the memory device was operated.

1 is a block diagram illustrating a connection state of a peripheral module of a semiconductor memory device.

2 is a timing diagram illustrating an operating state of FIG. 1.

1 and 2, a semiconductor memory device in which a first memory device U1, a third memory device U3, a second memory device U2, and a fourth memory device U4 share data input / output, respectively. It is shown as a module of.

When the first memory device U1 and the second memory device U2 are in an active state, the third memory device U3 and the fourth memory device U4 are inactivated. In other words, Is low level, At the low level, the third and fourth memory devices U3 and U4 The signals remain high at the high level. In this case, column address strobe signals of the memory devices U3 and U4. Since the operation is performed in accordance with the operations of the memory devices U1 and U2, the current in the memory devices U3 and U4 continues to be consumed, and the internal power supply voltage drops. Then, the dropped voltage causes the third and fourth memory devices to become inactive even when they enter the active state.

At this time, the first and second memory devices U1 and U2 become inactive and the time when the third and fourth memory devices U3 and U4 are activated should be small. That is, in the standby mode, it is necessary to quickly recover a dip of the internal power supply voltage caused by the dropped voltages of the memory devices U3 and U4. For example, if the memory devices U3 and U4 are to be switched from the standby mode to the active mode, And And And Must be in the enabled state. However, as can be seen on the timing diagram of FIG. And Is in an inactive state, the memory devices U3 and U4 do not operate.

Therefore, in the conventional internal power supply voltage generation circuit, a dip of the internal power supply voltage is generated due to the current consumed in the standby mode. In addition, since a large amount of time is required to recover the dip, an unsuitable problem may occur in a semiconductor memory device requiring high speed.

An object of the present invention is to provide an internal power supply voltage generation circuit for a semiconductor memory device capable of quickly recovering a dip of an internal power supply voltage when converting from a standby mode to an active mode, thereby reducing the time required for mode switching.

1 is a block diagram illustrating a peripheral circuit module connection state of a semiconductor memory device;

2 is an operation timing diagram according to a conventional embodiment;

3 is a block diagram showing a configuration of an internal power supply voltage generating circuit according to an embodiment of the present invention;

4 is a block diagram schematically illustrating a configuration of a first buffer, a second buffer, and a second detection circuit connected to FIG. 3;

5 is a circuit diagram showing in detail the second detection circuit of FIG.

6A is an operation timing diagram in accordance with an embodiment of the present invention;

Fig. 6B is a comparison waveform showing the recovery time of the internal power supply voltage according to the prior art and the present invention;

* Explanation of symbols for the main parts of the drawings

10: comparison unit 20: output control unit

30: first discharge unit 40: second discharge unit

50: first detector 60: second detector

70: discharge control

(Configuration)

According to an aspect of the present invention proposed to achieve the above object, a first buffer for generating a first control signal in synchronization with a row address strobe signal applied from the outside and a column address strobe signal applied from the outside And a second buffer for generating a pulse signal, the internal power supply voltage generating circuit of the semiconductor memory device for converting an external supply power applied from the outside into an internal supply power, wherein the power supply voltage and the internal supply power supply voltage are externally supplied. Comparison means for receiving the comparison and outputting a comparison signal; Output control means for controlling a voltage supplied to an output terminal in response to the comparison signal; A first discharging means and a second discharging means connected in parallel between said comparing means and ground, said first discharging means flowing a predetermined amount of current of said comparing means to ground in accordance with a reference voltage applied from the outside; First detection means for detecting whether the memory device operated in the standby mode is operated and generating a first detection signal according to the detected state; Second detection means for deactivating the first control signal in the standby state and generating a second detection signal when the pulse signal is activated; And current discharge control means for allowing the second discharge means to flow the current of the comparison means to ground while the second detection signal is in the activation period.

In a preferred embodiment of such a circuit, the second detecting means receives the first control signal and the pulse signal and outputs an input signal that is activated when the first control signal is deactivated and the pulse signal is activated. Input means for performing; Delay means for delaying the input signal to generate a delay signal; And combining means for receiving the delay signal and the input signal and combining the delayed signal and the input signal.

In a preferred embodiment of such a circuit, the input means comprises: a first inverter for inverting the first control signal; And a first NAND gate including an input terminal connected to an output terminal of the first inverter, a type force terminal to which the pulse signal is applied, and an output terminal for outputting an input signal.

In a preferred embodiment of such a circuit, the delay means comprises two inverters connected in series between an output end of the input means and one input end of the combination means.

In a preferred embodiment of such a circuit, the current discharge control means comprises one input end to which the output end of the delay means is connected, a type force end connected to the output end of the input means, and an output end to which the second detection signal is output. And a second NAND gate.

(Example)

The novel internal power supply voltage generation circuit of the present invention discharges a large amount of current at once by using control signals generated in synchronization with the row address strobe signal and the column address strobe signal in the standby mode. This allows the dips in the internal supply voltage to recover faster and transition from stand mode to active mode at a more stable level.

Hereinafter, reference drawings according to preferred embodiments of the present invention will be described with reference to FIGS. 3 to 4, 5, and 6.

3 is a block diagram showing a configuration of an internal power supply voltage generator circuit.

Referring to FIG. 3, the internal power supply voltage generation circuit includes a comparator 10, an output control unit 20, a first discharge unit 30, a second discharge unit 40, a first detection unit 50, and a second unit. The detection part 60 and the current discharge control part 70 are provided.

The comparison unit 10 compares the reference voltage Vref with the internal power supply voltage IVC, and outputs a comparison signal Vcom. The output control unit 11 outputs an external supply voltage (VCOM) by the comparison signal Vcom. EVC) is converted into an internal power supply voltage IVC and output. At this time, the amount of current discharged from the comparator 10 to the ground is controlled by the first discharge unit 30 and the second discharge unit 40. In particular, the operation of the second discharge unit 60 is determined by the current discharge control unit combining the detection signals generated by the first detection unit 50 and the second detection unit 60. If any one of the detection signals is at a high level, the second discharge unit 60 sends a predetermined amount of current of the comparison unit 10 to ground. If both of the first discharge unit 50 and the second discharge unit 60 operate, a larger amount of current may be sent to ground than when the first discharge unit 50 operates alone.

Referring to FIG. 3, the comparator 10 includes PMOS transistors M1 and M2 having an external power supply voltage EVC, a gate connected to each other, and a drain and a gate connected to each other. The drains are connected to the drains of the PMOS transistors M1 and M2, respectively, the reference voltage Vref and the internal power supply voltage IVC are applied to a gate, and the sources are connected to the NMOS transistors M3 and M4. ).

The first discharge unit 30 and the second discharge unit 40 are connected in parallel between the comparison unit 10 and the ground VSS. The first discharge unit 30 includes an NMOS transistor M6 to which a reference voltage Vref is applied to a gate, and the second discharge unit 40 has an output signal of the current discharge control unit 70 at a gate thereof. An NMOS transistor M7 is applied.

Referring to the operation of the comparator 10, first, the reference voltage Vref and the internal power supply voltage IVC are compared to output a comparison signal Vcom. For example, when the reference voltage Vref is greater than the internal power supply voltage IVC, the transistor M3 is turned on, so that the node N1 to which the drain of the transistor M3 is connected is at a low level, The comparison signal Vcom is output. On the contrary, when the reference voltage Vref is smaller than the internal power supply voltage IVC, the transistor M4 is turned on, so that the node N2 to which the drain of the transistor M4 is connected is charged low. Therefore, since the transistor M1 is turned on and the node N1 is charged to the external power supply voltage EVC level, the high level comparison signal Vcom is output.

The output controller 20 includes a PMOS transistor M5 having a source and a drain connected to an external power supply voltage terminal and an internal power supply voltage complex, and a gate connected to the first node N1 to receive the comparison signal Vcom. ).

When the comparison signal Vcom is at the high level, the transistor M5 is turned off to maintain the previous internal power supply voltage IVC level. When the comparison signal Vcom is at the low level, the transistor M5 is turned on and converts the external power voltage EVC into an internal power voltage IVC.

The first discharge unit 30 and the second discharge unit 40 are connected in parallel to each other between the comparison unit 10 and the ground VSS. The first discharge unit 30 includes an NMOS transistor M6 to which a reference voltage Vref is applied to a gate, and the second discharge unit 40 is connected to an output terminal of the current discharge control unit 70. NMOS transistor M7 is provided.

The first current discharge unit 30 causes the amount of current discharged from the comparison unit 10 to flow to the ground constantly, and the second current discharge unit 40 controls the amount of current discharged from the comparison unit 10. Adjust That is, when the reference voltage Vref is applied, the transistor M6 is turned on to discharge a certain amount of current from the comparator 10 to ground. At this time, the greater the magnitude of the reference voltage Vref is, the transistor M6 is fully conductive, and the amount of current discharged in proportion to the conduction state is also increased. In addition, the second discharge unit 40 of the comparison unit 10 when any one of the detection signals (CK, PCSTBE) generated from the first detection unit 50 and the second detection unit 60 is at a high level. Flow current to ground.

When the transistor M7 of the second discharge unit 40 is turned on, the deep discharge of the internal power supply voltage IVC is quickly restored by discharging a larger amount of current than when only the first discharge unit 30 is turned on. can do.

The first detector 50 includes a pumping voltage detector 50a, a reverse voltage detector 50b, and an oragate 50c. An output terminal of the pumping voltage detector 50a and an output terminal of the reverse voltage detector 50b are respectively connected to an input terminal of the oragate 50c and output a clock signal CK to its output terminal.

The circuit configuration and operation of the pumping voltage detector 50a and the reverse voltage detector 50b are omitted since they are well known in the art.

FIG. 4 is a block diagram showing the configuration of the buffers connected to FIG. 3 and the second detector.

5 is a circuit diagram showing in detail the configuration of the second detection unit.

4 and 5, the second detector 60 of the present invention includes an input unit 61, a delay unit 62, and a combination unit 63. The signals PR and PCM applied to the input unit 61 of the second detection unit 60 are externally applied row address strobe signals. Control signal PR and column address strobe signal generated in synchronization with The pulse signal PCM is generated in synchronization with.

When the first control signal PR is applied to the input unit 61, the inverter 61a outputting the inverted signal thereof and the inverted signal and the pulse signal PCM are input to output the combined signal S1. It consists of a NAND gate 61b. In addition, the delay unit 62 delays the combined signal S1 by connecting two inverters 62a and 62b in series, and the combination unit 63 is a combination from the input unit 61. And a NAND gate 63a which receives the signal S1 and the delayed signal DS1 from the delay unit 62 and combines them.

The operation of the second detection unit 60 will be described. When the first control signal PR is in an inactive state, that is, logic ″ 0 ″, and the pulse signal is logic ″ 1 ″, the logic from the inverter 61a is determined. A signal of "1" is output. The signal output from the NAND gate 61b is a signal of logic ″ 0 ″ due to the signal of logic ″ 1 ″ output from the inverter 61a and the pulse signal PCM of logic ″ 1 ″. On the other hand, the delay unit 62 delays and outputs the logic ″ 0 ″ signal from the input unit 61. The combining unit 63 receives the delay signal DS1 of the logic ″ 0 ″ and the signal of the logic ″ 0 ″ from the input unit 61 and outputs the second detection signal PCSTBE of the logic ″ 1 ″. do. As a result, the second detector 60 outputs the activated second detection signal PCSTBE only when the first control signal PR is in an inactive state and the pulse signal PCM is in an activated state.

6A is a timing diagram showing an operation state of the second detection unit.

Referring to FIG. 6A, the first section is when the first memory device U1 and the second memory device U2 of FIG. 1 are in an active state, and the second section is the third memory device U3 and the fourth memory device. When (U4) is in the standby state. Row address strobe signal in the second interval Address strobe signal when is disabled Is activated. In this case, the second detector 60 may transmit the row address signal. A deactivation period of the control signal PR generated in synchronization with the signal and the column address strobe signal The pulse signal PCM generated in synchronization with the signal is applied to generate the second detection signal PCSTBE having a high level. Due to the high level of the second detection signal PCSTBE, the current discharge control unit 70 outputs a signal of logic ″ 1 ″, and accordingly, the second discharge unit 40 is turned on so that the comparison unit 10 may be turned on. The current flows to ground together with the first discharge unit 30.

Therefore, since the first discharge unit 30 and the second discharge unit 40 discharge the current of the comparison unit 10 to the ground at once, the dip of the internal power supply voltage is quickly restored.

6B is a waveform diagram showing the recovery time of the internal power supply voltage according to the prior art and the embodiment of the present invention.

As shown in Fig. 6B, it can be seen that the time for recovering the dip of the internal power supply voltage IVC of the present invention is shorter than the time for recovering the dip of the conventional internal power supply voltage IVC. This quickly restores the dip in the internal supply voltage, reducing the time it takes to convert from standby to active mode.

The present invention detects an inactive state of a control signal generated in synchronization with a row address strobe signal and an active state of a pulse signal generated in synchronization with a column address strobe signal in a standby state, thereby detecting the amount of current discharged from the internal power supply voltage generating circuit. By adjusting, it is possible to quickly recover the dip phenomenon of the internal power supply voltage caused by the peripheral circuit operated in the standby mode, thereby providing a stable internal power supply voltage.

Claims (5)

A first buffer for generating a first control signal in synchronization with a row address strobe signal applied from the outside, and a second buffer for generating a pulse signal in synchronization with a column address strobe signal applied from the outside, and applied from the outside An internal power supply voltage generation circuit of a semiconductor memory device for converting an external supply power supply into an internal supply power supply, Comparison means for receiving a power supply voltage from an external supply voltage and an internal supply power supply voltage, comparing the same, and outputting a comparison signal; Output control means for controlling a voltage supplied to an output terminal in response to the comparison signal; A first discharge means and a second discharge means connected in parallel between said comparison means and ground, The first discharging means sends a predetermined amount of current of the comparing means to ground in accordance with a reference voltage applied from the outside; First detection means for detecting whether the memory device operated in the standby mode is operated and generating a first detection signal according to the detected state; Second detection means for deactivating the first control signal in the standby mode and generating a second detection signal when the pulse signal is activated; And current discharge control means for allowing the second discharge means to send the current of the comparison means to ground while the second detection signal is in the activation period. The method of claim 1, The second detecting means comprises: input means for receiving the first control signal and the pulse signal and outputting an input signal that is activated when the first control signal is deactivated and the pulse signal is activated; Delay means for delaying the input signal to generate a delay signal; And an combining means for receiving the delay signal and the input signal and combining the delayed signal and the input signal. The method of claim 2, The input means includes a first inverter for inverting the first control signal; And an input terminal connected to an output terminal of the first inverter, a type force terminal to which the pulse signal is applied, and a first NAND gate configured to output an input signal. The method of claim 2, And the delay means comprises two inverters connected in series between an output end of the input means and one input end of the combining means. The method of claim 1, The current discharge control means has an internal power supply voltage including a second NAND gate including an input terminal to which an output terminal of the delay means is connected, a type force terminal connected to an output terminal of the input means, and an output terminal to which a second detection signal is output. Generation circuit.