KR19980083459A - Databus Sizing Device - Google Patents

Abstract

The present invention relates to an apparatus for adjusting a data bus size, comprising: a data processor for outputting data, an address signal, and a control signal, in particular for controlling a predetermined device; A control signal generator for receiving and decoding a predetermined address signal and a control signal output from the data processor, and outputting a data direction control signal and a selection signal for selecting a predetermined device; A first buffer unit which receives, buffers and outputs predetermined data and address signals output from the data processing unit according to the control signal of the control signal generator; A second buffer unit which receives, buffers and latches predetermined data output from the first buffer unit according to a control signal of the control signal generator; An n-th buffer unit for receiving, buffering and latching and outputting predetermined data output from the first buffer unit according to the control signal of the control signal generator; And a device unit configured to receive an address signal output from the first buffer unit and data output from the buffer unit according to a selection control signal of the control signal generator. Therefore, in the present invention, an interface with a peripheral controller operating at high performance by using a low-performance data processor has the effect of operating the system regardless of the size of the data bus.

Description

Databus Sizing Device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic data bus sizing system. In particular, when designing an application circuit using a data processor (called a microprocessor), data can be inputted and outputted even when the bus sizes are different between the data processor and various devices. It relates to a bus size adjusting device.

In general, when the data processing unit and each device is interfaced with each other, accurate bus sizes are required, so when selecting a data processing unit and a device, the data bus size should be considered first. Data processing units are emerging, and various peripheral devices for high performance and specific purposes are being released.

In order to realize high-performance functions, the devices of the specific purpose are gradually increasing the length and operating frequency of data, but the function of the data processing unit is not limited to the control of such devices due to the improvement of the functions of the devices and the increase of the data processing speed. As a matter of fact, the function for processing data is reduced in reverse, so using a high-performance peripheral device will be an inefficient choice.

FIG. 1 is a block diagram showing an interface circuit between a data processing unit and a peripheral device according to the prior art. The data processing unit 1, the control signal unit 3, the buffer unit 5, and the devices 7 and 9 are shown in FIG. Include.

On the other hand, the data processing section 1 is configured to output address signals, data and control signals for controlling the devices 7 and 9, and the control signal section 3 is output from the data processing section 1. A predetermined address signal and a control signal are input, and a control signal and a selection signal for selecting the predetermined devices 7 and 9 are outputted, and the buffer section 5 controls the control signal section 3. It is configured to receive and buffer a predetermined address signal and data output from the data processing section 1 in accordance with the signal, and the devices 7 and 9 are configured according to the control signal output from the control signal section 3. It consists of an address signal output from the buffer section 5 and a plurality of memories or device control apparatuses for receiving data.

The prior art structured as described above requires a data bus of the same size to exchange data between the data processing unit 1 and the devices 7 and 9 at the interface between the data processing unit and the peripheral device or memory type.

As shown in the drawing, the buffer unit 5 is provided between the data processing unit 1 and the devices 7, 9 for the purpose of simply switching the signal level. If the data size of the data processing unit 1 is 16 bits, the number of data input / output required for the interface with the data processing unit 1 of all memories and peripheral devices 3, 5, 7, and 9 should be 16 bits or 8 bits. . With this configuration, it is impossible for the 32-bit devices 7 and 9 to connect with the data processing unit 1.

As described above, if the data bus of the peripheral device for a specific purpose is large, the data size of the data processing unit for controlling the data does not necessarily have to match the size. If the data bus is 16 bits in length, the connection bus size between the buffer and the devices connected to it must be 16 bits or 8 bits in order to connect.

An object of the present invention is to solve the above problems of the prior art, by configuring a control logic and a buffer that can interface regardless of the size of the data bus between two different devices data bus that can exhibit the optimal system performance The present invention provides a resizing device.

In order to achieve the above object, the apparatus of the present invention comprises: a data processor for outputting data, an address signal and a control signal to control a predetermined device; A control signal generator for receiving and decoding a predetermined address signal and a control signal output from the data processor, and outputting a data direction control signal and a selection signal for selecting a predetermined device; A first buffer unit for receiving, buffering, and outputting predetermined data and address signals output from the data processing unit according to the control signal output from the control signal generator; A second buffer unit which receives, buffers and latches predetermined data output from the first buffer unit according to the control signal output from the control signal generator; An n-th buffer unit for receiving, buffering and latching predetermined data output from the first buffer unit according to the control signal output from the control signal generator; A first device receiving an address signal output from the first buffer unit and data output from the first or second buffer unit according to the selection control signal output from the control signal generator; And an n-th device configured to receive an address signal output from the first buffer unit and data output from the n-th buffer unit according to the selection control signal output from the control signal generator.

1 is a block diagram illustrating an interface circuit between a data processor and a peripheral device according to the related art.

2 is a block diagram illustrating an interface circuit between a data processor and a peripheral device according to an exemplary embodiment of the present invention.

3 is a detailed block diagram illustrating a structure of the first buffer of FIG. 2 according to the present invention.

4 is a detailed block diagram illustrating a structure of the second buffer of FIG. 2 according to the present invention.

5 is a timing diagram illustrating a read cycle of each circuit block of FIGS. 2 to 4.

Explanation of symbols on the main parts of the drawings

10: Microprocessor. 20: Control signal generator.

30: first buffer section 31: first aa buffer.

35: 1st buffer. 40: 2nd buffer part.

41: Latch 2a. 43: Buffer 2b.

45: latch 2c. 47: buffer 2d.

50: n-th buffer unit. 60: first device.

70: nth device.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

2 is a block diagram illustrating an interface circuit between a data processor and a peripheral device according to an exemplary embodiment of the present invention, wherein the data processor 10, the control signal generator 20, the first buffer unit 30, A second buffer portion 40, an nth buffer portion 50, a first device 60, and an nth device 70 are included.

On the other hand, the data processor 10 is configured to output data (a), address signal (b) and control signal (c) in order to control a predetermined device, and the control signal generator 20 is the data Receives and decodes a predetermined address signal (b) and a control signal (c) output from the processor 10, and selects a data direction control signal (d, h, k) and a selection signal (i, l) for selecting a predetermined device. Is configured to output

In addition, the first buffer unit 30 may output the predetermined data a and the address signal b output from the data processing unit 10 according to the control signal d output from the control signal generator 20. The second buffer unit 40 is configured to be input, buffered, and output, and the second buffer unit 40 is configured to output from the first buffer unit 10 according to the control signal h output from the control signal generator 20. The data buffer h is configured to receive, buffer, and latch the data h, and the n-th buffer unit 50 is configured to output the first buffer unit according to the control signal k output from the control signal generator 20. It is configured to receive, buffer and latch predetermined data f outputted at 30).

In addition, the first device 60 may include the address signal e and the first or the output signal from the first buffer unit 30 according to the selection control signal i output from the control signal generator 20. N-bit memory or a device control device for receiving data (f, g) output from the second buffer unit (30, 40), and the n-th device 70 is the control signal generator 20 N-bit memory or device receiving the address signal e output from the first buffer unit 30 and the data j output from the n-th buffer unit 50 according to the selection control signal l output from the It consists of a control device.

Meanwhile, in the exemplary embodiment of the present invention, the data processor 10 is 16 bits in size, the first device 60 is 32 bits in size, and the nth device 70 is an 8 bit device.

FIG. 3 is a detailed block diagram illustrating the structure of the first buffer of FIG. 2 according to the present invention, and includes a first buffer 31 and a first buffer 35. The present invention will be described with reference to FIG. Looking at it as follows.

Meanwhile, the first a buffer 31 may bidirectionally transmit data to the data processor 10 and the first device 60 according to the data direction and the control signal d-1 output from the control signal generator 20. The first b buffer 35 bidirectionally transfers data to the data processing unit 10 and the second buffer unit 40 according to the data direction of the control signal generator 20 and the control signal d-2. It is configured to transmit.

The data buses of the first and second buffers 31 and 35 and the data processor 10 have a 16-bit size, and the data bus sizes of the first a buffer 31 and the first device 60 are 32 bits and a first bus. The data bus size of the buffer 35 and the first device 60 is 16 bits.

In the first buffer unit 30 according to the present invention configured as described above, 16 bits of data from the data processing unit 10 are inputted to and output from the first buffer 31 and the first buffer 35, respectively. Basically, in order to interface with the 16-bit data processor 10 and the 32-bit device 60, the data processor 10 needs two cycles. In the first cycle, byte0 and byte1, which are the data0 to data15 portions of data, first cycle, and then byte2 and byte3 are performed.

4 is a detailed block diagram showing the structure of the second buffer of FIG. 2 according to the present invention, in which the 2a latch 41, the 2b buffer 43, the 2c latch 45, and the 2d buffer are shown. 47, the present invention will be described with reference to FIGS. 2 and 3 as follows.

Meanwhile, the second a latch 41 is configured to receive the data f-2 output from the first b buffer 35 according to the delayed control signal h-1 output from the control signal generator 20. Also, the second b buffer 43 receives the data f′-2 output from the second a latch 41 according to the control signal h-2 output from the control signal generator 20. And the second c latch 45 inputs the data g output from the second b buffer 43 according to the delayed control signal h-4 output from the control signal generator 20. The second d buffer 47 is configured to receive the data f ″ -2 output from the second c latch 45 according to the control signal h-3 output from the control signal generator 20. ) Is buffered and output to the input bus f-2 of the second a latch 41.

On the other hand, the data bus size between the second a latch 41 and the second b buffer 43 is 16 bits, the output data bus size of the second b buffer 43 is 32 bits, and the second c latch 45 And the data bus size between the 2d buffer 47 is 16 bits and the output data bus size of the 2d buffer 47 is 16 bits.

FIG. 5 is a timing diagram illustrating a lead cycle of each circuit block of FIGS. 2 to 4. The operation of the present invention will be described in detail with reference to FIGS. 2 to 4 and the drawings.

First, in order to read data, the data processing unit 10 outputs an appropriate address signal to the address bus signal line, decodes it in the control signal generator 20, and activates the chip select signal sel1 of the first device 60. Further, the read signal line rd is activated, and the data enable signal den and the data direction signal dtr are made active. Since this cycle is a read cycle, all signal lines d_2 (L), d_2 (E), h_1 (E), h_2 (D), and h_2 (E) associated with the write signal wr remain high.

Since the cycle operation of the data processing unit 10 is 16 bits, an address multiple of 2 is output (for example, the last address is always 0, 2, 4, 6, 8, a, c, e). For 32-bit operation, the data processor 10 needs two cycles of operation, so the last digit address of the first cycle is always 0, 4, 8, c, and the last digit address of the second cycle is always 2, 6, a, and e, so that an address signal line distinguishable from each other is determined by the value of a1. That is, if a1 is 0, the cycle is the first cycle, and if a1 is 1, the cycle is the second cycle.

The operation of each buffer and latch element will be described with reference to the timing diagram of the same drawing under the above condition.

The first buffer 31 is enabled when the data processor 10 performs the second cycle and when the data direction signal dtr and the data enable signal den have a specific value. It is a bidirectional data buffer, which is connected between data 0 to data 15 of the 32-bit data bus and the data bus of the data processing unit.

The first buffer 35 is the same as the first buffer 31 and connects data 16 to data 31 and the data bus of the data processor 10 in a 32-bit data bus.

The second 41a latch 41 serves to temporarily store the value of the output data bus of the first buffer Buffer 35 on the data processing unit 10 in order to preserve the values of data 0 to data 15 during the first write cycle. Preserving the value of any other cycle (eg interrupt) during and during the second cycle keeps the data value unchanged during the next cycle. Since the latch enable signal is an edge latch signal, the output value f'-2 of the 2a latch 41 is maintained.

The second 2nd buffer 43 is a buffer element that separates the buses f'-2 and g, and the 2db buffer 47 is a buffer element that separates the buses f ''-2 and f-2.

The second c latch 45 serves to temporarily store the value of the output data bus g of the first device 60 in order to preserve the values of data 0 to data 15 during the read cycle. Preserving the value of another cycle (eg interrupt) keeps the value of the data unchanged during the next cycle. Since the latch enable signal is an edge latch signal, the value of g is maintained.

To sum it up again, it is as follows.

First, during the read cycle, the first b buffer 35 is enabled and the direction of data is in the a direction at f-2 (S1), and at the same time, the second c latch 45 latches g (S2). The value f ″ -2 latched at S2 is input to the first buffer 35 with the 2d buffer 47 enabled (S3), and the bus on the side of the final data processor 10 is controlled by S1. The data values data0 to data15 are transferred to a (S4). The first 1a buffer 31 is enabled and the direction of data becomes a on the bus g (S5). By S5, the data values data16 to data31 are transferred to the bus a on the side of the final data processing unit 10 (S6).

Secondly, during the light cycle, the first b buffer 35 is enabled and the direction of data is in the f-2 direction on the bus a (S11), and at the same time, the second a latch 41 reads the data value of the bus f-2. It latches (S12). The value f'-2 latched in step S12 is input to the first buffer Buffer 35 by enabling the second buffer Buffer 43 (S13), and the bus a on the side of the final data processor 10 by S11. The data values data0 to data15 are transferred (S14). The first 1a buffer 31 is enabled and the direction of data is from bus a to g (S15). In step S15, the data value is transferred to the data bus data16 to data31 of the devices 60 and 70 on the bus a on the side of the final data processing unit 10 (S16).

Finally, when another cycle is entered during the lead cycle, the same process as S1 to S4 during the lead cycle is performed (S21), the process of S21 is performed, and another cycle is entered (S22), In the case of S22, the 2d buffer 47 is disabled but the value of f " -2 is continuously latched (S23). After the cycle of S22 is finished, processes S5 and S6 of the lead cycle are performed.

Therefore, as described above, in the present invention, an interface with a peripheral controller operating at high performance using a low-performance data processor has an effect of operating the system regardless of the size of the data bus.

Claims (5)

A data processor for outputting data, an address signal, and a control signal to control a predetermined device; A control signal generator for receiving and decoding a predetermined address signal and a control signal output from the data processor, and outputting a data direction control signal and a selection signal for selecting a predetermined device; A first buffer unit for receiving, buffering, and outputting predetermined data and address signals output from the data processing unit according to the control signal output from the control signal generator; A second buffer unit which receives, buffers and latches predetermined data output from the first buffer unit according to the control signal output from the control signal generator; An n-th buffer unit which receives, buffers and latches predetermined data output from the first buffer unit according to the control signal output from the control signal generator; And a device for receiving an address signal output from the first buffer unit and data output from the buffer unit according to a selection control signal output from the control signal generator. 2. The apparatus of claim 1, wherein the first buffer unit comprises: a first buffer configured to bidirectionally transmit data to a data processor and a first device according to a data direction and a control signal output from the control signal generator; And a 1b buffer configured to bidirectionally transmit data to the data processor and the second buffer according to the data direction and the control signal of the control signal generator. The method of claim 1, wherein the second buffer unit comprises: a second latch receiving data output from the first buffer according to the delayed control signal output from the control signal generator; A second b buffer receiving data output from the second a latch according to the control signal output from the control signal generator; A second c latch receiving data output from the second b buffer according to the delayed control signal output from the control signal generator; And a 2d buffer receiving and buffering data output from the second c latch according to the control signal output from the control signal generator and outputting the buffered data to the input bus of the 2a latch. . The device of claim 1, wherein the device receives an address signal output from the first buffer unit and data output from the first or second buffer unit according to a selection control signal output from the control signal generator. 1 device; And an n-th device configured to receive an address signal output from the first buffer unit and data output from the n-th buffer unit according to the selection control signal output from the control signal generator. . 5. An apparatus according to claim 1, wherein the bus for transmitting data is a bidirectional bus.