KR19980063955A - Semiconductor memory - Google Patents

Abstract

Provided is a semiconductor memory device having a column redundancy method with high defect repair efficiency without causing a significant increase in chip size.

In the DRAM of the overlay DQ bus type, the eight cell array block group on the upper side of the row decoder 24 is defined as the cell array block group 10-1, and the eight cell array blocks below the row decoder. The group is referred to as the cell array block group 10-2. Spare column groups 11-1 and 11-2 are provided adjacent to each of the cell array block groups 10-1 and 10-2. Each of the 64 multiplexers receiving the outputs of the DQ buffer 13-1 (13-1 (0) to (31)) and 13-2 (13-2 (0) to (31)), respectively, is a 3-to-1 multiplexer ( 34 (34-0 to 63)), and the defective column of the cell array block group 10-1 can be replaced in both the spare column groups 11-1 and 11-2.

Description

Semiconductor memory

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the architecture of semiconductor memories, and more particularly to semiconductor memory circuits applied to DRAMs having a multi-bit output with an overlay-DQ bus.

Fig. 12 is a circuit block diagram showing a main part of an overlay DQ bus type 4M bit DRAM. In this example, 16 memory cell arrays having 256 rows and 1024 columns are arranged in units of blocks (referred to as cell array blocks) to form 4M bit DRAM. Of the 16 cell array blocks, two cell array blocks (e.g., indicated by diagonal lines) interposed between the row decoders 24 are simultaneously activated. The selection of the cell array to be activated is performed by the upper three bits (AR8 to 10) of the row address signal inputs (11 bits of AR0 to AR10).

In Fig. 12, the eight cell array block groups on the upper side of the row decoder 24 are referred to as cell array block groups 10-1, and the eight cell array block groups on the lower side of the row decoder 24 are referred to as cell array block groups. It is set to (10-2). The spare column group 11-1 which consists of four columns in which spare memory cell rows are arrange | positioned adjacent to the cell array block group 10-1 is provided. The spare column group 11-2 which consists of four spare columns in which spare memory cell rows are arrange | positioned adjacent to the cell array block group 10-2 is provided.

The spare column group 11-1 is a column redundancy selected in place of the defective column when a defective column exists in the cell array block group 10-1. The spare column group 11-2 is a column redundancy selected in place of the defective column when a defective column exists in the cell array block group 10-2.

256 pairs of DQ buses (regular DQ buses; DQ0 to 255, / DQ0 to 255 and DQ256 to 511, / DQ256 to 511) Similarly, the leading / is attached to the bar in the figure) is provided along the column direction above each of the cell array block groups 10-1 and 10-2. Further, on the upper side of each of the spare column groups 11-1 and 11-2, a pair of spare DQ buses S1DQ, / S1DQ and S2DQ, / S2DQ are provided along the column direction. These DQ buses are electrically connected to the columns of each cell array block through column switches described later in order to read column data in accordance with the column address signal input.

Thus, the structure which arrange | positioned the DQ bus in the form which overlaps a cell array is called the overlay DQ bus architecture. This overlaid DQ bus architecture has a configuration in which the chip size is not increased as much as possible, and at the same time, a large number of DQ buses can be connected to the activated cell array block. Suitable for DRAM with multiple bit outputs.

The DQ bus (512 pairs in total) includes multiplexers 12-1 and 12-2 (8-to-1 multiplexers 12-1 (0) to (31) and 12-2 (0) to (31)) and DQ. Buffers 13-1, 13-2 (13-1 (0) to (31), 13-2 (0) to (31)), and two-to-one multiplexers 14-1 (0) to (31), It is connected to 64 pairs of RWD buses through 14-2 (0) to (31) .. This RWD bus exchanges 64-bit I / O data with the outside of memory via the data input / output buffer 15.

On the other hand, the spare DQ buses S1DQ and / S1DQ are connected in parallel so as to be one input of each of the two-to-one multiplexers 14-1 (0) to (31) through the spare DQ buffer 16-1. The spare DQ buses S2DQ and / S2DQ are connected in parallel so as to be one input of each of the two-to-one multiplexers 14-2 (0) to (31) through the spare DQ buffer 16-2.

The two-to-one multiplexers 14-1 (0) to (31) and 14-2 (0) to (31) are 64-bit signals SH1 (0) to generated by the spare column hit determination circuit 17. (31) and SH2 (0) to (31) control whether to select a regular DQ bus and a DQ buffer or a spare DQ bus and a spare DQ buffer. The spare column hit determination circuit 17 performs the above control depending on whether or not the input column address signals AC0 to 4 coincide with the bad column addresses programmed in advance.

FIG. 13 is a circuit block diagram showing in more detail a portion from the cell array block of FIG. 12 to the RWD bus on the data input / output side, showing the cell array block group 10-1 side (spare column group 11-1). Inclusively). In Fig. 13, the spare column group 11-1 includes four spare column pairs S1BL (0) to (3) and / S1BL (0) to (3) to which a plurality of memory cells (not shown) are connected. Are connected to a pair of spare DQ buses S1DQ and / S1DQ via column switches. The four spare column pairs are selected by the spare column switch select signals S1SW (0) to (3). S / A is a sense amplifier.

In a regular cell array block, a DQ bus is provided at a ratio of one pair for four column pairs. That is, 256 pairs of DQ buses are arranged corresponding to 1024 column pairs in the cell array block. Four column pairs BL0 to 3 and / BL0 to 3 are connected to a pair of DQ buses (for example, DQ0 and / DQ0) via column switches.

The four column pairs are selected by the column switch select signals SW0 to 3. As shown in FIG. 13, the column switch selection signals SW0 to 3 are three for selecting AC0, AC1 (internal column address signals AC0I and AC1I) and cell array blocks of the least significant two bits of the column address signal. The bit is decoded by the logical product of the row address signals AR8, AR9, AR10 (internal row address signals are indicated by AR8I, AR9I, AR10I). In addition, ACiI, / ACiI (i = 0, 1), ACRjI, / ARjI (j = 8, 9, 10) have the column address buffer 25 more than the input of the column address signals AC0 to AC4 of FIG. The partial compensation signal generated by the row address buffer 22 is a part of the generated partial compensation signal and the input of the row address signals AR0 to AR10.

256 pairs of DQ buses on a cell array block are multiplexed by 8 to 1 multiplexers every 8 pairs. For example, the DQ buses DQ0 to 7 and / DQ0 to 7 in Fig. 13 are multiplexed by an 8 to 1 multiplexer 12-1 (0).

In the eight-to-one multiplexer 12-1 (0) to (31) and 12-2 (0) to (31), any one of eight pairs of DQ bus pairs is selected by three-bit selection signals (DQMUX0 to 2). Decide if Here, DQMUX0 to 2 are allocated the upper 3 bits (AC2 to 4) of the 5 bits of the column address signal. In other words, DQMUX0 to 2 correspond to internal column address signals AC2I to AC4I, respectively. For example, the outputs DQIN0 and / DQIN0 of the 8-to-1 multiplexer 12-1 (0) are input to the DQ buffer 13-1 (0), and the output DQOUT0 is a 2-to-1 multiplexer ( 14-2 (0)). The two-to-one multiplexer 14-2 (0) selects and outputs the output S1DQOUT of the spare DQ buffer 16-1 when the select signal SH1 (0) is at a high level, and selects DQOUT0 at a low level. Selective output is sent to the RWD bus.

The above configuration is similarly configured on the cell array block group 10-2 side (including the spare column group 11-2), and 64-bit signals are applied to both the cell array block group 10-1 side and the 10-2 side. Is sent to the RWD bus (see FIG. 12).

FIG. 14 is a circuit block diagram showing the configuration of the spare column hit determination circuit 17 in FIG. Eight address hit determination circuits corresponding to eight spare columns in total of the spare column groups 11-1 and 11-2 (171; 171-1 (0) to (3), 171-2 (0) to (3) ) And 64 multiplexer control signal generation circuits 172 (172-1 (0) to (31) and 172-2 (0) to (31)) corresponding to 64 two-to-one multiplexers in total.

15 and 16 are circuit diagrams showing the DQ buffer and spare DQ buffer selection circuit 28 for generating activation signals for the spare DQ buffer and the DQ buffer in FIG. 15 each has an OR gate configuration. If any one of S1SW (0) to (3) is at the high level (spare column hit), the signal RES1 rises and the spare DQ buffer 16-1 is activated. If any of S2SW (0) to (3) is at the high level (spare column hit), the signal RES2 rises to activate the spare DQ buffer 16-2.

Fig. 16 shows control signals SH1 (0) to (31) and SH2 (0) of the two-to-one multiplexer 14 (14-1 (0) to (31) and 14-2 (0) to (31)). Inverting (31) to generate an active high DQ buffer activation signal RE1 (0) to RE1 (31) and RE2 (0) to RE2 (31). For example, if SH1 (0) is at high level, since SH1 (1) to 31 are at low level, RE1 (0) is at low level and RE1 (1) to RE1 (31) is at high level. As a result, only the DQ buffer 13-1 (0) in FIG. 13 is inactivated, and an increase in current consumption due to unnecessary DQ buffer activation can be prevented.

As described above, the spare column hit determination circuit, the DQ buffer, and the spare DQ buffer generation circuit activate the spare column and the spare DQ buffer only when a bad column address is input, and control the two-to-one multiplexer to output the bad column. By replacing only the DQ buffer output corresponding to the line with the spare DQ buffer output, the memory circuit in which the bad column exists can be saved. In addition, in the above description, the structure which replaces the defective column of the cell array block group 10-1 (it has output numbers 0-31 as a corresponding input / output path) by the spare column of the spare column group 11-1 was shown. The same applies to a configuration in which a defective column of the cell array block group 10-2 (having output numbers 32 to 63 as corresponding input / output paths) is replaced with a spare column of the spare column group 11-2.

The configuration has the following problems. The spare column group 11-1 can replace the defective column only with respect to the cell array block group 10-1. In addition, the spare column group 11-2 can replace the defective column only with respect to the cell array block group 10-2. Therefore, when a defect concentrates in a specific cell array block group, there is a fear that the spare column prepared for the cell array block group will not be replaced.

In the above example, even though eight spare columns are prepared in all of the spare column groups 11-1 and 11-2, for example, if more than four defective columns exist in the spare column group 11-4, the relief is impossible. It is done.

As described above, in the conventional column redundancy technique, a spare column group that can function for each cell array block group is individually determined, and the spare column group corresponding to one cell array block group is shared with other adjacent cell array block groups. The configuration is impossible. As a result, there was a problem that the defect relief effect by column redundancy was low.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor memory circuit having a column redundancy method with high defect repair efficiency without causing a significant increase in chip size.

The semiconductor memory circuit of the present invention comprises a first memory cell array formed by arranging memory cells in a matrix in the row and column directions, and a memory cell arranged in matrix in a row and column directions. A second memory cell array activated simultaneously with the array, a first and second spare memory cell groups adjacent to the first and second memory cell arrays, and a column direction corresponding to the first and second memory cell arrays A plurality of data lines arranged in a row, at least one first and second spare data lines disposed in a column direction corresponding to the first and second spare memory cell column groups, respectively, and substituted with the data lines; When the address of the data line corresponding to the defective memory cell in the two memory cell arrays is stored and an external address signal is input, the external address signal A control circuit for transmitting a control signal for selecting and controlling the data line corresponding to the data line and the first or second spare data line, and the first or second spare data line corresponding to the external address based on the control signal; A selection control circuit for selecting a data line not being replaced, a data line corresponding to the external address, and a first or second spare data line to be replaced and sending out data of the memory cell according to the external address signal; The data line may be replaced with both the first and second spare data lines.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a circuit block diagram showing an essential part of an overlay DQ bus type 4M bit DRAM according to an embodiment of the present invention.

FIG. 2 is an essential part of the invention and is a circuit block diagram showing in more detail a portion from the cell array block of FIG. 1 to the RWD bus on the data input / output side. FIG.

3A, 3B, and 3C are circuit block diagrams showing the configuration of the spare column hit determination circuit in FIG.

FIG. 4 is a circuit diagram showing the address hit determination circuit of FIG.

FIG. 5 is a circuit diagram showing a configuration of the multiplexer control signal generation circuit in FIG. 3B. FIG.

6 is a circuit diagram showing the configuration of an activation signal control circuit to the spare DQ buffer shown in FIG. 1;

FIG. 7 is a circuit diagram showing a configuration of an activation signal control circuit to the DQ buffer in FIG. 1; FIG.

FIG. 8 is a circuit diagram showing a three-to-one multiplexer shown in FIG. 1 (or FIG. 2).

FIG. 9 is a first waveform diagram for explaining the operation of the address hit determination circuit in FIG. 4; FIG.

FIG. 10 is a second waveform diagram for explaining the operation of the address hit determination circuit in FIG. 4; FIG.

Fig. 11 is an operational waveform diagram of a multiplexer control signal generation circuit in which a fuse is cut.

Fig. 12 is a circuit block diagram showing a main part of an overlay DQ bus type 4M bit DRAM.

FIG. 13 is a circuit block diagram showing in more detail a portion from the cell array block of FIG. 11 to the RWD bus on the data input / output side. FIG.

FIG. 14 is a circuit block diagram showing the configuration of the spare column hit determination circuit in FIG.

FIG. 15 is a circuit diagram showing a configuration of an activation signal control circuit to the spare DQ buffer in FIG.

FIG. 16 is a circuit diagram showing a configuration of an activation signal control circuit to the DQ buffer shown in FIG.

Explanation of symbols for the main parts of the drawings

10-1, 10-2: cell array block group

11-1, 11-2: spare column group

12-1, 12-2: Multiplexer (8-to-1 Multiplexer)

13-1, 13-2: DQ Buffer

15: data input / output buffer

16-1, 16-2: spare DQ buffer

21: low system control circuit

22: row address buffer

23: Low Free Decoder

24: low decoder

25: column address buffer

26: column control circuit

27: column-free decoder

34-0 to 63: multiplexer (3 to 1 multiplexer)

37: spare column hit determination circuit

38: DQ buffer spare DQ buffer selection circuit

1 is a circuit block diagram showing a main portion of an overlay DQ bus type 4M bit DRAM according to an embodiment of the present invention. In such a configuration, as in FIG. 12, 16 cell array blocks consisting of 256 rows and 1024 columns are arranged to form a 4M bit DRAM. Of the 16 cell array blocks, two with a row decoder are activated at the same time. The selection of the activated cell array is performed by the upper three bits (AR8 to 10) of the input row addresses (11 bits of AR0 to AR10). The same code | symbol is attached | subjected to the place similar to FIG. The leading / in the text is attached with a bar above in the drawing as described above.

FIG. 1 has the following constitution as compared with FIG. 12. Each of the 64 multiplexers that receive the outputs of the DQ buffers 13-1 (13-1 (0) to (31) and 13-2 (13-2 (0) to (31)), respectively, is a 3-to-1 multiplexer (34). (34-0 to 63) The outputs of the normal DQ buffer 13-1 or 13-2 connecting the corresponding normal data lines to the three input terminals of the multiplexer 34 as described above. The outputs of the first spare DQ buffer 16-1 connecting the first spare data line and the outputs of the second spare DQ buffer 16-2 connecting the second spare data line are input.

The spare column hit determination circuit 37 also generates signals (SSW0-7, SH-0-63, SHA-0-63, SHB-0-63) necessary for the control of the DQ buffer and the multiplexer 34. . The structure is also mentioned later.

In the related art, the defective column in the cell array block group 10-1 can be replaced only with the spare column in the spare column group 11-1, and the defect relief efficiency is lowered. The circuit configuration involving the multiplexer 34 makes it possible to replace the defective column in the cell array block group 10-1 in any of the spare column groups 11-1 and 11-2. Of course, the defective column of the cell array block group 10-2 can be replaced in any of the spare column groups 11-1 and 11-2. As a result, the rescue efficiency of the defective memory is greatly improved. Moreover, even if it is set as such a structure, since a spare column group does not increase, the advantage of not largely increasing a chip size like FIG. 12 is inherited.

FIG. 2 is an essential part of the present invention, and is a circuit block diagram showing in more detail a portion from the cell array block of FIG. 1 to the RWD bus on the data input / output side, showing the cell array block group 10-1 side (spare column group). (11-1) is also representative). The three-to-one multiplexer 34 (34-0 to 63 respectively) is controlled by three signals of SH-i, SHA-i, and SHB-i (i = 0 to 31). Although described later, the three input terminals of the multiplexer 34, the output of the normal DQ buffer 13-1 or 13-2, and the first by these control signals SH-i, SHA-i, SHB-i. The output of either the output of the spare DQ buffer 16-1 or the output of the second spare DQ buffer 16-2 is selected.

For other configurations, the names of the signals are only slightly different, and they are not basically changed from FIG. The spare column group 11-1 is composed of four spare column pairs SBL0 to 3 and / SBL0 to 3, and a pair of spare DQ buses (through the column switch controlled by the selection signals SSW0 to 3) SDQ, / SDQ). The spare column group 11-2 is composed of four spare column pairs SBL4-7 and / SBL4-7, and a pair of spare DQ buses (SDQ) are connected through column switches controlled by the selection signals SSW4-7. , / SDQ).

In a regular cell array block, a DQ bus is provided at a pair ratio for four column pairs. That is, 256 pairs of DQ buses are arranged corresponding to 1024 column pairs in the cell array block. Four column pairs BL0 to 3 and / BL0 to 3 are connected to a pair of DQ buses (for example, DQ0 and / DQ0) via column switches.

Here, four column pairs are selected by the column switch selection signals SW0 to 3. As shown in Fig. 2, the column switch selection signals SW0 to 3 are the lowest two bits (AC0, AC1 (internal column address signals AC0I and AC1I)) of the column address signal and three bits for selecting the cell array block. Is decoded by the logical product of the row address signals AR8, AR9, AR10 (internal row address signals AR8I, AR9I, AR10I).

256 pairs of DQ buses on a cell array block are multiplexed every 8 pairs by an 8-to-1 multiplexer. For example, the DQ buses DQ0-7 and / DQ0-7 in FIG. 2 are multiplexed by an 8 to 1 multiplexer 12-1 (0).

In the eight-to-one multiplexer 12-1 (0) to (31) and 12-2 (0) to (31), which DQ bus pair from among eight pairs is selected by the three-bit selection signal (DQMUX0 to 2). Determine. Here, DQMUX0 to 2 are allocated the upper three bits (AC2 to 4) of the five column address signal bits (DQMUX0 to 2 correspond to internal column address signals AC2I to AC4I, respectively).

The outputs of the eight-to-one multiplexers are input to the DQ buffers 13 (13-1 (0) to 31, 13-2 (0) to (31)), and each output thereof corresponds to a corresponding three-to-one multiplexer ( To 34 (34-0 to 63). A 64-bit signal is sent to the RWD bus in accordance with the cell array block group 10-1 side and 10-2 side.

3A, 3B, and 3C are circuit block diagrams showing the configuration of the spare column hit determination circuit 37. Eight address hit determination circuits 371 (371-0 to 7) corresponding to eight spare columns in total of the spare column groups 11-1 and 11-2, and a total of 64 two-to-one multiplexers 34 respectively. 128 multiplexer control signal generation circuits 372 (372-1 (0) to (63), 372-2 (0) to (63)) provided to match SHA and SHB signals to the multiplexer control signal generation circuit ( NAND gates 373 (373-0 to 63) for outputting another control signal generated at the outputs SHA-0 to 63 of 372.

4 and 5 respectively show the configuration of the address hit determination circuit 371 of FIG. 3A and the multiplexer control signal generation circuit 372 of FIG. 3 among the spare column hit determination circuits 37 of FIG. 1. This is a circuit diagram. 8 address hit determination circuits are provided for the signal outputs SSW0-7. Here, the signal output SSW0 is represented typically. The fuse FS is cut and programmed in advance so that there is no ground bus only when a column address signal corresponding to a bad column is input.

In addition, 128 multiplexer control signal generation circuits are provided for the signal outputs SHA-0 to 63 and SHB-0 to 63. FIG. Here, the signal output SHA-0 is shown as representative. Each has a bit program circuit BPC, and each output and each output of the spare column hit determination circuit 37 (here, SSW0 to 3, and SSW4 to 7 for signal outputs SHB-0 to 63). This configuration reflects the NAND logic of. When the column address signal corresponding to the bad column is inputted, SHA-1 goes low when the fuse is blown to the bit program circuit.

6 and 7 are circuit diagrams showing the configuration of the selection circuit 38 for generating an activation signal to the spare DQ buffer and the DQ buffer in FIG. 5 has an OR gate structure, respectively. When any one of SSW0 to 3 is at the high level (spare column hit), the signal RES1 rises to activate the spare DQ buffer 16-1. If any of SSW4 to 7 is at the high level (spare column hit), the signal RES2 rises to activate the spare DQ buffer 16-2.

FIG. 8 is a circuit diagram showing the three-to-one multiplexer 34 shown in FIG. 1 (or FIG. 2). Normal DQ buffer 13-1 or 13-2 by pass gates PG1 to 3 controlled by control signals SH-i, SHA-i and SHB-i (i = 0 to 63), respectively. ), One of the output of the first spare DQ buffer 16-1, and one of the output of the second spare DQ buffer 16-2 is selected and output.

3 to 5, the multiplexer selects the output from the regular DQ buffer when SH-i is at low level and SHA-i and SHB-i are at high level. In addition, when SH-i and SHB-i are high level and SHA-i is low level, the output of the spare DQ buffer 16-1 is selected. In addition, when SH-i and SHA-i are high level and SHB-i is low level, the output of the spare DQ buffer 16-2 is selected.

Next, the replacement operation of the spare column with respect to the defective column according to the configuration of the present invention will be described. For example, assume that the bit line BL1 of the cell array block group 10-1 of FIG. 2 is a bad column. The column address of BL1 is 00001 (AC0 = 1, AC1 to AC4 = 0). Instead of this defective BL1, the spare columns SBL0 and / SBL0 are programmed to be replaced to provide normal function.

That is, in the address hit determination circuit 371-0 of FIG. 3, the fuse corresponding to AC0I, / AC1I to / AC4I shown in FIG. 4 is cut off, and the defective column address is programmed. Since the defective BL1 corresponds to the DQ buffer of output number 0 as the corresponding input / output path, the spare column switch selection signal shown in FIG. 5 in the multiplexer control signal generation circuit 372-1 (0) of FIG. The fuse FS of the bit program circuit corresponding to SSW0) is cut off and the output number corresponding to the corresponding input / output path of the defective column is programmed.

The operation of the address hit determination circuit of FIG. 4 will be described with reference to FIGS. 9 and 10. First, Fig. 9 is an operation when the input address signal (00000 in this example) does not coincide with the programmed bad address signal (00001). After the inversion signal CASint of / CAS is raised, the node NA in FIG. 4 is lowered to the low level by the NMOS transistor (NMOS) which inputs / AC0I as a gate at the high level of the initial state, so that SSW0 is also low. Print the level. Since SSW0 is the column switch signal (active high) of the spare column, the spare column is not selected in this case.

Thus, the signals SAH-0 and SBH- from the multiplexer control signal generation circuit (shown in FIG. 3) 372-1 (0) and 372-2 (0) through the corresponding bit program circuit BPC (shown in FIG. 5). 0 goes high and the multiplexer selects regular DQOUT0.

Next, a case may be considered in which an address signal such as the programmed bad address signal 0001 is input (FIG. 10). At this time, AC0I and / AC1I to / AC4I become high level after CASint is raised, but node N4 in FIG. 4 is not lowered to low level because of the blown fuse, and SSW0 outputs a high level. Thus, the column switches of the spare columns SBL0 and / SBL0 in FIG. 2 are selected.

Next, the multiplexer control signal generation circuit of FIG. 3 will be described with reference to FIGS. 5 and 11. Fig. 11 is an operational waveform diagram of the multiplexer control signal generation circuit 372-1 (0) with the fuse blown. Since the fuse is disconnected after CASint rises from the low level to the high level, the node NC in the bit program circuit of FIG. 5 remains at the high level, and since the SSW0 is the high level output, the node NC is low. Transitions to a high level. Therefore, SHA-0 goes down.

Here, in Fig. 3, since the fuse is not blown with respect to the multiplexer control signal generation circuits 372-1 (1) to 372-2 (0) to 31, the node NB in Fig. 5 is at a low level. Falls into. Therefore, SHA-1 to 63 and SHB-0 to 63 are at a low level. Therefore, in the two-to-one multiplexer 34 of FIG. 8, the spare column output SDQOUT from the spare DQ buffer 16-1 is transferred to the RWD bus instead of DQOUT0 connected to the bad column.

In Fig. 6, SSW0 is at high level, RES1 is at high level, and spare DQ buffer 16-1 is in an active state. In addition, in FIG. 3C, only SHA-0 is low level, only SH-0 is high level, so that only signal RE0 is low level in FIG. 7, and the DQ buffer 13-0 is connected to the bad column of FIG. Becomes inactive. As a result, it is possible to prevent an increase in current consumption due to unnecessary DQ buffer activation. Otherwise, if a bad column does not exist, the two-to-one multiplexers 34-1 to 63 select an output connected to a normal normal column and are transferred to the RWD bus.

Next, the case where BL0 shown in FIG. 2 is a defective column and this is struck by SBL4 of the spare column group 11-2 will be described. At this time, the address hit determination circuit 371-4 in Fig. 3 is programmed with the column address corresponding to the defective BL0 in the above-described method. The fuse of the bit program circuit corresponding to SSW4 of the multiplexer control signal generation circuit 372-2 (0) may be cut off.

In this way, when the bad column address is input from the outside, the signal SSW4 becomes high during the operation of the address hit determination circuit 371 of FIG. In the figure, SSW4 goes high and RES2 goes high, and spare DQ buffer 16-2 is active. Thereby, the columns SBL4 and / SBL4 of the spare column group 11-2 are selected.

In addition, at the high level of SSW4, the output SHB-0 of the multiplexer control signal generation circuit 372-2 (0), which is blown by the fuse of the bit program circuit, becomes low level. In Fig. 3C, only SHB-0 is low level, and only SH-0 is high level. As a result, only the signal RE0 becomes low in FIG. 7, and the DQ buffer 13-1 (0) connected to the bad column of FIG. 2 is inactivated (prevention of unnecessary current increase due to unnecessary DQ buffer activation). Contributes to).

As a result, the spare column output SDQOUT from the spare DQ buffer 16-2 is transferred to the RWD bus instead of DQOUT0 connected to the bad column. Otherwise, if there are no bad columns, the two-to-one multiplexers 34-1 to 63 select an output connected to a normal canonical column and transfer it to the RWD bus.

According to the above configuration, even if the address signal inputted from the outside corresponds to any defective memory cell sequence among the cell address block groups 10-1 and 10-2, the spare memory cell sequence 11-1 and 11-2 are replaced. Since the circuit is configured to be possible, the defect relief efficiency is improved. In addition, the defect repair efficiency is improved, but the circuit size such as a spare column which is directly related to column redundancy does not necessarily need to be increased, so that the chip size is not significantly increased.

As described above, according to the present invention, a spare column group that can function for each cell array block group is not individually determined, but can be shared for other cell array block groups. A high degree of freedom column redundancy technology is provided, and as a result, it is possible to provide a semiconductor memory device having high rescue efficiency of defective memory without causing a significant increase in chip size.

Claims (6)

A first memory cell array formed by arranging the memory cells in a matrix in the row and column directions; A second memory cell array formed by arranging the memory cells in a matrix in a row and column direction and being activated simultaneously with the first memory cell array; A group of first and second spare memory cells adjacent to the first and second memory cell arrays, respectively; A plurality of data lines arranged in a column direction corresponding to the first and second memory cell arrays; At least one first and second spare data lines disposed in column directions corresponding to the first and second spare memory cell column groups, respectively, and substituted with the data lines; An address of a data line corresponding to a bad memory cell of the first and second memory cell arrays is stored, and when an external address signal is input, the data line corresponding to the external address signal and the first or second spare data line are selected. A control circuit for transmitting a control signal for controlling; A data line not substituted with the first or second spare data line corresponding to the external address based on the control signal, and a first or second spare data line substituted with the data line corresponding to the external address. Select control circuit for transmitting data of a memory cell according to the external address signal And And said data line is replaceable with both said first and second spare data lines. The signal control circuit of claim 1, wherein the selection control circuit is configured to perform at least one of a signal for selecting the first spare data line, a signal for selecting and controlling the second spare data line, and a signal for selecting and controlling the data line. And a multiplexer circuit for selecting one of a data line and said first and second spare data lines. The circuit of claim 1, wherein the selection control circuit A buffer circuit for selecting a data line corresponding to the external address from a plurality of data lines provided in the first and second memory cell arrays; A first spare buffer circuit for selecting the first spare data line; A second spare buffer circuit for selecting the second spare data line; The buffer circuit, the first and second spares in at least a signal for selective control of the first spare data line, a signal for selective control of the second spare data line, and a signal for selective control of the data line And a multiplexer circuit for selecting one of a data line selected by the buffer circuit and one of the first and second spare data lines. The semiconductor memory device according to any one of claims 1 to 3, wherein the first and second memory cell arrays each constitute a plurality of memory cell array block groups. The semiconductor memory device according to claim 1, wherein the memory cell constitutes a memory cell of a DRAM. A memory cell array formed by arranging the memory cells in a matrix in the row and column directions; A second memory cell array formed by arranging the memory cells in a matrix in a row and column direction and being activated simultaneously with the first memory cell array; A group of first and second spare memory cells spaced apart from each other; A plurality of data lines arranged in a column direction corresponding to the first and second memory cell arrays; At least one first and second spare data lines disposed in column directions corresponding to the first and second spare memory cell column groups, respectively, and substituted with the data lines; An address of a data line corresponding to a bad memory cell among the first and second memory cell arrays is stored, and when an external address signal is input, the data line corresponding to the external address signal and the first or second spare data line are selected. A control circuit for transmitting a control signal for controlling; On the basis of the control signal, a data line not substituted with the first or second spare data line corresponding to the external address, and a first or second spare data line substituted with the data line corresponding to the external address; And a selection control circuit for selecting and sending data of the memory cell according to the external address signal, And the data line is replaceable with any one of the first and second spare data lines.