KR19980055986A - Asynchronous transfer mode cell connection mapping device - Google Patents

Abstract

The present invention relates to an ATM cell connection mapping apparatus for performing connection processing of an input ATM cell in a reassembly, demultiplexing, or switching circuit of an ATM layer processing system. The ATM cell connection mapping apparatus includes: a cell connection memory having a hash table; A cell link mapping control block for outputting the base address of the cell-connected memory generated by performing a hash function on the VPI / VCI of the ATM cell, and when the VPI / VCI of the ATM cell is compared with the data in the internal cache. A cache block for generating a target address for directly designating a location where the hash bucket chain of the cell-connected memory is stored and directly outputting the cell-connected memory to the cell-connected memory unit, and using a base address from the cell-linked mapping control block, Accesses the location where the hash bucket chain is stored, or from the cache block Access the location where the hash bucket chain of the cell-connected memory is stored by using a target address, and sequentially compare the entry of the accessed hash bucket chain with the VPI / VCI of the ATM cell and compare the VC table corresponding to the VPI / VCI. Means for finding.

Description

Asynchronous transfer mode cell connection mapping device

The present invention relates to a hierarchical processing system of an asynchronous transfer mode (ATM) cell, and more particularly, to the connection of input ATM cells in a reassembly, demultiplexing or switching circuit of an ATM cell hierarchical processing system. The present invention relates to an ATM cell connection mapping apparatus that performs) processing.

In general, the ATM method is a technique for fast multi-switching by splitting information into short cells of fixed length attached with headers. The ATM method is a technique for multi-switching data at high speed by dividing information into units of fixed-length short cells attached to a header. The header includes a destination of data to be transmitted. Multiple exchanges of cells

1 is a diagram illustrating a structure of a cell for a general asynchronous transmission mode, GFC (10), VPI (20), VCI (30), PTI (40), RES (50), CLP (60), HEC (70) It includes.

The GFC 10 is a part for controlling a call flow occurring in each terminal, and has a size of 4 bits. The VPI 20 is configured as 8 bits as a part indicating a path of a cell, and the VIC 30 is a cell. It is a 16-bit size that indicates the destination of.

The PTI 40 has a size of 2 bits as a part for discriminating whether it is user information or network related information, the RES 50 has a size of 1 bit as a reserved field, and the CLP 60 removes a cell. It indicates the priority of the city and has a size of 1 bit.

In addition, the HEC 70 is configured to have an 8-bit size as a part used for error checking of the header and cell synchronization.

Therefore, in the asynchronous transmission mode, the destination of the data to be transmitted is distinguished by the above-described cell header composed of 40 bits, i.e., 5 bytes.

In the asynchronous transmission mode cell configured as described above, in consideration of all the values that the VPI 20 and the VCI 30 can have, since the user network interface (UN) has 8 bits and 16 bits, respectively, VPI and The number of channels that can be configured using VCI is 2 ²⁴ = 16 mega. Therefore, since it is impossible to predict the assigned VPI and VCI, the receiving side should have control and processing information for all inputtable channels, and must quickly find the information position of the corresponding channel every cell input.

The ATM cell layer processing system utilizes a cell mapping scheme for identifying cells in order to locate the information of the corresponding channel. Such a cell mapping apparatus includes a memory address method for setting an address corresponding to a total channel allocated by UNI, a sequential access method for assigning an address only to a channel currently being used, and contents stored instead of an address of a memory or Various methods have been proposed, such as a method using a content addressable memory (CAM) addressed by data.

However, the general memory system has a disadvantage in that a large capacity memory is used because the processing speed is high but an address must be allocated to a channel not used in the UNI.

Secondly, the sequential access method can be implemented with an appropriate size of memory, but it has a disadvantage in that the processing speed is slow because all the allocated addresses must be compared sequentially to find the same address with the input VPI / VCI information. .

Third, the shortcomings of the general memory method and the sequential access method described above are compensated for, resulting in a fast processing speed and a small memory capacity. However, there is a disadvantage in that the CAM is not cost effective because it is an expensive component.

Therefore, an object of the present invention is to provide a cell connection mapping apparatus capable of cell identification using a general memory.

1 is a diagram illustrating a configuration of an asynchronous transmission mode cell.

2 is a block diagram of an asynchronous transmission mode cell connection mapping apparatus according to a preferred embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

100: cell connection mapping control block 110: cell connection cache block

120: hash function block 130: function selection register

140: multiplexer 200: cell connection memory unit

210: hash table 220: hash bucket chain

230: VC table 300: mapping controller

According to the present invention for achieving the above object, a cell connection memory having a hash table and a cell connection mapping for outputting the base address of the cell connection memory generated by performing a hash function on the VPI / VCI of the ATM cell A cache that generates a target address that directly designates a location where the hash bucket chain of the cell-connected memory is stored when the control block and the VPI / VCI of the ATM cell are compared with data in an internal cache, and directly outputs the target address to the cell-connected memory unit. A hash bucket chain of the cell-connected memory using a block and a base address from the cell-linked mapping control block to access a location where the hash bucket chain of the cell-connected memory is stored, or a target address from the cache block. Access this stored location to access the entry of the accessed hash bucket chain. A cell mapping unit connected to the group ATM cells includes means to find the VC table corresponding to the VPI / VCI as compared to the VPI / VCI and the sequence is provided.

The above and other objects and various advantages of the present invention will become more apparent from the preferred embodiments of the present invention described below with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2, a block diagram of an ATM cell connection mapping apparatus according to a preferred embodiment of the present invention is shown. The cell connection mapping apparatus includes a cell connection mapping control block 100, a cell connection memory unit 200, and a mapping controller 300.

The cell connection mapping control block 100 includes a cache block 110 composed of a cell connection cache 12 and a cache controller 114, a hash function block 120 having a plurality of hash functions, a hash function selection register 130, Multiplexer 140, hash table / base register 150, adder 160, and target address selector 170 are provided.

The cell connection mapping control block 100 processes the VPI / VCI of the input ATM cell by using an internal cache, simultaneously using the selected hash function to obtain the result simultaneously with the cache access, and the cell connection upon a cache miss. Access the memory 200.

The cell-connected memory unit 200 composed of SRAMs specifies a target address that designates a hash bucket chain 220 having a plurality of entries for the VC table 230 each having processing information for one channel. It consists of a hash table 210 having a bucket pointer field 214 for storing and a depth field 212 for storing the physical address of the bucket pointer field 212.

The mapping controller 300 records the selected information in an internal register of the cell-linked mapping control block 100, reads the information from the cell-connected memory unit 200, determines the hash function selection information, linear-array-length, and the cell. In the hash table / base register 150 area of the connection mapping control block 100, internal cache control information is recorded in the cache control unit 110.

The operation of the cell mapping apparatus of the above-described configuration is described below.

The VPI / VCI value input to the cell connection mapping control block 100 is provided to the internal connection cache / controller block 110 and the hash messenger block 120 and processed simultaneously in the following two ways.

In cell-attached cache / controller block 110, cache controller 114 compares each line of cache 112 with VPI / VCI to determine a hit or miss and outputs a cache hit or miss signal to target address selector 170. do. In addition, the cache controller 114 outputs the target address to the hash table 210 of the cell-connected memory unit 200 to access the hash bucket chain during the cache hit. The target address is an address signal that designates a VC table for the corresponding channel of the input ATM cell, and directly accesses one bucket pointer in the bucket pointer field 214 of the hash table 210 of the cell-connected memory unit 200. do.

The function selection register 130 provides a function selection signal to the multiplexer 140, and the multiplexer 140 selectively outputs a hash function of the hash function block 120 to the adder 160 in response to the function selection signal. The hash function selected by the multiplexer 140 is added to the result of the hash function from the hash table / base memory 150 providing the key value in the adder 160, i.e., the base address, and output to the target address selector 170. .

The target address selector 170 determines whether to deliver the output of the adder 160 to the cell-connected memory 200 according to the cache hit / mass control signal from the cache controller 114. That is, if a cache hit signal is provided, the output of the adder 160 is ignored, and if a miss signal is provided, the output of the adder 160 is transferred to the cell-connected memory 200 to provide a deep field () of the hash table 210. A physical address of 212) is specified, and one bucket pointer designated by this physical address is accessed to find the corresponding channel of the input ATM cell.

The mapping controller 300 finds the final VC table n in the cell connection memory unit 200 according to the output from the cell connection mapping control block 100. The process is explained as follows.

When the target address is provided from the cache block 110 of the cell connection mapping control block 100, the bucket pointer of the hash table 210 of the cell connection memory unit 200 is directly accessed. However, when the base address is provided from the cell connection mapping control block 100, the deep field 212 of the hash table 210 of the cell connection memory unit 200 is referred to. According to the reference of the deep field 212, a bucket pointer, which is a target address in the bucket pointer field 214, corresponding thereto is found and used to access the hash bucket chain 220. Here, entries corresponding to Lin-Arr-Len (= K) can be accessed only once. Otherwise, you can read the field of the next pointer of the entry being processed and access the next entry.

Cell headers and table entries whose headers of cells entered in each entry are cold-masked by a header mask in the table entry while sequentially accessing the first entry to the last entry in one hash bucket chain 220. Is compared to a header within the.

When the comparison result is matched, one VC table is found in the VC table 230 using the VC table pointer of the hash bucket chain 220 designated by the matched entry. If the comparison does not match, the next entry is found and the same comparison is repeated. At this time, if a matching entry is not found in the hash bucket chain 220 as a result of the comparison of all entries, the input ATM VPI / VCI value is treated as wrong.

As such, when a cache hit or a cache miss hash function is used to reach the final VC table to access information for the corresponding ATM cell, the fields required to update the internal cache 112, e.g., of the total cells entered. The number and elapsed time are newly revised.

In the hash table 210, the number of entries of the cell-connected memory unit 200 increases when a new channel in the input direction is created and decreases when a channel in use is lost. If the bucket pointer value of the area specified by the address generated as a result of the hash function using the newly created channel's VPI / VCI is not set, the bucket pointer 0 to N-1 should be newly renewed. It then creates a new entry for the new hash bucket, creates a VC table, and writes its address to the VC table 230. However, if there is a bucket pointer in the area in the hash table 210 specified by the address generated as a result of the hash function, it increments one deep value in the deep field 212 and in the bucket chain 220 specified by the bucket pointer. Add a new entry. Create a VC table and store its address in the VC table pointer in the new bucket entry.

Since the deep storage 212 area of the hash table 210 reflects that the number of entries in the hash bucket is increased and decreased when a new channel is created and destroyed according to the VPI / VCI allocation of the ATM cell, the mapping controller 300 ) Is used whenever the deep field 212 is updated to evaluate the performance of the hash function.

When one ATM cell is input, the contents of the VC table 230 determined by the VPI / VCI value include the recorded information on the total number of input cells and the elapsed time. This content is frequently read by the mapping controller 300 and provided as a reference for selecting a channel to replace during cache replacement. Therefore, the mapping controller 300 frequently transmits channel information to be replaced through the line 180 to the cache 112 based on the information about the total number of input cells and the elapsed time.

The mapping controller 300 modifies the contents of the hash function selection register 130 when initializing the cell mapping device or when the user channel to be reassembled is out of mode to change the hash function or to change the linear bucket array of the hash bucket chain. Can be changed.

As described above, according to the present invention, since the control / process data memory area required for reassembly processing can be shared, the cell connection mapping apparatus can be implemented at a low cost, and an advantage of fast cell mapping processing is provided. .

Claims (4)

An ATM cell connection mapping apparatus, A hash table consisting of a deep field and a bucket pointer field, wherein the bucket pointer of the bucket pointer field in the hash table specifies a hash bucket chain having a plurality of entries, each hash bucket chain having processing information in one channel. A cell association memory having a VC table pointer field specifying a VC table; A connection mapping block configured to output a base address specifying a physical address of the deep field generated by performing a hash function on the VPI / VCI of the ATM cell; The base address is used to access the location where the corresponding hash bucket chain is stored in the bucket pointer field by referring to the deep field of the hash table of the cell-connected memory, and the entry of the accessed hash bucket chain is stored with the VPI / VCI of the ATM cell. And means for finding a VC table corresponding to the VPI / VCI by comparing sequentially. The method of claim 1, wherein the connection mapping block is: A hash function block having a plurality of hash functions; Function selection means for generating a signal for selecting the plurality of hash functions; A multiplexer for selecting one hash function from the block according to the selection signal; Means for providing a key value; Means for generating the base address by adding the key value to a hash function selected from the multiplexer. The apparatus of claim 2, wherein the ATM cell connection mapping device comprises: Internal cell connection cache; The VPI / VCI of the ATM cell is compared with the data in the cell connection cache to generate a hit or miss signal, and when the hit generates a target address that designates one bucket pointer in the bucket pointer field in the cell connection memory. A cache controller for directly outputting to the connection memory unit; Means for outputting the target address to the cell-connected memory in response to a hit or miss signal from the cache controller. The method of claim 2, And the data in the cache memory are replaced with reference to the total number of hits after the replacement and the total number of cells after the replacement.