KR19980054997A - Stacked Semiconductor Packages - Google Patents

Abstract

As described above, in the present invention, an alignment groove is formed in the upper surface of the package by inserting guide pins and leads shorter than the thickness of the package into the package, thereby reducing the time required to align the plurality of packages. It is possible to prevent misalignment of leads that are misaligned when moving to reflow.

In addition, by forming a protrusion under the guide pin to distribute the weight of the stacked package it is possible to prevent the deformation of the lead or solder ball due to the load of the stacked package it is possible to improve the reliability of the product.

Description

Stacked Semiconductor Packages

The present invention relates to a stacked semiconductor package, and more particularly, to form a stacked package using a pin grid array (PGA) package or a ball grid array (BGA) package, and to align the guide pins by inserting guide pins at respective package edges. It relates to a stacked semiconductor package for preventing the lead from being deformed due to the load of this simple stacked package.

In recent years, in accordance with the trend of multifunction, large number of input / output, high speed, and large capacity of semiconductor devices, stacked packages in which several packages are stacked have been developed.

Stacked packages are typically stacked with multiple semiconductor packages to increase the memory capacity of DIP or SOJ packages with low pin count, and then soldered and electrically connected between leads to electrically conduct each semiconductor package. Such a laminated package includes a process of stacking a DIP or SOJ semiconductor package, and a process of mounting the stacked semiconductor package on a printed circuit board.

1 is a perspective view illustrating a stacked package of a small outline J-formed pakage (SOJ) type.

In general, a method of manufacturing a SOJ package is a semiconductor chip attached to an upper surface of a die pad of a lead frame by using an insulating adhesive or an insulating tape, and electrically connected to a bonding pad and an inner lead formed on the upper surface of the semiconductor chip by a conductive wire. It conducts and encapsulates using molding resin in order to protect a semiconductor chip, a wire, and an inner lead.

After the trim process, the outer leads of the semiconductor package are formed in a J shape to form an SOJ type semiconductor package.

The manufacturing method of the SOJ type laminated semiconductor package using the SOJ semiconductor package thus formed is as follows.

As illustrated in FIG. 1, a plurality of SOJ semiconductor packages 11 are stacked on the bottommost SOJ semiconductor package 15. Here, the leads 17 of the lowermost SOJ package 15 and the leads 13 of the SOJ package 11 to be stacked on the uppermost SOJ package 15 are accurately aligned. Thereafter, when a plurality of SOJ packages 13 are stacked on the lowermost SOJ package 15, the aligned lead 17 and the lead 13 are electrically aligned to electrically conduct the respective SOJ packages 11 and 15. Each laminated SOJ package 11 and 15 is connected by soldering therebetween.

The SOJ type stacked package 10 manufactured as described above is placed on the upper surface of a printed circuit board (not shown), and then solder is melted at a lower temperature than the solder used when connecting the leads 13 and 17. The SOJ type stacked semiconductor package 10 is mounted on a printed circuit board.

Meanwhile, as illustrated in FIG. 2, a DIP type stacked package may be formed using the DIP semiconductor package.

However, when stacking a plurality of SOJ packages or DIP packages to form a stacked package, it takes a lot of time to align each package, and even to reflow the stacked packages to electrically connect each of the completed packages. There was a problem in that the alignment failure that the outer leads are shifted from each other due to the handling miss when moving. In addition, when stacking a plurality of SOJ packages or DIP packages, the package located at the lowermost layer has a problem in that the outer leads are deformed due to the load of the stacked packages, thereby reducing the reliability of the product.

Accordingly, an object of the present invention is to reduce the time required to align the respective packages, to prevent misalignment of the outer leads that are misaligned by the handling when moving to reflow to electrically connect the stacked packages, and to stack the stacked packages. The present invention provides a stacked semiconductor package that prevents deformation of an outer lead due to a load, thereby improving product reliability.

FIG. 1A is a perspective view illustrating a stacked package of a dual inline package (DIP) type, FIG. 1B is a perspective view illustrating a stacked package of a small outline j-formed package (SOJ) type,

FIG. 2 is a cross-sectional view of a multilayer semiconductor package of a PPGA (Plastic Pin Grid Array) type according to the first embodiment of the present invention.

3 is a cross-sectional view illustrating a stacked-type semiconductor package of a bill grid array (BGA) type according to a second embodiment of the present invention.

In order to achieve the above object, the present invention provides a cavity for mounting a metal pattern and a semiconductor chip, a first via hole formed around the cavity to electrically connect the metal pattern, and a second via hole formed in the corner portion. A printed circuit board comprising: a cap coupled to a cavity to protect the semiconductor chip; shorter lengths than a thickness of the printed circuit board; and leads inserted into a first via hole; and a length greater than a thickness of the printed circuit board. A plurality of short PPGA packages including guide pins inserted into the second via holes and supporting the respective packages are stacked.

Hereinafter, an embodiment of a stacked semiconductor package according to the present invention will be described with reference to FIG. 3.

2 is a cross-sectional view of a multilayer semiconductor package of a PPGA (Plastic Pin Grid Array) type according to the first embodiment of the present invention.

The cavity 23 is formed in the center of the upper surface of the PPGA printed circuit board 21, the semiconductor chip 25 is mounted on the upper surface of the cavity 23, the semiconductor chip 25 and the PPGA printed circuit board 21. Metal wires (not shown) formed at the ends are connected by wires 27, and the cavity is sealed by a cap 29 to protect the semiconductor chip 25. In addition, a plurality of first via holes 31 are formed along the rectangular cavity 23 to electrically connect the metal wires formed on the PPGA printed circuit board 21, Two via holes 32 are formed. In addition, conductive leads 33 having a length shorter than the thickness of the PPGA printed circuit board 21 are inserted in each of the first via holes 31, and package leads stacked in the second via holes 32. Conductive guide pins 35 having a length shorter than the thickness of the PPGA printed circuit board 21 are inserted in order to facilitate the alignment of the 33, and the lead ( In order to prevent 33 from being deformed, two projections 37 are formed. Here, since the length of the lead 33 and the guide pin 35 is shorter than the thickness of the PPGA printed circuit board 21, an alignment groove 39 having a predetermined depth is formed on the upper surface of the PPGA printed circuit board 21. Solder is plated on the 33 and the guide pin 35.

Referring to the PPGA type laminated package manufacturing method using the PPGA package configured as described above are as follows.

The PPGA package has the advantages of a light package, low cost, good electrical characteristics and multipinning.

First, a plurality of PPGA packages are stacked on the lowermost PPGA package 30. Here, the leads 34 and the guides of the PPGA package 30a to be stacked on the lowermost PPGA package 30 in the align groove 39 of a predetermined depth formed along the upper edge and the bottom surface of the lowermost PPGA package 30. The pins 36 are inserted a predetermined length to align the leads 33 and 34 accurately. Subsequently, when the plurality of PPGA packages 30a are stacked on the lowermost PPGA package 30, the stacked PPGA packages 30 and 30a are mounted on a printed circuit board (not shown), and then the respective PPGA packages 30 are mounted. In order to electrically conduct the 30a and connect the stacked PPGA packages 30 and 30a to the printed circuit board, the stacked PPGA package 20 is introduced into a high temperature heater. At this time, the solder that is plated on the leads 33 and 34 and the guide pins 35 and 36 is melted, and the leads 33 and 34 are connected, and the PPGA semiconductor package 20 laminated with the printed circuit board. Is connected.

3 is a cross-sectional view illustrating a stacked-type semiconductor package of a bill grid array (BGA) type according to a second embodiment of the present invention.

The cavity 43 is formed in the center of the upper surface of the BGA printed circuit board 41, the semiconductor chip 45 is mounted on the upper surface of the cavity 43, the semiconductor chip 45 and the BGA printed circuit board 41. Metal wires (not shown) formed at the ends are connected by the wires 47, and the cavity 43 is sealed by a cap 49 to protect the semiconductor chip 45. In addition, a plurality of first via holes 51 are formed along the rectangular cavity 43 to electrically connect the metal wires formed on the BGA printed circuit board 41, and the edges of the printed circuit board 41 are formed. The second via hole 52 is formed in the portion. Solder balls 53 and 54 are formed under each of the first via holes 51, and a BGA printed circuit is used to facilitate stacking and alignment of the second via holes 52 package. Conductive guide pins 55 having a length shorter than the thickness of the substrate 41 are inserted, and under the guide pins 55, the solder balls 53 and 54 are prevented from being deformed due to the weight of the stacked packages. Two projections 57 are formed. Here, since the length of the guide pins 55 and 56 is shorter than the thickness of the BGA printed circuit board 41, an alignment groove 59 having a predetermined depth is formed in the corner of the upper surface of the BGA printed circuit board 41, and the guide The pins 55 and 56 are plated with solder.

A method of manufacturing a BGA type stacked package using the BGA package configured as described above is as follows.

First, a plurality of BGA packages are stacked on the bottommost BGA package 50. Here, the guide pins 56 of the BGA package 50a to be stacked on the lowermost BGA package 50 are inserted into the alignment groove 59 having a predetermined depth formed at the upper edge of the lowermost BGA package 50 by a predetermined length. To accurately align the BGA package 50a stacked on the lowermost BGA package 50.

When the plurality of BGA packages 50a are stacked on the lowermost BGA package 50, the BGA type stacked package 40 is formed by using the guide pins 55 formed on the lowermost BGA package 50. Mount on Thereafter, each of the plurality of stacked BGA packages 50 and 50a is electrically connected to each other and inserted into the printed circuit board inside a high temperature heater to connect the BGA type stacked package 40 and a printed circuit board (not shown). When the BGA-type stacked package 40 is inserted, the solder that is plated on the guide pins 55 and 56 is melted, and the respective guide pins 55 and 56 are connected, and the printed circuit board and the BGA-type stacked package are connected. The package 40 is connected.

As such, when a lead or a guide pin having a length shorter than the thickness of the package is formed, an alignment groove having a predetermined depth is formed on the upper surface of the package to facilitate alignment of each package, and electrically connect each of the plurality of stacked packages. In order to prevent the occurrence of misalignment during the movement to the reflow, the projections are formed on the guide pins to prevent the load of the stacked package is distributed to deform the lead or solder balls. In addition, the solder is plated on the guide pins and leads in advance, and then the guide pins and leads are inserted into the package to bond the stacked packages using one kind of solder, and the stacked packages are mounted on the printed circuit board. You can proceed simultaneously.

As described above, according to the present invention, an alignment groove is formed in the upper surface of the package by inserting guide pins and leads shorter than the thickness of the package into the package, thereby reducing the time required to align the plurality of packages. When moving to reflow, there is an effect of preventing misalignment of leads that are misaligned.

In addition, by forming a protrusion in the lower portion of the guide pin to distribute the weight of the stacked package it is possible to prevent the deformation of the lead or solder balls due to the load of the stacked package has the effect of improving the reliability of the product.

Claims (6)

In the stacked semiconductor package, A printed circuit board formed of a cavity for mounting a metal pattern, a semiconductor chip, a first via hole for electrically connecting the metal pattern, and a second via hole formed in the corner portion; A cap coupled to the cavity, leads that are shorter than the thickness of the printed circuit board and inserted into the first via hole, and are shorter than the thickness of the printed circuit board and inserted into the second via hole to protect the A stacked semiconductor package, characterized in that a plurality of PPGA package including a guide pin for supporting the package is stacked. The multilayer semiconductor package of claim 1, wherein an alignment groove having a predetermined depth is formed on an upper surface of the PPGA package. The multilayer semiconductor package of claim 1, wherein a protrusion is formed under the guide pin to distribute the load of the package. In the stacked semiconductor package, A printed circuit board formed of a cavity for mounting a metal pattern, a semiconductor chip, a first via hole for electrically connecting the metal pattern, and a second via hole formed in the corner portion; A cap coupled to the cavity to protect the solder, a solder ball formed under the first via hole, and a guide pin having a length shorter than a thickness of the printed circuit board and inserted into the second via hole to support each package. A stacked semiconductor package, characterized in that a plurality of BGA packages are stacked. The multilayer semiconductor package of claim 4, wherein an alignment groove having a predetermined depth is formed at an edge portion of an upper surface of the BGA package. The multilayer semiconductor package of claim 1, wherein a protrusion is formed under the guide pin to distribute the load of the package.