KR19980051524A - Device Separation Method of Semiconductor Device - Google Patents
Device Separation Method of Semiconductor Device Download PDFInfo
- Publication number
- KR19980051524A KR19980051524A KR1019960070426A KR19960070426A KR19980051524A KR 19980051524 A KR19980051524 A KR 19980051524A KR 1019960070426 A KR1019960070426 A KR 1019960070426A KR 19960070426 A KR19960070426 A KR 19960070426A KR 19980051524 A KR19980051524 A KR 19980051524A
- Authority
- KR
- South Korea
- Prior art keywords
- film
- trench
- device isolation
- insulating film
- oxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
- 239000004065 semiconductor Substances 0.000 title abstract description 7
- 238000000926 separation method Methods 0.000 title 1
- 238000002955 isolation Methods 0.000 claims abstract description 36
- 238000000034 method Methods 0.000 claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 claims abstract description 10
- 150000004767 nitrides Chemical class 0.000 claims description 20
- 239000000758 substrate Substances 0.000 claims description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 11
- 229910052710 silicon Inorganic materials 0.000 claims description 11
- 239000010703 silicon Substances 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims description 6
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims description 2
- 238000001039 wet etching Methods 0.000 claims description 2
- 239000000463 material Substances 0.000 claims 1
- 238000007517 polishing process Methods 0.000 claims 1
- 230000000593 degrading effect Effects 0.000 abstract 1
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000007792 addition Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
Landscapes
- Element Separation (AREA)
Abstract
본 발명은 반도체소자의 소자분리막 제조방법에 관한 것으로, 고집적 반도체소자에 적용하기 위한 트렌치 소자분리막을 제조하는 과정에서 패드산화막을 제거하는 공정에서 소자분리막과 액티브영역의 경계면에서 트렌치 상부 모서리가 노출됨으로 인하여 반도체소자의 성능이 저하되는 것을 방지하기 위하여 소자분리막을 T자 형태로 형성하는 것이다.The present invention relates to a method for fabricating a device isolation film of a semiconductor device, wherein the upper edge of the trench is exposed at the interface between the device isolation film and the active region in the process of removing the pad oxide film during the manufacture of the trench device isolation film for application to the highly integrated semiconductor device. In order to prevent the performance of the semiconductor device from degrading, the device isolation film is formed in a T-shape.
Description
본 발명은 반도체소자의 소자분리막 제조방법에 관한 것으로, 특히 1 GigaDRAM급 이상의 반도체소자에 적용하기 위한 트렌치 소자분리막 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a device isolation film of a semiconductor device, and more particularly, to a method of manufacturing a trench device isolation film for application to a semiconductor device of 1 GigaDRAM or more.
일반적으로 반도체소자 소자분리방법으로 LOCOS(Local Oxidation of Silicon) 공정을 주로 이용하였으나 더욱 고집적화됨에 따라 상기의 공정은 버즈빅이 발생되는 문제점으로 인해 고집적화에 장애요인으로 작용하고, 소자분리막의 단차로 인해 후속 공정을 진행하는데 어려움이 발생된다.In general, the LOCOS (Local Oxidation of Silicon) process is mainly used as a method of separating semiconductor devices, but as the integration becomes more highly integrated, the above process acts as a barrier to high integration due to the problem of the occurrence of buzz big, Difficulties arise in the subsequent process.
한편, 상기한 문제점을 극복하기 위한 소자분리방법으로 트렌치 소자분리방법이 대두되었다. 트렌치 소자분리방법은 실리콘 기판에 트렌치를 형성한다음, 이 트렌치에 절연막을 채워서 소자분리막으로 사용하는 것이다.Meanwhile, a trench isolation method has emerged as an isolation method for overcoming the above problems. In the trench isolation method, a trench is formed in a silicon substrate, and an insulating film is filled in the trench to be used as an isolation layer.
트렌치 소자분리막을 제조하는 단계를 도 1 내지 도 5에 도시된 도면을 참조하여 설명하기로 한다.A step of manufacturing the trench isolation layer will be described with reference to the drawings illustrated in FIGS. 1 to 5.
도 1은 실리콘 기판(1)의 상부에 패드 산화막(2), 질화막(2)을 순차적으로 적층하고, 소자분리마스크를 이용한 식각 공정으로 소자분리 영역으로 한정되는 지역의 질화막(3)과 패드산화막(2) 및 그 하부의 실리콘 기판(1)을 식각하여 트렌치(4)를 형성하고, 전체적으로 산화막(5)을 두껍게 형성한 단면도이다.FIG. 1 sequentially deposits the pad oxide film 2 and the nitride film 2 on the silicon substrate 1, and the nitride film 3 and the pad oxide film in a region limited to the device isolation region by an etching process using an device isolation mask. (2) and the silicon substrate 1 in the lower portion thereof are etched to form the trenches 4, and the oxidized film 5 is thickly formed as a whole.
도 2는 상기 산화막(5)을 질화막(3)의 표면이 노출되기까지 식각하여 트렌치(4)에 산화막(5)을 채운 단면도이다.FIG. 2 is a cross-sectional view of the oxide film 5 filled with the oxide film 5 by etching the oxide film 5 until the surface of the nitride film 3 is exposed.
도 3은 상기 질화막(3)을 제거하여 상기 트렌치(4)에 채워진 산화막(5)의 상부면이 돌출되는 것을 도시한다.3 shows that the upper surface of the oxide film 5 filled in the trench 4 protrudes by removing the nitride film 3.
도 4는 상기 패드 산화막(2)을 제거하기 위해 식각공정을 진행하면 기판 표면과 트렌치(4) 상부면의 모서리부(6)가 노출됨을 도시한다. 여기서, 트렌치(4)에 남았는 산화막(5)은 소자분리막으로 이용된다.FIG. 4 shows that the etching process to remove the pad oxide layer 2 exposes the substrate surface and the edge portion 6 of the trench 4 upper surface. Here, the oxide film 5 remaining in the trench 4 is used as the device isolation film.
도 5는 후속 공정으로 게이트 산화막(7)을 형성하였을때 상기 트렌치(4) 상부면의 모서리부(6)에는 게이트 산화막(7)의 두께가 얇게 형성되어 소자의 성능이 취약하게 되는 문제가 발생된다.5 shows that when the gate oxide film 7 is formed in a subsequent process, a thin thickness of the gate oxide film 7 is formed in the corner portion 6 of the upper surface of the trench 4, resulting in a weak performance of the device. do.
상기와 같이 종래기술로 트렌치 소자분리막을 형성하는 경우 패드산화막을 식각할때 소자분리막과 액티브영역의 경계면에서 트렌치 상부 모서리가 노출되고, 후속 공정에서 게이트 산화막을 형성하여도 상기 모서리부가 취약하여 소자의 신뢰성을 떨어뜨리는 문제를 초래한다.As described above, when the trench isolation layer is formed in the prior art, when the pad oxide layer is etched, the upper corner of the trench is exposed at the interface between the isolation layer and the active region. It causes a problem of deterioration of reliability.
본 발명은 트렌치 소자분리막을 제조하는 과정에서 소자분리막과 액티브영역의 경계면에서 트렌치 상부 모서리가 노출되고, 후속 공정에서 게이트 산화막을 형성하여도 상기 모서리부가 취약하게 되는 것을 해소하는데 그 목적이 있다.An object of the present invention is to solve the problem that the upper edge of the trench is exposed at the interface between the device isolation layer and the active region in the process of manufacturing the trench isolation layer, and that the corner portion becomes weak even when the gate oxide layer is formed in a subsequent process.
도 1 내지 도 5는 종래기술에 의해 트렌치 구조의 소자분리막 제조단계를 도시한 단면도이다.1 to 5 are cross-sectional views illustrating a device isolation film manufacturing step of a trench structure according to the prior art.
도 6 내지 도 14는 본 발명에 의해 트렌치 구조의 소자분리막 제조단계를 도시한 단면도이다.6 to 14 are cross-sectional views illustrating a device isolation film manufacturing step of a trench structure according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1,11 : 실리콘 기판 2,12 : 패드 산화막1,11 silicon substrate 2,12 pad oxide film
3,13 : 질화막 4 ,16 : 트렌치3,13: nitride film 4,16: trench
5,14,17 : 산화막 7 : 게이트 산화막5,14,17: oxide film 7: gate oxide film
15 : 감광막 패턴15 photosensitive film pattern
상기 목적을 달성하기 위한 본 발명은 실리콘 기판 상부에 패드 산화막, 질화막, 절연막을 적층하고, 그 상부에 소자분리 마스크용 감광막 패턴을 형성하는 공정과, 상기 감광막 패턴을 마스크로 이용하여 절연막에서 패드산화막까지 순차적으로 식각하여 패턴을 형성하는 공정과, 노출된 소자분리영역의 실리콘 기판을 건식식각하여 트렌치를 형성하고, 상기 감광막 패턴을 제거하는 공정과, 상기 질화막을 선택적으로 일정 깊이 제거하는 공정과, 질화막 상부에 있는 절연막을 제거하는 공정과, 전체적으로 절연막을 두껍게 증착하는 공정과, 상기 절연막의 제거하되 질화막이 노출되도록 상기 트렌치에 절연막으로 채워진 T자 형태의 소자분리막을 형성하는 공정과, 상기 질화막을 제거하고, 상기 패드 산화막을 제거하는 공정으로 이루어지는 소자분리막 제조방법이다.According to an aspect of the present invention, a pad oxide film, a nitride film, and an insulating film are stacked on an upper surface of a silicon substrate, and a photoresist pattern for forming a device isolation mask is formed thereon; Sequentially etching to form a pattern, dry etching the silicon substrate of the exposed device isolation region to form a trench, removing the photoresist pattern, selectively removing the nitride film to a predetermined depth, Removing the insulating film over the nitride film, depositing a thick insulating film as a whole, forming a T-shaped device isolation film filled with the insulating film in the trench such that the insulating film is removed but the nitride film is exposed; A device powder comprising a step of removing and removing the pad oxide film It is a manufacturing method.
본 발명에 의하면 소자분리막을 T자 형태로 제조하여 게이트 산화막을 형성하는 전계의 공정에서 패드산화막을 제거할 때 트렌치의 상부 모서리부가 노출되는 것을 방지할 수가 있다. 그 결과 소자의 성능이 향상되고, 신뢰성을 높일 수 있다.According to the present invention, it is possible to prevent the upper edge portion of the trench from being exposed when the pad oxide film is removed in the process of electric field forming the gate oxide film by forming the device isolation film in the T shape. As a result, the performance of the device can be improved and the reliability can be improved.
상술한 목적 및 특징들, 장점은 첨부된 도면과 관련한 다음의 상세한 설명을 통하여 보다 분명해질 것이다. 이하 첨부된 도면을 참조하여 본 발명의 실시예를 상세히 설명하면 다음과 같다.The above objects, features, and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 6 내지 도 14는 본 발명의 실시예에 의해 트렌치 소자분리막을 제조하는 과정을 설명하기로 한다.6 to 14 will be described a process of manufacturing a trench isolation film according to an embodiment of the present invention.
도 6은 실리콘 기판(11) 상부에 패드 산화막(12), 질화막(13), 제1 산화막(14)을 적층하고, 상기 제1 산화막(14) 상부에 감광막을 도포하고, 소자분리 마스크를 이용한 노광 및 현상 공정으로 감광막 패턴(15)을 형성한 단면도이다.FIG. 6 shows a pad oxide film 12, a nitride film 13, and a first oxide film 14 stacked on a silicon substrate 11, a photoresist film is coated on the first oxide film 14, and an element isolation mask is used. It is sectional drawing which formed the photosensitive film pattern 15 by the exposure and image development process.
도 7은 상기 감광막 패턴(15)을 마스크로 이용하여 산화막(14)에서 패드산화막(12)까지 순차적으로 식각하여 패턴을 형성한 단면도이다.FIG. 7 is a cross-sectional view of a pattern formed by sequentially etching the oxide layer 14 to the pad oxide layer 12 using the photosensitive layer pattern 15 as a mask.
도 8은 노출된 소자분리영역의 실리콘 기판(11)을 건식식각하여 트렌치(16)를 형성하고, 상기 감광막 패턴(15)을 제거한 단면도이다.FIG. 8 is a cross-sectional view of the trench 16 formed by dry etching the exposed silicon substrate 11 in the device isolation region and removing the photoresist pattern 15.
도 9는 인산(H3PO4)을 습식식각용액으로 이용하여 상기 질화막(13)을 일정깊이 제거한 것을 도시한 단면도이다.9 is a cross-sectional view showing that the nitride film 13 is removed to a predetermined depth by using phosphoric acid (H 3 PO 4 ) as a wet etching solution.
도 10은 케미칼 메카니칼 폴리싱(Chemical Mechanical Polishing)을 이용하여 상기 제1 산화막(14)을 제거한 단면도이다.FIG. 10 is a cross-sectional view of removing the first oxide layer 14 by using chemical mechanical polishing.
도 11은 전체적으로 제2 산화막(17)을 두껍게 증착하여 상기 트렌치(16)를 채운 단면도이다.FIG. 11 is a cross-sectional view of the trench 16 filled with a thick second oxide film 17 as a whole.
도 12는 케미칼 메카니칼 폴리싱(Chemical Mechanical Polishing)을 이용하여 상기 질화막(13) 상부면까지 제2 산화막(17)을 제거하여 상기 트렌치(16)에 제2 산화막을 채워진 소자분리막(18)을 형성한 단면도이다.FIG. 12 illustrates a device isolation film 18 having a second oxide film filled in the trench 16 by removing the second oxide film 17 to the upper surface of the nitride film 13 by using chemical mechanical polishing. It is a cross section.
도 13은 상기 질화막(13)을 제거한 단면도이다.13 is a cross-sectional view of the nitride film 13 removed.
도 14는 상기 패드 산화막(12)의 두께 만큼 전면식각하여 실리콘 기판(11)의 상부면이 노출되도록 한 단면도로서, 소자분리막(18)의 일정 두께도 함께 식각된다.FIG. 14 is a cross-sectional view of the entire surface of the silicon oxide substrate 11 exposed by the thickness of the pad oxide layer 12 to expose the upper surface of the silicon oxide substrate 11.
상기와 같이 소자분리막이 T자 형태로 제조됨에 따라 패드산화막을 제거하는 공정에서 트렌치의 상부 모서리부가 노출되는 문제는 발생되지 않게 된다.As the device isolation layer is manufactured in the T-shape as described above, the problem of exposing the upper edge portion of the trench in the process of removing the pad oxide layer does not occur.
상기한 본 발명은 소자분리막을 형성할때 소자분리막이 T자 형태로 제조하여 게이트 산화막을 형성하기 전단계의 공정으로 패드산화막을 제거할때 트렌치의 상부 모서리부가 노출됨으로 인해 상기 모서리부에서 취약해지는 문제점을 해결할 수 있다. 그 결과 소자의 성능이 향상되고, 신뢰성을 높일 수 있다.In the present invention, when the device isolation film is formed, the device isolation film is formed in a T-shape, and thus the upper edge portion of the trench is exposed when the pad oxide film is removed in a step of forming the gate oxide film. Can be solved. As a result, the performance of the device can be improved and the reliability can be improved.
아울러 본 발명의 바람직한 실시예들은 예시의 목적을 위해 개시된 것이며, 당업자라면 본 발명의 사상과 범위안에서 다양한 수정, 변경, 부가등이 가능할 것이며, 이러한 수정 변경 등은 이하의 특허 청구의 범위에 속하는 것으로 보아야 할 것이다.In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to various modifications, changes, additions, etc. within the spirit and scope of the present invention, such modifications and modifications belong to the following claims You will have to look.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960070426A KR19980051524A (en) | 1996-12-23 | 1996-12-23 | Device Separation Method of Semiconductor Device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960070426A KR19980051524A (en) | 1996-12-23 | 1996-12-23 | Device Separation Method of Semiconductor Device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR19980051524A true KR19980051524A (en) | 1998-09-15 |
Family
ID=66384429
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019960070426A Ceased KR19980051524A (en) | 1996-12-23 | 1996-12-23 | Device Separation Method of Semiconductor Device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR19980051524A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100857576B1 (en) * | 2002-06-27 | 2008-09-09 | 매그나칩 반도체 유한회사 | Storage node formation method of semiconductor device |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56103446A (en) * | 1980-01-22 | 1981-08-18 | Fujitsu Ltd | Semiconductor device |
| JPH06140501A (en) * | 1992-10-27 | 1994-05-20 | Toshiba Corp | Semiconductor device and manufacture thereof |
| KR950012685A (en) * | 1993-10-29 | 1995-05-16 | 김주용 | Device Separation Method of Semiconductor Device |
| JPH07193121A (en) * | 1993-12-27 | 1995-07-28 | Toshiba Corp | Method for manufacturing semiconductor device |
| US5712185A (en) * | 1996-04-23 | 1998-01-27 | United Microelectronics | Method for forming shallow trench isolation |
| KR0170897B1 (en) * | 1994-12-31 | 1999-03-30 | 김주용 | Method of manufacturing element-segregation insulating film of semiconductor device |
| KR100200731B1 (en) * | 1996-10-05 | 1999-06-15 | 윤종용 | Method of forming a device isolation film of semiconductor device |
-
1996
- 1996-12-23 KR KR1019960070426A patent/KR19980051524A/en not_active Ceased
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56103446A (en) * | 1980-01-22 | 1981-08-18 | Fujitsu Ltd | Semiconductor device |
| JPH06140501A (en) * | 1992-10-27 | 1994-05-20 | Toshiba Corp | Semiconductor device and manufacture thereof |
| KR950012685A (en) * | 1993-10-29 | 1995-05-16 | 김주용 | Device Separation Method of Semiconductor Device |
| JPH07193121A (en) * | 1993-12-27 | 1995-07-28 | Toshiba Corp | Method for manufacturing semiconductor device |
| KR0170897B1 (en) * | 1994-12-31 | 1999-03-30 | 김주용 | Method of manufacturing element-segregation insulating film of semiconductor device |
| US5712185A (en) * | 1996-04-23 | 1998-01-27 | United Microelectronics | Method for forming shallow trench isolation |
| KR100200731B1 (en) * | 1996-10-05 | 1999-06-15 | 윤종용 | Method of forming a device isolation film of semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100857576B1 (en) * | 2002-06-27 | 2008-09-09 | 매그나칩 반도체 유한회사 | Storage node formation method of semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100318640B1 (en) | Manufacturing method of semiconductor device | |
| KR19980051524A (en) | Device Separation Method of Semiconductor Device | |
| KR100249320B1 (en) | Trench manufacturing method for semiconductor element isolating | |
| KR100313523B1 (en) | Manufacturing method for isolation in semiconductor device | |
| KR19990003538A (en) | Manufacturing method of semiconductor device | |
| KR100273244B1 (en) | Method for fabricating isolation region of semiconductor device | |
| KR0148611B1 (en) | Formation method of element isolation layer for semiconductor devices | |
| KR19980048836A (en) | Device Separating Method of Semiconductor Device | |
| KR0161727B1 (en) | Element isolation method of semiconductor device | |
| KR100528797B1 (en) | Method of forming an isolation film in a semiconductor device | |
| KR100265177B1 (en) | Semiconductor element isolation method | |
| KR20030049783A (en) | Method of forming an isolation film in semiconductor device | |
| KR20030001965A (en) | Method for fabricating semiconductor device | |
| KR100724197B1 (en) | Manufacturing Method of Semiconductor Device | |
| KR20020044682A (en) | Method for forming isolation layer in semiconductor device | |
| KR100422960B1 (en) | Device isolation insulating film formation method of semiconductor device | |
| KR0172760B1 (en) | Method for manufacturing device isolation insulating film of semiconductor device | |
| KR20000045374A (en) | Method for manufacturing semiconductor device | |
| KR19980065679A (en) | How to form shallow trench insulation | |
| KR20030002702A (en) | Method of forming an isolation layer in a semiconductor device | |
| KR19990080468A (en) | Trench manufacturing method for semiconductor device isolation | |
| KR970005114B1 (en) | Preparation method of field oxidation layer in semiconductor element | |
| US7645680B2 (en) | Method of manufacturing isolation layer pattern in a semiconductor device and isolation layer pattern using the same | |
| KR0166489B1 (en) | Device Separation Method of Semiconductor Devices | |
| KR970005703B1 (en) | Semiconductor device having trench type isolation structure and manufacturing method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PA0109 | Patent application |
Patent event code: PA01091R01D Comment text: Patent Application Patent event date: 19961223 |
|
| PG1501 | Laying open of application | ||
| A201 | Request for examination | ||
| PA0201 | Request for examination |
Patent event code: PA02012R01D Patent event date: 20011204 Comment text: Request for Examination of Application Patent event code: PA02011R01I Patent event date: 19961223 Comment text: Patent Application |
|
| E902 | Notification of reason for refusal | ||
| PE0902 | Notice of grounds for rejection |
Comment text: Notification of reason for refusal Patent event date: 20030825 Patent event code: PE09021S01D |
|
| E601 | Decision to refuse application | ||
| PE0601 | Decision on rejection of patent |
Patent event date: 20031216 Comment text: Decision to Refuse Application Patent event code: PE06012S01D Patent event date: 20030825 Comment text: Notification of reason for refusal Patent event code: PE06011S01I |