KR19980036777A - Semiconductor Chip Package - Google Patents
Semiconductor Chip Package Download PDFInfo
- Publication number
- KR19980036777A KR19980036777A KR1019960055399A KR19960055399A KR19980036777A KR 19980036777 A KR19980036777 A KR 19980036777A KR 1019960055399 A KR1019960055399 A KR 1019960055399A KR 19960055399 A KR19960055399 A KR 19960055399A KR 19980036777 A KR19980036777 A KR 19980036777A
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- KR
- South Korea
- Prior art keywords
- semiconductor chip
- chip package
- semiconductor
- pattern
- mounting density
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Lead Frames For Integrated Circuits (AREA)
Abstract
본 발명은 반도체칩의 양면에 패턴을 형성하여 1칩화하여 실장밀도를 향상시키도록 한 반도체칩패키지에 관한 것이다.The present invention relates to a semiconductor chip package in which a pattern is formed on both sides of a semiconductor chip to form a single chip to improve the mounting density.
본 발명의 목적은 반도체칩패키지의 크기를 증가시키지 않고 반도체칩패키지의 실장밀도를 향상시키도록 한 반도체칩패키지를 제공하는데 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor chip package for improving the mounting density of the semiconductor chip package without increasing the size of the semiconductor chip package.
이와 같은 목적을 달성하기 위한 본 발명에 의한 반도체칩패키지는 양면에 패턴이 형성된 반도체칩들을 수용하고 양면중 일면의 패턴이 LOC형 리드프레임의 내측단부에 와이어본딩되고 타면이 상기 리드프레임의 외측단부에 와이어본딩되어 여 반도체칩패키지의 수직, 수평크기를 증대시키지 않고도 실장밀도를 향상시키는 것을 특징으로 한다.The semiconductor chip package according to the present invention for achieving the above object accommodates the semiconductor chips having a pattern formed on both sides, the pattern of one side of the both sides is wire-bonded to the inner end of the LOC type lead frame, the other side is the outer end of the lead frame It is wire-bonded to the semiconductor chip package to increase the mounting density without increasing the vertical and horizontal size.
Description
본 발명은 반도체장치의 제조방법에 관한 것으로, 더욱 상세하게는 반도체칩의 양면에 패턴을 형성하여 1칩화하여 실장밀도를 향상시키도록 한 반도체칩패키지에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a semiconductor chip package in which patterns on both surfaces of a semiconductor chip are formed into one chip to improve mounting density.
최근, 전자기기의 고기능화, 소형화 추세에 맞추어 인쇄회로기판의 실장밀도를 증대시키기 위해 반도체칩패키지가 경박단소화되고 있다. 또한, 반도체칩의 고속화, 고기능화에 대응하기 위해 반도체칩패키지의 형태가 경박단소화, 다핀화되고 있다.In recent years, in order to increase the mounting density of printed circuit boards in accordance with the trend of high functionality and miniaturization of electronic devices, semiconductor chip packages have been reduced in size and weight. In addition, in order to cope with high speed and high functionality of the semiconductor chip, the form of the semiconductor chip package has been reduced in size, weight, and pinning.
종래에는 상부면에만 패턴이 형성된 반도체칩을 수용하는 반도체칩패키지의 실장밀도를 향상시키기 위해서 동일 외부리드들이 전기적으로 연결되도록 반도체칩패키지들이 적층되었다. 그러나, 반도체반도체칩패키지의 적층수가 많을수록 전체 반도체칩패키지의 높이가 비례하여 높아졌다.Conventionally, semiconductor chip packages are stacked such that the same external leads are electrically connected in order to improve the mounting density of the semiconductor chip package containing the semiconductor chip having a pattern formed only on the upper surface thereof. However, as the number of stacked semiconductor semiconductor chip packages increased, the height of the entire semiconductor chip package increased proportionally.
이러한 문제점을 개선하기 위해 제안된 방안중의 하나가 하나의 반도체칩패키지에 2개 이상의 반도체칩들을 수용하는 것이다. 이는 반도체칩의 실장밀도를 향상시키거나 반도체칩의 특성을 향상시키거나 특별한 기능을 유도하는 경우에 주로 이용되고 있다.One of the proposed methods to solve this problem is to accommodate two or more semiconductor chips in one semiconductor chip package. This is mainly used to improve the mounting density of the semiconductor chip, improve the characteristics of the semiconductor chip or induce a special function.
도 1은 종래 기술에 의한 반도체칩패키지의 구조를 나타낸 단면도이다.1 is a cross-sectional view showing the structure of a semiconductor chip package according to the prior art.
도 1에 도시된 바와 같이, 인쇄회로기판(1)의 상부면에 반도체칩(3),(4)이 접착제(5)에 의해 접착되며 약간의 거리를 두고 있다. 반도체칩(3),(4)의 본딩패드들(도시안됨)이 와이어(7)에 의해 인쇄회로기판(1)의 금속패턴(도시안됨)에 전기적으로 연결되어 있다. 반도체칩(3),(4)과 와이어(7)가 봉지체(9)에 의해 감싸져 있다.As shown in FIG. 1, the semiconductor chips 3 and 4 are bonded to the upper surface of the printed circuit board 1 by the adhesive agent 5 and spaced apart from each other. Bonding pads (not shown) of the semiconductor chips 3 and 4 are electrically connected to the metal patterns (not shown) of the printed circuit board 1 by wires 7. The semiconductor chips 3, 4 and the wire 7 are wrapped by the encapsulation body 9.
이와 같이 구성된 종래의 반도체칩패키지의 경우, 하나의 반도체칩패키지에 여러개의 반도체칩(3),(4)을 수용하여 실장밀도를 향상시킬 수 있다. 이를 위해 반도체칩들(3),(4)과 인쇄회로기판1)의 상부면 사이에 임의의 물질로 이루어진 접착제(5)가 필수적이다.In the case of the conventional semiconductor chip package configured as described above, the mounting density can be improved by accommodating several semiconductor chips 3 and 4 in one semiconductor chip package. For this purpose, an adhesive 5 made of any material is essential between the semiconductor chips 3, 4 and the upper surface of the printed circuit board 1.
그러나, 이는 신뢰도의 측면에서 볼 때, 반도체칩의 접촉면에서의 박리(delamination)를 유발시킬 가능성을 증가시킨다. 또한, 2개 이상의 반도체칩을 적층하므로 개별 반도체칩이 갖고 있는 두께에 따라 접착물질의 두께, 전기적 연결 방식 및 전체 반도체칩패키지 두께의 한계와 신뢰도의 관점에서 많은 문제점이 예상되고 있다.However, this increases the possibility of causing delamination at the contact surface of the semiconductor chip in terms of reliability. In addition, since two or more semiconductor chips are stacked, many problems are expected in view of the limitations and reliability of the thickness of the adhesive material, the electrical connection method, and the thickness of the entire semiconductor chip package according to the thickness of the individual semiconductor chips.
따라서, 본 발명의 목적은 반도체칩패키지의 크기를 증가시키지 않고 반도체칩패키지의 실장밀도를 향상시키도록 한 반도체칩패키지를 제공하는데 있다.Accordingly, it is an object of the present invention to provide a semiconductor chip package designed to improve the mounting density of a semiconductor chip package without increasing the size of the semiconductor chip package.
도 1은 종래 기술에 의한 반도체칩패키지의 구조를 나타낸 단면도.1 is a cross-sectional view showing the structure of a semiconductor chip package according to the prior art.
도 2는 본 발명에 의한 반도체칩패키지의 구조를 나타낸 단면도.2 is a cross-sectional view showing the structure of a semiconductor chip package according to the present invention.
*도면의주요부분에대한부호의설명** Explanation of symbols on the main parts of the drawings *
1: 인쇄회로기판 3,4: 반도체칩1: printed circuit board 3, 4: semiconductor chip
5: 접착제 7: 와이어5: adhesive 7: wire
9: 봉지체 11: 반도체칩9: Encapsulation Body 11: Semiconductor Chip
13: 접착테이프15: 내부리드13: adhesive tape 15: inner lead
17: 와이어 19: 봉지체17: wire 19: encapsulation
이와 같은 목적을 달성하기 위한 본 발명에 의한 반도체칩패키지는 양면에 패턴이 형성된 반도체칩들을 수용하고 양면중 일면의 패턴이 LOC형 리드프레임의 내측단부에 와이어본딩되고 타면이 상기 리드프레임의 외측단부에 와이어본딩되어 여 반도체칩패키지의 수직, 수평크기를 증대시키지 않고도 실장밀도를 향상시키는 것을 특징으로 한다.The semiconductor chip package according to the present invention for achieving the above object accommodates the semiconductor chips having a pattern formed on both sides, one side of the pattern is wire-bonded to the inner end of the LOC type lead frame and the other side is the outer end of the lead frame It is wire-bonded to the semiconductor chip package to increase the mounting density without increasing the vertical and horizontal size.
이하, 본 발명에 의한 반도체칩패키지를 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, a semiconductor chip package according to the present invention will be described in detail with reference to the accompanying drawings.
도 2는 본 발명에 의한 반도체칩패키지의 구조를 나타낸 단면도이다.2 is a cross-sectional view showing the structure of a semiconductor chip package according to the present invention.
도 2에 도시된 바와 같이, 반도체칩(11)의 상부면 양측 가장자리가 접착테이프(13)에 의해 대향하는 좌,우측 내부리드들(15)의 내측 선단부 근처의 하부면에 접착되고 반도체칩(11)의 상부면의 본딩패드들(도시안됨)이 와이어(17)에 의해 내부리드들(15)의 상부면 내측 선단부 근처에 대응하여 전기적으로 연결되고 반도체칩(11)의 하부면의 본딩패드들(도시안됨)이 와이어(17)에 의해 내부리드들(15)의 하부면의 내측 선단부로부터 약간 거리를 둔 영역에 대응하여 전기적으로 연결된다. 반도체칩(11)과 와이어(17) 및 내부리드들(15)이 성형수지의 봉지체(19)에 의해 감싸여져 있다. 여기서, 반도체칩(11)의 양면에는 동종 또는 이종의 반도체칩을 위한 패턴이 형성되어 있다.As shown in FIG. 2, both edges of the upper surface of the semiconductor chip 11 are bonded to the lower surface near the inner front end portions of the left and right inner leads 15 opposed by the adhesive tape 13. Bonding pads (not shown) of the upper surface of 11 are electrically connected correspondingly near the inner leading end of the upper surface of the inner leads 15 by wires 17 and bonding pads of the lower surface of the semiconductor chip 11. (Not shown) are electrically connected to each other by a wire 17 corresponding to an area slightly distanced from the inner leading end of the lower surface of the inner leads 15. The semiconductor chip 11, the wire 17, and the inner leads 15 are surrounded by the encapsulation body 19 of the molding resin. Here, patterns for the same or different types of semiconductor chips are formed on both surfaces of the semiconductor chip 11.
이와 같이 양면에 패턴들이 형성된 반도체칩들(11)이 하나의 반도체칩패키지에 수용되면, 반도체칩패키지는 2개의 반도체칩패키지(5)가 적층된 것과 같은 실장밀도를 가지며 전체 높이를 훨씬 낮추어 경박단소화를 이룩할 수 있다. 또한, 반도체칩의 접착 신뢰도를 확보할 수 있고 반도체칩 두께의 감소로 인한 기타 공정 안정화를 이룩할 수 있다.When the semiconductor chips 11 having the patterns formed on both sides are accommodated in one semiconductor chip package, the semiconductor chip package has the same mounting density as the two semiconductor chip packages 5 are stacked, and the overall height is made much lower and thus thinner. It can achieve shortening. In addition, it is possible to secure the adhesion reliability of the semiconductor chip and to achieve other process stabilization due to the reduction of the semiconductor chip thickness.
이상에서 살펴본 바와 같이, 본 발명은 양면에 동종 또는 이종의 패턴이 형성된 반도체칩을 반도체칩패키지에 수용하여 반도체칩패키지의 경박단소화를 이룩할 수 있다. 양면에 반도체칩들의 패턴들이 형성되어 양면의 반도체칩들 접착에 대한 신뢰성이 각각의 반도체칩들이 접착된 경우에 비하여 향상된다.As described above, according to the present invention, a semiconductor chip package having semiconductor patterns of the same type or a heterogeneous pattern formed on both surfaces thereof may be accommodated in the semiconductor chip package, thereby achieving light and thin reduction of the semiconductor chip package. Patterns of semiconductor chips are formed on both sides, so that reliability of adhesion of the semiconductor chips on both sides is improved as compared with when each semiconductor chip is bonded.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960055399A KR19980036777A (en) | 1996-11-19 | 1996-11-19 | Semiconductor Chip Package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960055399A KR19980036777A (en) | 1996-11-19 | 1996-11-19 | Semiconductor Chip Package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR19980036777A true KR19980036777A (en) | 1998-08-05 |
Family
ID=66321341
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019960055399A Withdrawn KR19980036777A (en) | 1996-11-19 | 1996-11-19 | Semiconductor Chip Package |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR19980036777A (en) |
-
1996
- 1996-11-19 KR KR1019960055399A patent/KR19980036777A/en not_active Withdrawn
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PA0109 | Patent application |
Patent event code: PA01091R01D Comment text: Patent Application Patent event date: 19961119 |
|
| PG1501 | Laying open of application | ||
| PC1203 | Withdrawal of no request for examination | ||
| WITN | Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid |