KR19980015364A - Field effect transistor and manufacturing method thereof - Google Patents

Abstract

Disclosed is a structure of a non-destructive read-out type field effect transistor employing a capacitorless memory device, particularly a ferroelectric thin film as a gate dielectric film, and a method of manufacturing the same. In order to activate the impurities for the formation of the source / drain of the transistor, a ferroelectric thin film which loses its ferroelectricity at high temperature can not be adopted as a gate film because a heat treatment at a high temperature is required in a process currently used, It is difficult to obtain ferroelectricity because natural oxide is formed on the silicon interface. Therefore, when the gate dielectric film is replaced with a non-oxide ferroelectric thin film, polycrystalline silicon source / drain is formed first, It's a dielectric barrier. Regular small source / drain increases the field-effect transistor by suppressing the reaction and current leakage possible between the two materials is shielded by the silicon oxide film.

Description

Field effect transistor and manufacturing method thereof

FIG. 1 is an equivalent circuit diagram of a conventional ferroelectric memory device. FIG.

FIG. 2 is a schematic diagram of a ferroelectric transistor according to the present invention. FIG.

3 is a cross-sectional view of a ferroelectric transistor according to the present invention;

4 (a) to 4 (k) are cross-sectional views of a ferroelectric transistor according to the present invention.

Description of the Related Art [0002]

1: Silicon substrate 2: active region

3: isolation region

A silicon oxide 4: a silicon oxide film 4: a silicon oxide film 4: a silicon oxide film 4: a silicon oxide film 4: a silicon oxide film 4: a silicon oxide film 5: Polycrystalline silicon film

4a and 4b: polycrystalline silicon (or polycide) source / drain

6a and 6b: a source / drain diffusion layer,

7, 15: gate dielectric film

8: Metal gate electrode

10, 10a, 10b, 10c: a silicon nitride film,

12a, 12b: photoresist

17a and 17b: a metal electrode,

The present invention relates to a transistor and a manufacturing method thereof, and more particularly, to a field effect transistor using a ferroelectric as a gate dielectric film and a method of manufacturing the same.

As shown in FIG. 1 (a), a conventional ferroelectric field effect transistor uses a ferroelectric thin film as a gate thin film, and the resistance between the source and the drain of the field effect transistor by the spontaneous polarization direction of the ferroelectric thin film A method of applying the method to a memory device has been studied.

Also, as shown in FIG. 1 (b), the dielectric film of the storage capacitor in the dynamic random access memory (DRAM) device structure can be made ferroelectric to make the recharging time very long.

According to the above, the SRAM has the same function as the static random access memory (SRAM), and the erasable programmable read only memory (EEPROM) is superior in performance to the erasable programmable read only memory .

However, in order to activate impurities for the formation of the source / drain of the field-effect transistor having the structure (a) in FIG. 1, since heat treatment at a high temperature (850 ° C. or more) is required in the currently widely used process, ferroelectricity is lost at high temperature It was impossible to adopt a ferroelectric thin film as a gate dielectric film. In addition, most of the ferroelectric thin films known to date are perovskite type oxides such as BaTiO ₃ , PbTiO _3, PZT, and KNbO ₃ . Therefore, when the oxides are directly used as a gate dielectric film, natural oxides are formed at the silicon interface, and it is very difficult to obtain ferroelectricity on silicon.

For the above reasons, a transistor structure which does not require a high-temperature process after forming a ferroelectric thin film is indispensable, and a non-oxide-based ferroelectric thin film is required.

In addition, BaMgF ₄ and the like have been developed in the nonoxide-based ferroelectric thin film to improve the thinning performance and the performance. Therefore, there is a demand for a field effect transistor structure in which a ferroelectric thin film is formed and then a high temperature process is not required.

Disclosure of the Invention The present invention has been made in view of the above-mentioned problems, and it is an object of the present invention to provide a non-destructive read-out field effect transistor employing a capacitorless memory deivce, particularly a ferroelectric thin film as a gate dielectric film, And a manufacturing method thereof.

In order to achieve the above object, a field-effect transistor according to the present invention is characterized in that a gate electrode is formed of a metal system and a gate dielectric film is a non-oxide-type ferroelectric thin film.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is an equivalent circuit diagram of a conventional ferroelectric memory device. In FIG. 1 (a), a ferroelectric thin film is used as a gate dielectric film to detect a change in resistance between a source and a drain of a field effect transistor due to the spontaneous polarization direction of the ferroelectric thin film A method for application to a memory device is being studied.

FIG. 1 (b) shows the same function as a static random access memory (SRAM) by making the recharge time very long by making the dielectric film of the storage capacitor a ferroelectric in a dynamic random access memory (DRAM) In addition to increasing the number of read and write, it can perform better than conventional electrically erasable programmable read only memory (EEPROM). However, in the above structure (a), since a heat treatment at a high temperature (850 DEG C or more) is required in a currently widely used process for activating impurities for forming a source / drain of a field effect transistor, a ferroelectric It was impossible to adopt a thin film as a gate dielectric film. In addition, most of the ferroelectric thin films known to date are perovskite-type oxides such as BaTiO ₃ , PbTiO ₃ , PZT, and KNbO ₃ .

If the oxides are directly used as a gate dielectric film, a native oxide is formed at the silicon interface, and it is very difficult to obtain ferroelectricity on silicon.

For the above reasons, a transistor structure which does not require a high-temperature process after forming a ferroelectric thin film is indispensable, and a non-oxide-based ferroelectric thin film is required.

As described above, BaMgF ₄ and the like have been developed in non-oxide based ferroelectric thin films to improve thinning performance and performance. Therefore, there is a demand for a field effect transistor structure in which a ferroelectric thin film is formed and a high temperature process is not required.

FIG. 2 is a schematic diagram of a ferroelectric transistor according to the present invention. The above structure shows a design of a field effect transistor in which polycrystalline silicon (or polycide) 4a, 4b is used as a source / drain.

FIG. 3 is a cross-sectional view of a ferroelectric transistor according to the present invention, showing the structure of FIG. 2 along a line AA '. The source / drain diffusion layers 6a and 6b are formed by polycrystalline silicon (or polycide), and the source / drain diffusion layers 6a and 6b are formed by the silicon- (P) and arsenic (As) impurities contained in the silicon substrate (4a, 4b) diffuse into the silicon substrate (1) while forming n ^- and n ⁺ diffusion layers, respectively. The gate dielectric film 7 is made of a ferroelectric material and the gate dielectric film 7 and polycrystalline silicon (or polycide) source / drain regions 4a and 4b are shielded by the silicon oxide films 5a and 5b, And suppresses the reaction or current leakage.

In addition, the metal gate electrode 8 is not made of polycrystalline silicon, which is generally used in a metal-oxide semiconductor (MOS) transistor, but is made of metal.

4a to 4k are cross-sectional views of the ferroelectric transistor of the present invention. In the above-mentioned process sequence, a shows that the silicon substrate 1 is formed by the silicon oxide films 3a and 3b. In the above structure, the silicon oxide films 3a and 3b are formed on the P-type silicon substrate 1 by thermal oxidation or chemical vapor deposition (CVD), and an active mask operation is performed Thereby removing the photosensitive film of the isolation region 3. After the removal of the photoresist, the oxide films 3a and 3b and the silicon substrate 1 are formed by reactive ion etching (RIE) to form a groove. Then, the surface of the groove is thermally oxidized, and chemical vapor deposition (CVD) ) Grooves are filled with a silicon oxide film and then the surface is planarized by etch-back or chemical-mechanical polishing (CMP) to form the structure shown in FIG. 4 (a).

FIG. 4 (b) is a cross-sectional view of a silicon nitride film 10 formed by a low pressure LPCVD process after forming a thermal oxide film or a chemical vapor deposition (CVD) And a vapor deposition (CVD) silicon oxide film 11 are sequentially formed. The thickness of the silicon oxide film 9 is 10 to 30 nm, and thermal oxidation is performed in a diffusion furnace at a temperature of 850 DEG C and an oxygen atmosphere for 15 to 30 minutes. In addition, the thickness of the silicon nitride film 10 as a 20~50nm, the nitriding is carried out at a temperature of 825 ℃ in a low pressure chemical vapor deposition (LPCVD), and SiH ₄ / NH ₃ / H ₂ atmosphere.

The thickness of the silicon oxide film 11 is 200 to 400 nm, and oxidation is performed in a SiH ₄ / O ₂ atmosphere by chemical vapor deposition (CVD).

FIG. 4C shows removal of the photoresist film of the source / drain region by performing a source / drain mask operation.

Accordingly, the photoresist films 12a, 12b, and 12c remain outside the source / drain regions.

FIG. 4 (d) shows the silicon oxide film 11, the silicon nitride film 10, and the silicon oxide film 9 of the source / drain region are sequentially etched by reactive ion etching (RIE) .

By the above process, the silicon substrate 1 on which the source / drain is to be formed is exposed.

4 shows that the polycrystalline silicon film 4 is formed by low pressure chemical vapor deposition (LPCVD) after removing the photoresist films 12a, 12b and 12c described above. Even if amorphous silicon is deposited instead of polycrystalline silicon It is acceptable.

The thickness of the polycrystalline silicon film 4 is about 50 to 100 nm thicker than the silicon oxide films 11a, 11b, and 11c.

In FIG. 4F, the polycrystalline silicon film 4 is flattened by chemical-mechanical polishing (CMP) until the silicon oxide films 11a, 11b and 11c are exposed.

For the chemical-mechanical polishing (CMP), a slurry obtained by mixing a KOH solution and silica is used.

In the above process, the silicon oxide films 11a, 11b, and 11c are hardly polished because the etching rate of the polycrystalline silicon film and the silicon oxide film is 20: 1 or more.

In addition, phosphorus (P) and arsenic (AS), which are the N-type impurities of the opposite type, are ion-implanted while the phosphorus dose is 5 to 20 × 10 ¹² cm ^-2 , the energy is 50 to 80 KeV, The ozone concentration is 2 to 6 × 10 ¹⁵ cm ^-2 and the energy is 50 to 100 keV.

However, the ion-implantation of phosphorus and arsenic may be performed in the step of FIG.

After the above steps are performed, a polycide (a metal silicide used for the gate electrode of the silicon integrated circuit and a two-layer structure including the polysilicon film) may be formed by depositing a metal on the polycrystalline silicon and then performing heat treatment.

G in the following FIG. 4 shows that the silicon oxide films 14a and 14b of 30 to 50 nm are formed by thermally oxidizing the polycrystalline silicon 4a and 4b formed in the source / drain region. The channel region is formed in the silicon nitride film 10b It is not thermally oxidized.

The above thermal oxidation is carried out at a high temperature of 850 DEG C for 20 to 60 minutes in an oxygen atmosphere.

In the above process, phosphorus and arsenic contained in the polycrystalline silicon 4a and 4b diffuse into the silicon substrate 1 to form the source / drain 6a and 6b.

And phosphorus diffuses deeper than arsenic to form n ^- layer, and arsenic diffuses less than phosphorus to form high concentration n ⁺ layer.

FIG. 4 (h) in the following figure shows removal of the above silicon nitride films 10a, 10b and 10c by using a phosphoric acid solution and removal of the silicon oxide films 9a by using a hydrofluoric acid solution.

In this process, the oxide films 14a and 14b are etched to be thinner than the original thickness, and the thicknesses of the silicon oxide films 5a and 5b become 20 to 40 nm.

The silicon oxide films 5a and 5b serve to prevent the ferroelectric thin film from reacting with the polycrystalline silicon source / drain and the gate / drain superposed capacitance from becoming large.

4 (i) in the following figure shows that the gate dielectric film 15 is formed as the gate insulating film.

As the gate dielectric film 15, a non-oxide-based ferroelectric thin film which does not form an oxide by reacting with an oxide-based ferroelectric, a two-layer structure of an oxide film and a ferroelectric thin film, or silicon is selected.

For example, BaMgF ₄ is deposited on a silicon substrate by ultra high vacuum (UHV) chemical vapor deposition (CVD).

4 (j) shows that the gate dielectric film 7 and the gate electrode 8 are formed.

A metal (W, Al or Al / TiW, a multilayer metal such as Cu / TiN) is deposited on the gate dielectric layer 15 by physical vapor deposition or metal organic chemical vapor deposition After the deposition of 500 to 1000 nm, a gate mask operation is performed to leave the photoresist film in the gate region. Then, the metal and the gate dielectric film 15 are etched by reactive ion etching (RIE) or wet etching to form the gate dielectric film 7 and the gate electrode (8).

And the source electrode 16a and the drain electrode 16b are formed by a general metal oxide semiconductor (MOS) process such as formation of a contact and formation of a metal wiring.

As described above, the field-effect transistor and the method of manufacturing the same may be applied to a field-effect transistor (FET) of a polycrystalline silicon source / drain, a gate dielectric film and a polycrystalline silicon source / drain are shielded by a silicon oxide It is possible to realize a manufacturing method capable of increasing the electric field effect of the transistor by suppressing possible reaction or current leakage between the two materials.

Claims (10)

A method for fabricating a non-destructive read (NORO) -type transistor employing a ferroelectric thin film as a gate dielectric film, A first step of forming an isolation region on the silicon substrate 1 with the silicon oxide films 3a and 3b, A silicon oxide film 10 and a chemical vapor deposition (CVD) silicon oxide film 11 are formed by low pressure chemical vapor deposition (LPCVD) after forming a thermal oxide film or a chemical vapor deposition (CVD) oxide film 9 on the substrate 1, In order, A third step of forming a photoresist film on the silicon oxide film 11 and performing a source / drain mask operation to remove the photoresist film only in the source / drain regions; A fourth step of successively etching the silicon oxide film 11, the silicon nitride film 10 and the silicon oxide film 9 of the source / drain regions from which the photoresist film is removed by reactive ion etching (RIE) A fifth step of removing the remaining photoresist films 12a, 12b, and 12c by etching in the third step and then forming a polycrystalline silicon film 4 by low pressure chemical vapor deposition (LPCVD) A sixth step of flattening the epitaxial polycrystalline silicon film 4 until the silicon oxide films 11a, 11b, and 11c are exposed, A seventh step of ion implanting P and As ions into the polycrystalline silicon films 4a and 4b formed in the source / drain regions and thermally oxidizing the silicon oxide films 14a and 14b; Removing the remaining silicon nitride films 10a, 10b, and 10c using a phosphoric acid solution, and removing the silicon oxide film 9 using a hydrofluoric acid solution; A ninth step of forming a non-oxide-based ferroelectric thin film 15 which does not form an oxide by reacting with an oxide-based ferroelectric, a two-layer structure of an oxide film and a ferroelectric thin film, A metal is deposited on the ferroelectric thin film 15 for PVD or MOCVD and then a gate mask is performed to leave the photoresist film in the gate region and then reactive ion etching (RIE) or wet etching Etching the metal and the ferroelectric thin film 15 to form a gate dielectric film 7 and a gate electrode 8; And forming a source electrode (17a) and a drain electrode (17b) by a contact formation process and a metal wiring formation process. 2. The method according to claim 1, Wherein the source / drain mask operation is performed after the active mask operation. The method of claim 1, wherein the fifth step Wherein the thickness of the lower silicon oxide film / the silicon nitride film / the upper silicon oxide film is 10 to 30 nm, 20 to 50 nm, and 200 to 400 nm, respectively. The method of claim 1, wherein the sixth step Wherein the polycrystalline silicon film (4) is planarized by chemical mechanical polishing (CMP). 2. The method of claim 1, wherein the step Wherein the silicon oxide films (14a, 14b) are formed by thermal oxidation only at the source / drain of the polycrystalline silicon (4a, 4b) so that the thickness is 30 to 50 nm. Silicon oxide films 3a and 3b formed for the isolation region on the substrate 1, A thermal oxidation film or a chemical vapor deposition (CVD) oxide film 9, a silicon nitride film 10 and a chemical vapor deposition (CVD) silicon oxide film 11, which are sequentially formed on the silicon oxide film, The polycrystalline silicon films 4a and 4b formed by deposition and chemical mechanical polishing (CMP) on the source / drain regions in which the chemical vapor deposition oxide film 9, the silicon nitride film 10, and the chemical vapor deposition silicon oxide film 11 are etched, 4b, Silicon oxide films 14a and 14b formed by thermally oxidizing the polycrystalline silicon films 4a and 4b, Source / drain diffusion layers 6a and 6b formed by diffusing phosphorus and arsenic contained in the polycrystalline silicon films 4a and 4b into the substrate 1 by the thermal oxidation, Silicon oxide films 5a and 5b formed to be thin when the silicon nitride film 10 and the silicon oxide film 9 are removed, A ferroelectric thin film 15 formed to insulate the gate electrode from the silicon nitride film and the silicon oxide film, And a ferroelectric thin film (7) formed by etching the ferroelectric thin film (15) and a gate electrode (8) formed on the ferroelectric thin film (7). The method according to claim 6, Wherein a channel region is protected from reactive ion etching (RIE) damage by using a multi-layer insulating film composed of a lower silicon oxide film, a silicon nitride film, and an upper silicon oxide film. The method according to claim 6, The thick silicon oxide films 5a, 5b, 5d, and 5e are formed using the silicon nitride film / silicon oxide film in the channel region only on the source / drain diffusion layers 6a and 6b to react with the ferroelectric thin films 7 and 15, Thereby preventing the drain overlapping capacitance from increasing. The ferroelectric thin film according to claim 6, An oxide-based ferroelectric oxide film, a ferroelectric thin film, or a non-oxide ferroelectric thin film such as BaMgF ₄ . 7. The semiconductor device according to claim 6, wherein the gate electrode (8) W, Al metal or Al / TiW, Al / TiN, and Cu / TiN.