KR19980014354A - Method of calculating floating gate voltage of EEPROM device - Google Patents

Abstract

The present invention relates to a method of calculating a floating gate voltage of an EEPROM device.

A typical EEPROM device is fabricated through a two-layer polysilicon gate process with a structure comprising a silicon substrate, a drain-source, an N + diffusion region gate oxide, a gate oxide, a first poly layer, a second poly layer, ONO and tunnel oxide .

A number of interlayer structures are regarded as a predetermined capacitance, an equivalent circuit diagram of the EEPROM is constructed, and a suitable expression for deriving the floating gate voltage is obtained by appropriately analyzing the equivalent circuit.

Description

Method of calculating floating gate voltage of EEPROM device

The present invention relates to a method of calculating a floating gate voltage of an EEPROM device.

A memory device manufactured by an integrated circuit (IC) technology can largely classify a RAM into a ROM. Of these, a read-only memory (ROM) is a memory for reading 0 or 1 digital data predetermined in each unit cell As a device, a mask ROM (Mask ROM) in which data is pre-stored in a manufacturing process and a programmable ROM (PROM) in which a user can directly write data after being shipped at a manufacturing factory can be divided again.

EEPROM (Electrically Erasable Programmable Read Only Memory) is an electrically writable and data erasable memory device and is generally manufactured through a double polysilicon gate process.

Actual device parameters need to be measured during these device fabrication processes, and such measurements require significant accuracy. The device parameter values accurately provided through simulation or the like for producing an appropriate integrated circuit device can not only predict the operation characteristics of the final device to be obtained but also determine the thickness and the impurity concentration of the silicon layer .

FIG. 1 is an enlarged cross-sectional view illustrating a typical semiconductor structure and its fabrication process in connection with a general EEPROM device.

The first layer is a silicon substrate, the second region is the drain of the EEPROM device, and the third region is the source of the EEPROM device. The fourth layer is a source and drain region composed of a 2500 angstrom thick BN ⁺ oxide region formed by heavily doping an N type donor, and a fifth layer is an oxide region for forming a tunnel as a silicon oxide formed by diffusing an N type donor.

In the same figure, the sixth layer is a gate oxide, the seventh layer is one poly layer, and the eighth layer is an ONO layer. The ninth layer is a gate oxide, and a second poly layer is formed on the ninth layer.

During the fabrication of the second poly layer, the same mask process is performed on the ONO layer 8 to form a second poly layer, which is denoted by 10. 11 is an N channel formed on the substrate 1 below the gate oxide 6.

Such a two-layer polysilicon gate process may be a method of first defining a source and a drain and then defining a second poly layer, or a method of first defining a first poly and a second poly layer and then forming a source and a drain.

A method of defining a source and a drain and then defining a second poly layer for the purpose of illustration will be described as follows.

More specifically, first, a gate oxide 6 and a first poly layer 7 are sequentially stacked on a silicon substrate 1, an oxide film is deposited, and then a source 3 region and a drain region 2) Define the area. It then spreads the N ⁺ donor. After the masking oxide film is removed, an oxidation process is performed to form gate oxide (9), and finally, polycrystalline silicon is coated to define the second poly layer (10).

This EEPROM semiconductor fabrication process significantly increases the parasitic effect of the capacitance since the second poly layer does not self-align with the N ⁺ diffusion region 4.

In order to store information in the EEPROM manufactured through such a process procedure, the drain voltage V _D and the gate voltage V _G are respectively set to predetermined set voltages, and the gate voltage V _G is set to the drain voltage V _D ) so that a channel is formed under which the charge moves under the first poly layer (7). At this time, the electrons are collected in the first poly layer through the gate oxide, which is a thin gate oxide film. At this time, the threshold voltage (V _T ) increases according to the amount of the electrons to be collected in the first poly layer 7, and the inversion disappears.

Also, when no electrons are present in the first poly layer 7, a channel is formed at a lower threshold voltage (V _T ) than in the case where the electrons are present, and this state can be defined as 1.

The first poly layer 7 performing the above operation is not electrically connected to the outside and is called a floating gate.

An object of the present invention is to calculate the voltage to be applied to a floating gate in an EEPROM device and to advantageously perform an integrated circuit manufacturing process using the calculated device parameters.

FIG. 1 is an enlarged cross-sectional view illustrating a semiconductor structure of a general EEPROM; FIG.

FIG. 2 is an equivalent circuit diagram of an EEPROM device used to calculate a floating gate voltage according to the present invention; FIG.

DESCRIPTION OF REFERENCE NUMERALS IN THE DRAWINGS

1: substrate 2: drain

3: source 4: buried N ⁺ diffusion region

5: BN oxide 6: gate oxide

7: first poly 8: ONO

9: gate oxide 10: second poly

C ₁ , C ₂ , C ₃ , C ₄ : Capacitance

In order to achieve the above object, the present invention proposes an equivalent circuit consisting of a predetermined capacitance between respective individual layers with respect to a laminated structure of an EEPROM, and calculates the floating gate voltage of the EEPROM device using this equivalent circuit.

Hereinafter, a specific configuration, actions, and effects of the present invention will be described in detail with reference to FIG. 2 attached hereto.

FIG. 2 is an equivalent circuit diagram of a pair of EEPROM elements for implementing the floating gate voltage calculation method according to the present invention.

The equivalent circuit of the EEPROM according to the present invention has four capacitances in total. The second capacitance C ₂ and the third capacitance C ₃ are connected in parallel and the first capacitance C ₁ is connected to one side of the parallel circuit. Respectively. And the other side of the first capacitance C ₁ not connected to the parallel circuit is connected to the power supply voltage + 5V.

Other connection points not connected to the first capacitance C ₁ of the parallel circuit of the second capacitance C ₂ and the third capacitance C ₃ are grounded.

The fourth capacitance C ₄ is connected in parallel to the circuit formed by connecting the parallel capacitance of the second capacitance C ₂ and the third capacitance C ₃ and the first capacitance in series. That is, one side of the fourth capacitance C ₄ is given a power supply voltage + 5V and the other side is grounded.

Each element shown in FIG. 2 having the circuit configuration as described above will be described in connection with the first aspect.

Note that in FIG. 1, the interlayer structure in which the ONO layer 8 is interposed between the second poly layer 10 and the first poly layer 7 will be noted. The second poly layer is electrically connected to an external lead wire connected to the power supply voltage + 5V to constitute one side of the capacitor electrode, and the ONO layer 8 inserted at the center is a dielectric thin film serving as a dielectric of the capacitance.

The first poly layer 7 does not have any external electrical contact, but operates as a floating gate, thereby constituting another electrode side of the capacitance. Accordingly, the first capacitance C _{1 of} FIG. 2 represents a structure formed by the first poly layer 7, the ONO layer 8 and the second poly layer 10.

Next, in relation to the second capacitance C ₂ , one side of the electrode is constituted by the first poly layer 7, that is, the floating gate electrode, one side of the capacitance electrode, and the tunnel oxide formed in the center in the form of a thin layer serves as a dielectric of the capacitance And the N ⁺ diffusion region 4 buried in the lower portion forms another side of the capacitance.

Thus, the second capacitance C ₂ represents a structure formed by the first poly layer 7, the tunnel oxide and the N ⁺ diffusion region 4.

In the case of the third capacitance C ₃ , the first poly layer 7 included to constitute the first and second capacitors also constitutes one side of the capacitance electrode, and the gate 1 oxide 6 is connected to the first And is disposed under the poly layer 7 to serve as a dielectric of the capacitance, and the N-channel 11 is responsible for the other electrode.

The third capacitance C ₃ represents a structure formed by the first poly layer 7, gate oxide 6 and N channel 4.

On the other hand, in the laminated structure of the second poly layer 10, the BN oxide region 6 and the N ⁺ diffusion region 4 shown on the right side of the drawing in FIG. 1, the second poly layer 10 is formed on one side The BN oxide region 5 serves as a dielectric inserted in the capacitance, and the N ⁺ diffusion region 4 used in conjunction with the first and second capacitances constitutes the other side of the capacitance.

Therefore, the fourth capacitance can be displayed instead of this laminated structure.

In the thus-combined electric circuit of the present invention, the voltage applied between the first capacitance and the second and third capacitance parallel parts, that is, the first poly layer, may be expressed by the floating gate voltage (VFG).

When a general circuit analysis is introduced, the floating gate voltage (VFG) is expressed by the following equation.

According to this equation, the floating gate voltage (VFG) of the complex multi-layered EEPROM can be calculated by simple calculation using measurements according to the interlayer structure represented by the first capacitance, the second capacitance, the third capacitance and the fourth capacitance, respectively .

The first, second, third, and fourth capacitances are relatively easy to measure, unlike the floating gate voltage, which is difficult to directly measure the voltage because there is no external physical contact at this time.

As described above in detail, the present invention can easily derive the floating gate voltage of an electrically recordable and erasable ROM device using a plurality of capacitance values due to a semiconductor internal structure in a semiconductor process It is a useful invention to make it possible.

Claims (1)

In the EEPROM device, a first capacitance C ₁ representing a structure formed of the first poly layer 7, the ONO layer 8 and the second poly layer 10, A second capacitance C ₂ representing a structure formed of the first poly layer 7, the tunnel oxide and the N channel 11, A third capacitance C ₃ representative of the structure formed by the first poly layer 7, the gate 1 oxide 6 and the N ⁺ diffusion region 4, and A fourth capacitance C ₄ representative of the structure formed by the second poly layer 10, the BN oxide region 5 and the N ⁺ diffusion region 4, At this time, the second capacitance C ₂ and the third capacitance C ₃ form a parallel circuit, the first capacitance C ₁ is connected in series to the parallel circuit, and a fourth capacitance C ₄ are connected in parallel and a predetermined power source voltage is applied to a contact between the _first and fourth capacitors C ₁ and C ₄ and the _second and third capacitances C ₂ and C ₃ as constituting the EEPROM equivalent circuit is a ground contact point of the parallel circuit one end and a fourth capacitance (C _4), a parallel circuit of the first capacitance (C ₁₎ and the second, the third capacitance (C _2, C ₃₎ The voltage of the connected contact point is defined as the floating gate voltage (VFG) Wherein the floating gate voltage of the EEPROM device is calculated based on the calculated floating gate voltage.