KR19980014926A - Logic array devices for high-speed ordering - Google Patents

Abstract

The present invention relates to a logic array device for high-speed ordering,

At least one gate array having a plurality of identical unit logic cells and a circuit board having first, second and third metal layers formed on the gate layer,

NAND, NOR, INVERTER, AND, and OR functions,

And the ratio between the rise time and the fall time of the logic cell having each of the at least three functions is constant.

Description

HIGH SPEED CUSTOMIZABLE LOGIC ARRAY DEVICE

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic array device for high-speed ordering used in a special purpose integrated circuit, and more particularly to a structure of a main building block of a gate array.

In general, microelectronic integrated circuits can be classified into two types, ready-made and custom-made. The customized product can be classified into three types: full-custom, standard cell, and gate array. The gate array is simpler to design and manufacture than the other two types. The gate array includes one type of building block. The metal interconnect layer should be ordered for each application. The basic building block, referred to as a unit logic cell, is typically of the NAND type.

Recently, complex unit logic cells have been proposed for use in gate arrays. For example, each unit logic cell is a high-density multiplexer-based architecture of RJ LANDERS, SS Mahant-Shetti, and C. Lemonds. For High Density, Low Power Gate Arrays, and Volume 30 of April, 1995, the solid-state circuit of the IEEE Journal, number 4, pages 392-396, State Circuits.

The complex unit logic cell has the advantage of reducing final power consumption and design area.

See Delay Effect Rule in Deep Submicron ICs in Precision Submicron Integrated Circuits by C. Maxfield in Electronic Design (PP 109 - 122), published June 12, 1995 The gate array, which is becoming increasingly important as a geometry device for cooling millions of incremental gate count devices and the deep sub-micron regime, usually includes NAND cells with two input stages Unit logic cell, and the conventional gate array has various disadvantages summarized as follows.

Referring to FIG. 1A, if another logic function, such as a NAND gate and a NOR gate, is applied to a unit logic cell of a gate array having one fixed size transistor, even if the unit logic cell is driven with the same load, The slope of the rising and falling time of the output signal of the output signal is very different. This phenomenon complicates the calculation and calculation of the signal delay by analogy from other logic cells.

Referring to FIG. 2A, when a unit logic cell is applied to another logic function, the input threshold switching voltage of the unit logic cell is functionally dependent. For example, in some cell libraries, if the logic cells are different, the voltage Vcc is switched differently between 0.28 and 0.5 hours. The functional dependent slope phenomenon of the output signal described above and the functional dependence of the input switching voltage limit greatly complicate the calculation of switching timing and signal delay. Moreover, the secondary complexity of the conventional gate array is that of the signal slope function into which the switching point of the gate array is input. Here, if the response to the late switching signal occurs at 0.3 Vcc, the response to the fast switching signal will occur at 0.4 Vcc. This is known as SLOPE-DEPENDENT DELAY.

Referring to FIG. 3A, in a conventional gate array, the slope of the gate drive capacity and the output signal is a function according to the logic state (0 or 1) of another input terminal input to the gate. This is known as STATE DEPENDENT DRIVE CAPABILITY.

Referring to Figure 4A, in a conventional gate array, the slope of the gate drive capability and the output signal depends on the input causing the output. This is known as the PATH-DEPENDENT DRIVE CAPABILITY.

Referring to FIG. 5A, in a conventional gate array, a delay between a transition occurring when inputting to the gate and a transition occurring when outputting from the gate corresponds to a function of a logic state (0 or 1) of another input terminal input to the gate . This is known as state-dependent pin-to-pin delay (STATE DEPENDENT PIN-TO-PIN DELAY).

As a result of the above-described phenomenon, the total delay of the input stage to the gate and of the load gate is varied by more than 100% between the transition and the transition in the deep sub-micron technology.

One way to overcome these difficulties is to develop a simulation tool with computer design and very precise algorithms.

Accordingly, it is an object of the present invention to provide a gate array having a unit logic cell design capable of eliminating the above-described phenomenon.

According to an embodiment of the present invention, there is provided a logic array device for high-speed ordering, comprising: a circuit board having at least one gate array and including at least a first metal layer, a second metal layer and a third metal layer; And a gate layer including a unit logic cell.

The ordering logic array device includes at least three of the following characteristics: NAND, NOR, inverter, AND, and OR characteristics. In addition, the ratio of the rise time and the fall time of the logic cell including at least three characteristics is constant.

That is, the ratio of rise time to fall time is approximately 1.

A logic array device for high-speed ordering according to a preferred embodiment of the present invention includes a circuit board having at least one gate array and including at least a first metal layer, a second metal layer, and a third metal layer, and a plurality of the same unit logic cells And a gate layer including the gate electrode.

The custom logic array device includes at least three of the following characteristics: NAND, NOR, inverter, AND, and OR characteristics. Further, if the drive circuits are the same, they have the same rise time and same fall time.

In addition, a logic array device for high-speed ordering according to a preferred embodiment of the present invention includes a circuit board having at least one gate array and including at least a first metal layer, a second metal layer, and a third metal layer, And a gate layer including a cell.

The custom logic array device includes at least three of the following characteristics: NAND, NOR, inverter, AND, and OR characteristics. Also, at least three of the features operate at a similar timing to a similar switching voltage.

A logic array device for high-speed ordering according to a preferred embodiment of the present invention includes a circuit board having at least one gate array and including at least a first metal layer, a second metal layer, and a third metal layer, and a plurality of the same unit logic cells And a gate layer including the gate electrode.

The custom logic array device includes at least three of the following characteristics: NAND, NOR, inverter, AND, and OR characteristics. Also, at least three of the features work with one similar switching voltage.

The timing according to the preferred embodiment of the present invention is state independent.

The three characteristics of the switching voltage differ by at most 10%.

A plurality of unit logic cells according to a preferred embodiment of the present invention constitute at least one multiplexer.

The characteristic is implemented by an arrangement of one of a second metal layer and a third metal layer.

One of the logic cells with the same rise time and fall time according to the inventive practice of the present invention has a load of at least 10 ^-9 seconds for a 0.6 micron CMOS technology.

1A is a characteristic diagram of a conventional gate array showing rise and fall time characteristics of signal voltages that are differently output in the NAND2 and NOR2 functions

FIG. 1B is a characteristic diagram of a gate array according to the present invention showing rise and fall time characteristics of a signal voltage output in the NAND2 and NOR2 functions

2A is a characteristic diagram of a conventional gate array showing the characteristics of a thresholded switching voltage that is differently output in NAND2 and NOR2 functions

FIG. 2B is a characteristic diagram of a gate array according to the present invention showing the characteristics of a threshold switching voltage that is similarly output in NAND2 and NOR2 functions

3A is a characteristic diagram of a conventional gate array showing a slave state of the output drive capacity

3B is a characteristic diagram of the gate array according to the present invention showing the independent state of the output drive capacity

4A is a characteristic diagram of a conventional gate array showing a slave path of a driving capacity

4B is a characteristic diagram of a gate array according to the present invention showing an independent path of a driving capacity

5A is a characteristic diagram of a conventional gate array showing a dependent state of a PIN-TO-PIN DELAY TIME

5B is a characteristic diagram of the gate array according to the present invention showing the independent state of the pin-to-pin delay time

6 is a schematic diagram showing a unit logic cell according to the present invention

Figure 7 is a schematic diagram illustrating the transistor levels that make up the unit logic cell of Figure 6 in accordance with the present invention;

Figures 8A, 8B, 8C, 8D and 8E illustrate five different embodiments of the unit logic cells of Figures 6 and 7,

Description of the Related Art

10: unit logic cell 12: first multiplexer

14: second multiplexer 16, 18, 20, 22:

28: Optional inputs 30, 32, 56, 156: Outputs

50, 62, 70, 80, 90, 150, 162, 170, 190:

52, 60, 72, 82, 92, 152, 160, 172, 192: N transistors

Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 1 to 8. FIG.

6, a unit logic cell 10 according to the present invention includes a first multiplexer 12 and a second multiplexer 14, . Here, the output terminal of the first multiplexer 12 becomes the selection input terminal of the second multiplexer 14.

The first multiplexer 12 has a first input stage 16, a second input stage 18, a selection input stage 28 and an inverted output stage (not shown) which provides an output as a selected input of the second multiplexer 14 30).

The second multiplexer 14 is comprised of a first input 20, a second input 22 and an inverted output 32.

Referring to FIG. 7, FIG. 7 is a schematic diagram illustrating the transistors that make up the unit logic cell 10 of FIG. 6 according to the present invention, wherein the first multiplexer 12 is comprised of ten, Is different. 6) is connected to the gate of P transistor 50, which is typically 6.5 microns wide, and to the gate of N transistor 52, which has a width of 2.1 microns. The transistors 50 and 52 are connected to each other and constitute a CMOS inverter 54. [ The output 56 of CMOS inverter 54 is connected to the gate of N transistor 60, which is typically 3.6 microns wide, and to the gate of P transistor 62, which is 10 microns wide.

The dimensions of the transistor described above can be found in the process file known as TS60T of TOWER SEMICONDUCTOR LTD. Of MIGDAL HAEMEK, Israel. All of the transistors described above have a channel length of 0.6 microns. Other dimensions are the same as manufactured semiconductors used in different process files, and related dimensions are used for the same semiconductor.

6) is connected to the gate of P transistor 70, which is typically 10 microns wide, and to the gate of N transistor 72, which has a width of 3.6 microns.

6) is connected to the gate of P transistor 80, which is typically 10 microns wide, and to the gate of N transistor 82, which is 3.6 microns wide. Input terminal 16 (see Figure 6) Is typically connected to the gate of P transistor 90 having a width of 10 microns and to the gate of N transistor 92 having a width of 3.6 microns.

The multiplexer is composed of the above-described transistor array, and the output terminal 30 of the multiplexer is connected to the drains of the transistors 62 and 70 and to the sources of the transistors 60 and 72.

The output 30 of the first multiplexer 12 is coupled to the gate of a P transistor 150 having a width of typically 7 microns and the N transistor 152 having a width of 2.5 microns as a selected input of the second multiplexer 14, Respectively. The transistors 150 and 152 are connected to each other and constitute a CMOS inverter 154. The output stage 156 of the CMOS inverter 154 is connected to the gate of the N transistor 160, which is typically 2.1 microns wide, and the gate of the P transistor 162, which is 6.5 microns wide.

6) is connected to the gate of P transistor 170 having a width of 6.5 microns and the gate of N transistor 172 having a width of 2.1 microns.

6) is connected to the gate of P transistor 180 having a width of 6.5 microns and to the gate of N transistor 182 having a width of 2.1 microns.

The output stage 30 (see FIG. 6) is connected to the gate of P transistor 190 having a width of 6.5 microns and the gate of N transistor 192 having a width of 2.1 microns.

The multiplexer 14 is comprised of the transistor arrangement described above and the output 32 of the multiplexer constitutes the output of the unit logic cell and is connected to the drains of the transistors 162 and 190 and to the sources of the transistors 160 and 192 .

The circuit shown in FIG. 7, which provides unit logic cells with the following advantages, will be able to demonstrate its effectiveness by those skilled in the art using a simulation program such as HSPICE, a META-SOFTWARE INC. Product.

A. The output signal of a unit logic cell with the same rising and falling time slopes, as shown in FIG. 1B.

B. As shown in FIG. 2B, the possibility of a logic function implemented by a unit logic cell at a 0.5 Vcc switching voltage

C. As shown in FIG. 3B,

D. As shown in Fig. 4B,

E. As shown in Figure 5B, when the state is an independent pin-to-pin delay

The unit logic cells described in connection with Figures 6 and 7 are operated to provide many other logic functions, some of which are shown in Figures 8A-8E.

8A, logic 1 is input to the input stage 20, logic 0 is input to the input stage 22, logic 0 is input to the input stage 16, and variables B and A Respectively, the unit cell acts as a NAND gate.

8B, logic 1 is input to the input stage 20, logic 0 is input to the input stage 22, logic 1 is input to the input stage 18, and variables B and A Respectively, the unit cell acts as a NOR gate.

8C, a logic 0 is input to the input terminal 20, a logic 1 is input to the input terminal 22, a logic 0 is input to the input terminal 16, and variables B and A Respectively, the unit cell acts as an AND gate.

8D, a logic 0 is input to an input terminal 20, a logic 1 is input to an input terminal 22, a logic 1 is input to an input terminal 18, and variables B and A Respectively, the unit cell acts as an OR gate.

8E, a logic 1 is input to the input stage 20, a logic 0 is input to the input stage 22, a logic 0 is input to the input stage 16, a logic 1 is input to the input stage 18, When the variable A is input to the input terminal 28, the unit cell acts as an inverter.

The transistor arrangement of FIG. 7 may be provided and operated on the logic functions shown in FIGS. 8A-8E, and the logic functions described above apply to the same unit logic cells as FIG. All these logic functions have the same timing, delay, output, switching voltage and drive characteristics.

Furthermore, the unit logic cells of FIG. 7 are designed to be state independent and can generate various logic functions by setting them to input logic 0 and 1, and this logic pulse maintains the arrangement characteristics of the FIG. 7 device. The various functions have the same output characteristics.

The configuration and operation of the unit logic cell according to the preferred embodiment of the present invention is useful in constructing logic libraries for gate arrays that are based on these unit logic cells. One unit cell that is predictable and simple consists of over 200 different logic functions. (Only five functions have been described above.) Furthermore, due to the special function of the unit logic cell, these characteristics exist across the entire library. For example, all library cells have the same Vcc / 2 switching voltage. While the operation of relatively simple logic functions appears to be lower than the optimal efficiency, the operation of the complex logic function is direct and highly efficient.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, will be.

Claims (11)

At least one gate layer having a plurality of identical unit logic cells and a circuit board having first, second and third metal layers formed on the gate layer, NAND, NOR, INVERTER, AND, and OR functions, Wherein the ratio between the rise time and the fall time of the logic cell having each of the at least three functions is constant. The method according to claim 1, Wherein the ratio between the rise time and the fall time is one. At least one gate layer having a plurality of identical unit logic cells and a circuit board having first, second and third metal layers formed on the gate layer, NAND, NOR, INVERTER, AND, and OR functions, Wherein the three functions have the same rise time and fall time in the same drive circuit. At least one gate layer having a plurality of identical unit logic cells and a circuit board having first, second and third metal layers formed on the gate layer, NAND, NOR, INVERTER, AND, and OR functions, Wherein all three of the functions operate under conditions of a similar switching voltage and timing generally. At least one gate layer having a plurality of identical unit logic cells and a circuit board having first, second and third metal layers formed on the gate layer, NAND, NOR, INVERTER, AND, and OR functions, Wherein all three of the functions operate at similar switching voltages. The method according to claim 1, Wherein all three of the functions operate at generally similar switching voltages. The method according to claim 1, Wherein the timing is state independent. 6. The method according to any one of claims 1 to 5, Wherein the switching voltages of at least three functions differ by at most 10% from each other. The method according to claim 1, Wherein the plurality of unit logic cells each include at least one multiplexer. The method according to claim 1, Wherein the NAND, NOR, INVERTER, AND, and OR functions are performed by arranging at least one of the second and third metal layers. The method according to claim 1, Wherein at least one of the logic cells drives a load of the other one of the logic cells, wherein a rise time and a fall time for at least one of the logic cells is less than 10 < ^-9 > seconds.