KR19980013940A - Method for manufacturing a read-only nonvolatile semiconductor memory device - Google Patents

Abstract

FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention. FIG. A method of manufacturing a volatile semiconductor memory device, comprising: Forming a photoresist pattern covering element active regions of the peripheral circuit region and overlapping an element isolation region edge of the peripheral circuit region to a certain extent, and forming a device active region of the cell array region exposed by the photoresist pattern In order to improve device isolation characteristics in a part of the device isolation region exposed in the device isolation region and the peripheral circuit region, a typical field ion implantation is formed. In the same photoresist pattern, Forming a channel region, and forming a gate oxide film, a gate electrode, a source / drain, and a contact on the resultant structure. Therefore, the conventional photolithography process for forming the doping profile and the depletion channel region can be shortened to one photolithography process, and the productivity and cost can be reduced by about 10%.

Description

Method for manufacturing a read-only nonvolatile semiconductor memory device

The present invention relates to a method of manufacturing a nonvolatile semiconductor memory device, and more particularly, to a method of manufacturing a read-only nonvolatile semiconductor memory device.

In general, read-only nonvolatile semiconductor memory devices, i.e., maschromes, are nonvolatile memory devices that can permanently store information through the use of custom masks during the manufacturing process. Therefore, the user must provide the ROM manufacturer with a bit pattern of the desired memory. The stored data can not be changed and only the read operation is possible. These memory circuits are implemented by bipolar, enmos, and cmos technology. Currently, twin or tube (well or twin tube) is being actively pursued based on Moos technology. The program process for inputting information on or off of the SiMOS masks is performed by adjusting the threshold voltage of the cell transistors in the cell array region. For example, programming by the implementation of the off-cell transistor initializes the cell transistor in a depletion type at the initial stage of the process, and after the formation of the gate, high energy boron ions are selectively implanted over the gate, And the voltage is formed to be high. On the contrary, programming by the implementation of the on-cell transistor is to change the channel concentration in a depletion type by implanting ions selectively after gate formation in the initial enhancement. At this time, the off-cell programming process requires a process for initializing the entire cell transistor to on-cell, i.e., a depletion type initialization process. The on-cell programming process does not require an initialization process, One mask process is reduced. However, in the on-cell programming process, phosphorous or arsenic impurities for lowering the threshold voltage are larger in mass than the boron used in the off-cell programming process and require a large amount of energy for gate penetration of the same thickness. Accordingly, not only the programming process is limited according to the performance of the ion implanter, but also ions having high energy penetrate into the device isolation film due to misalignment in the process and variation in the pattern size after etching, deteriorating the device isolation characteristics. For this reason, conventional mask ROM production uses the off-cell programming process. That is, there is a need for a process for initializing the entire cell array in a depletion type before gate formation.

1 to 3 are views showing a method of manufacturing a read-only nonvolatile semiconductor memory device according to an embodiment of the related art. Referring first to FIG. 1, a conventional local oxidation process (LOCOS), such as an etch-back local oxidation process or a polybuffer local oxidation process, has a reduced buried surface and a planarized surface, The separation membranes 16a to 16g are formed by wet oxidation. The peripheral circuit regions 4 and 6 and the cell array region 2 of the CMOS are separated by the element isolation film 16d, and the CMOS peripheral circuit regions 4 and 6 are divided into the n channel region 4 and the L channel region 6, respectively. The channel region 6 has a well region 10 of opposite conductivity type under the channel. This well region 10 can be formed after or before the formation of the device isolation film. On the other hand, in order to improve the isolation characteristics of the n channel region 4, the impurity boron of the same conductivity type as that of the impurity of the substrate, for example, Group 3 of the periodic table is ion implanted at about 130 keV. At this time, a mask is formed on the active region of the to-be-channel region 6 to form the ion implantation. Such ion implantation is generally referred to as a local ion implantation after field oxidation process after the device isolation film is formed. As a result, the doping profiles 22a and 22b are formed, so that the isolation characteristics of the n channel region 4 are improved. The doping profiles 22a and 22b form peaks at the bottom of the device isolation films 16a to 16g depending on the thickness of the device isolation films 16a to 16g. The doping profiles 22a and 22b are formed deeply in the active region by the transmission range. The device characteristics are not greatly affected. Thereafter, though not shown in the drawing, a threshold voltage adjusting ion implantation for adjusting the threshold voltage by changing the surface concentration of the channel is performed.

2, the peripheral circuit regions 4 and 6 for forming the channels of the cells in the cell array region 2 in an initialized state, i.e., a depletion type, are completely cut off by the mask 12, and arsenic ions, which are impurities of Group 5 on the periodic table, The depletion region 14 is formed by injecting the device isolation film by self-alignment. At this time, since the transmission range is about 350 to 500 ANGSTROM, the device isolation films 16a to 16c of about 2000 ANGSTROM or more can not be transmitted, and ions are implanted only on the active region.

3 selectively forms gate oxide films and gate electrodes 18, 18a, 18b and 18c, which are not shown in the figure, in the resultant initialized in the depletion type. Thereafter, the above-mentioned maschromium is produced through a general procedure such as a contact process and a metal process process. Among the above-described embodiments, the process for forming the doping profile 22 and the process for forming the channel region into the depletion type 14 are divided into two processes as separate masks.

Accordingly, an object of the present invention is to provide a method of manufacturing a read-only nonvolatile semiconductor memory device for carrying out a process for forming a doping profile for the channel isolation and a process for initially depleting a channel region in the same mask pattern .

It is another object of the present invention to provide a method of manufacturing a diurnal nonvolatile semiconductor memory device having an off-programming process of a simple manufacturing method.

FIGS. 1 to 3 illustrate a method of manufacturing a read-only nonvolatile semiconductor memory device according to an embodiment of the related art; FIG.

4 and 5 illustrate a method of manufacturing a read-only nonvolatile semiconductor memory device according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the drawings, the same reference numerals are used for the same reference numerals even though they are shown in different drawings. It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention.

4 and 5 are views showing a method of manufacturing a read-only nonvolatile semiconductor memory device according to an embodiment of the present invention. Referring to FIG. 4, device isolation films 16a to 16g are formed on a semiconductor substrate 8 by a conventional local oxidation process (LOCOS) such as an etch back local oxidation process or a poly buffer local oxidation process to define an activation region, And the peripheral circuit regions 4 and 6 and the cell array region 2, respectively. And further subdivided into the endo-conduction channel region 4 and the conduction-type channel region 6 of the circuit regions 4 and 6. Figure 4 cuts the entire device active area of the endothelial channel region 4 with masks 12a, 12b. At this time, the masks 12a and 12b overlap the edges of the element isolation films 16d to 16f. The width of the mask that overlaps the edge is about 0.1 to 0.3 mu m so as to secure a process margin for masking the entire active region. On the other hand, a mask 12c is formed on the entire surface of the device isolation region and the to-be-processed active region formed on the end-effected well region 10 of the processed channel region 6, and the exposed active region of the cell array region 2 and the isolation region 16a 16b and 16c, primary ion implantation is performed on a part of the surface of the element isolation region 16d with boron ions to improve device isolation characteristics. FIG. 1 shows a typical doping profile, that is, a circular field region 22, A second ion implantation is performed with arsenic ions to form a depletion channel region 14. [ That is, unlike the conventional embodiment, the doping profile 22 and the depletion channel region 14 are formed by one process on the same mask pattern. However, the primary and secondary ion implantation are performed independently.

5 selectively forms a gate oxide film, gate electrodes 18, 18a and 18b on the depletion channel region 14. [ The manufacturing process is then completed through conventional manufacturing processes. The endocellular channel region 4 of the peripheral circuit regions 4 and 6 is opened at the time of ion implantation of the doping profile formation (Enfield formation) for enhancing the device isolation characteristic, and at the time of ion implantation for the formation of the depletion channel region, According to the present invention as described above, the active region is shielded by a mask at the time of ion implantation for enfilming formation or depletion channel region formation to enhance device isolation characteristics. That is, the difference of the prior art is that the doping profile of the encapsulation field formation for enhancing the device isolation characteristic is not formed in the active region of the channel region 4. However, the threshold voltage thereof is lowered by about 0.05 to 0.1 V, but this can be compensated by the ion implantation process for the subsequent threshold adjustment, and the above-described reduction of the threshold voltage does not cause a problem due to punch through. Also, the depletion channel region formed by the second ion implantation performed independently is not formed in the channel region 4, and the ions that are secondarily implanted by the thickness of the isolation film 16d can not be transmitted. That is, only the primary ions are transmitted.

The present invention has the effect of shortening the conventional photolithography process for forming the doping profile and the depletion channel region to one photolithography process, thereby improving the productivity and reducing the cost by about 10%.

Claims (2)

FIG. 1 shows a read-only nonvolatile semiconductor memory (hereinafter referred to as " nonvolatile semiconductor memory ") formed by a device isolation region and a device active region formed on a typical semiconductor substrate, A method of manufacturing a device, comprising: Forming a photoresist pattern covering element active regions of the peripheral circuit region and overlapping an element isolation region edge of the peripheral circuit region to a certain extent, and forming a device active region of the cell array region exposed by the photoresist pattern In order to improve device isolation characteristics in a part of the device isolation region exposed in the device isolation region and the peripheral circuit region, typical field ion implantation is performed. In the same photoresist pattern, And forming a gate oxide film, a gate electrode, a source / drain, and a contact on the resultant structure. The method of claim 1, further comprising: Wherein the field ion implantation of the first conductive type and the ion implantation of the typical ion implantation of FIG. 2 are independently performed in the same photoresist pattern.