KR102849309B1 - Semiconductor integrated circuit for minimizing leakage currents of power transistors, and method thereof - Google Patents

Abstract

A semiconductor integrated circuit capable of minimizing leakage current of each power transistor is disclosed. The semiconductor integrated circuit includes a first electronic circuit connected to a first node, a second electronic circuit connected to a second node, a first power transistor controlling a first virtual operating voltage of the first node in response to a first bias voltage, a second power transistor controlling a second virtual operating voltage of the second node in response to a second bias voltage, and a bias voltage control circuit comparing the first virtual operating voltage and the second virtual operating voltage to generate a comparison signal, and controlling the first bias voltage and the second bias voltage respectively so that a first leakage current of the first power transistor and a second leakage current of the second power transistor are each minimized according to the comparison signal.

Description

Semiconductor integrated circuit for minimizing leakage currents of power transistors and method thereof {SEMICONDUCTOR INTEGRATED CIRCUIT FOR MINIMIZING LEAKAGE CURRENTS OF POWER TRANSISTORS, AND METHOD THEREOF}

The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor integrated circuit and a method thereof capable of minimizing leakage currents of power transistors by controlling a frequency or capacitance related to the control of bias voltages supplied to power transistors using a comparison result of virtual operating voltages.

As CMOS process technology enters the nanoscale realm, power consumption is becoming a critical factor in VLSI design. As processes become increasingly miniaturized, supply voltages continue to decline, and to maintain logic performance, transistor threshold voltages must decrease proportionally, leading to an exponential increase in leakage power.

The increasing leakage power can be reduced by using methods such as transistor sizing, transistor stacking, dual/multi-Vth cells, body biasing, dynamic voltage scaling, or power gating. Among them, power gating is known to be the most effective method for reducing the circuit's leakage current in sleep mode while maintaining high performance in active mode.

Patent Registration: Registration No. 10-2022355 (Published on September 18, 2019) U.S. Patent Publication No.: US2023/0298840 (published on September 21, 2023) Patent Publication No. 10-2020-0120496 (Published October 21, 2020)

The technical task to be achieved by the present invention is to provide a semiconductor integrated circuit and a method thereof capable of minimizing leakage currents of the power transistors by comparing virtual operating voltages supplied to electronic circuits through power transistors and automatically controlling the virtual operating voltages based on the comparison result.

A semiconductor integrated circuit according to embodiments of the present invention includes a first electronic circuit connected to a first node, a second electronic circuit connected to a second node, a first power transistor controlling a first virtual operating voltage of the first node in response to a first bias voltage, a second power transistor controlling a second virtual operating voltage of the second node in response to a second bias voltage, and a bias voltage control circuit comparing the first virtual operating voltage and the second virtual operating voltage to generate a comparison signal, and controlling each of the first bias voltage and the second bias voltage to minimize a first leakage current of the first power transistor and a second leakage current of the second power transistor, respectively, according to the comparison signal.

According to embodiments, the bias voltage control circuit includes a first bias voltage control circuit that controls a first frequency of a first non-sinusoidal wave according to the comparison signal and controls the first bias voltage according to the first frequency, and a second bias voltage control circuit that controls a second frequency of the second non-sinusoidal wave according to the comparison signal and controls the second bias voltage according to the second frequency.

According to embodiments, the bias voltage control circuit includes a first bias voltage control circuit that generates a first digital signal using the comparison signal and controls a first capacitance using the first digital signal to generate the first bias voltage, and a second bias voltage control circuit that generates a second digital signal using the comparison signal and controls a second capacitance using the first digital signal to generate the second bias voltage.

The semiconductor integrated circuit further includes a core connected to a third node, and a third power transistor that controls a third virtual operating voltage of the third node in response to the first bias voltage or the second bias voltage, and a channel width of each of the first power transistor and the second power transistor is smaller than a channel width of the third power transistor.

According to embodiments of the present invention, a method of operating a semiconductor integrated circuit includes a step of controlling a first virtual operating voltage of a first node to which a first electronic circuit is connected using a first power transistor that operates according to a first bias voltage, a step of controlling a second virtual operating voltage of a second node to which a second electronic circuit is connected using a second power transistor that operates according to a second bias voltage, a step of comparing the first virtual operating voltage and the second virtual operating voltage using a bias voltage control circuit to generate a comparison signal, and a step of controlling each of the first bias voltage and the second bias voltage so that a first leakage current of the first power transistor and a second leakage current of the second power transistor are each minimized according to the comparison signal.

According to embodiments, the step of controlling each of the first bias voltage and the second bias voltage includes the step of controlling each of the first frequency of the first non-sinusoidal wave and the second frequency of the second non-sinusoidal wave using the comparison signal, and the step of controlling the first bias voltage using the first frequency and controlling the second bias voltage using the second frequency.

According to embodiments, the step of controlling each of the first bias voltage and the second bias voltage includes the step of generating each of the first capacitance and the second capacitance using the comparison signal, and the step of controlling the first bias voltage using the first capacitance and controlling the second bias voltage using the second capacitance.

A semiconductor integrated circuit and method according to an embodiment of the present invention have the effect of minimizing leakage currents of the power transistors by comparing virtual operating voltages supplied to electronic circuits through power transistors and automatically controlling the virtual operating voltages based on the comparison result.

In order to more fully understand the drawings cited in the detailed description of the present invention, a detailed description of each drawing is provided.
FIG. 1A is a block diagram of a semiconductor integrated circuit that minimizes leakage current of each power switch using a direct voltage sensing method according to embodiments of the present invention.
FIG. 1b is a block diagram of a semiconductor integrated circuit that minimizes leakage current of each power switch using a replica voltage detection method according to embodiments of the present invention.
FIG. 2 is a block diagram of a semiconductor integrated circuit using a first algorithm for minimizing leakage current of each power switch using a direct voltage sensing method and frequency control according to embodiments of the present invention.
FIGS. 3A to 3H are conceptual diagrams illustrating a first algorithm performed by the semiconductor integrated circuit illustrated in FIG. 2.
FIG. 4a is an embodiment of a circuit diagram of a first bias voltage control circuit of the semiconductor integrated circuit illustrated in FIG. 2.
FIG. 4b is an embodiment of a circuit diagram of a second bias voltage control circuit of the semiconductor integrated circuit illustrated in FIG. 2.
FIG. 5A is a block diagram of a semiconductor integrated circuit using a first algorithm for minimizing leakage current of each power switch using a direct voltage sensing method and capacitance control according to embodiments of the present invention.
FIG. 5b is a flowchart explaining an operation method of a semiconductor integrated circuit using the first algorithm illustrated in FIG. 5a and FIG. 7.
FIG. 6a is an embodiment of a circuit diagram of a first bias voltage control circuit of the semiconductor integrated circuit illustrated in FIG. 5a.
FIG. 6b is an embodiment of a circuit diagram of a second bias voltage control circuit of the semiconductor integrated circuit illustrated in FIG. 5a.
FIG. 7 is a block diagram of a semiconductor integrated circuit using a first algorithm for minimizing leakage current of each power switch using a replica voltage detection method and frequency control according to embodiments of the present invention.
FIG. 8a is an embodiment of a circuit diagram of a first bias voltage control circuit of the semiconductor integrated circuit illustrated in FIG. 7.
FIG. 8b is an embodiment of a circuit diagram of a second bias voltage control circuit of the semiconductor integrated circuit illustrated in FIG. 7.
FIG. 9A is a block diagram of a semiconductor integrated circuit using a second algorithm for minimizing leakage current of each power switch using a direct voltage sensing method and capacitance control according to embodiments of the present invention.
FIG. 9b is a flowchart illustrating an operation method of a semiconductor integrated circuit using the first algorithm illustrated in FIG. 9a, FIG. 11, FIG. 12, and FIG. 13.
FIGS. 10A to 10H are conceptual diagrams illustrating a second algorithm performed by the semiconductor integrated circuit illustrated in FIG. 9.
FIG. 11 is a block diagram of a semiconductor integrated circuit using a second algorithm for minimizing leakage current of each power switch using a replica voltage detection method and capacitance control according to embodiments of the present invention.
FIG. 12 is a block diagram of a semiconductor integrated circuit using a second algorithm for minimizing leakage current of each power switch using a direct voltage sensing method and frequency control according to embodiments of the present invention.
FIG. 13 is a block diagram of a semiconductor integrated circuit using a second algorithm for minimizing leakage current of each power switch using a replica voltage detection method and frequency control according to embodiments of the present invention.

FIG. 1A is a block diagram of a semiconductor integrated circuit that minimizes leakage current of each power switch using a direct voltage sensing method according to embodiments of the present invention.

Referring to FIG. 1A, a semiconductor integrated circuit (100_1, 100_2, 100_4, and 100_6 collectively referred to as '100') includes a first power transistor (PSW1), a second power transistor (PSW2), a bias voltage control circuit (101), a first electronic circuit (160_1), and a second electronic circuit (160_2). The semiconductor integrated circuit (100) may be a system on chip (Soc) or a semiconductor chip.

The first power transistor (PSW1) is connected between a power line (PL) that supplies an operating voltage (VDD) and a first node (ND1), and controls a first virtual operating voltage (VVDD1) of the first node (ND1) to which the first electronic circuit (160_1) is connected using a first bias voltage (BIAS1).

The second power transistor (PSW2) is connected between the power line (PL) and the second node (ND2), and controls the second virtual operating voltage (VVDD2) of the second node (ND2) to which the second electronic circuit (160_2) is connected using the second bias voltage (BIAS2).

The bias voltage control circuit (101_1 to 101_7 are collectively referred to as '101') compares a first virtual operating voltage (VVDD1) and a second virtual operating voltage (VVDD2) with each other, generates a comparison signal based on the comparison result, and controls or independently controls each of the first bias voltage (BIAS1) and the second bias voltage (BIAS2) to minimize a first leakage current (Ilkg1) flowing in a first power transistor (PSW1) that controls the voltage level of the first virtual operating voltage (VVDD1) and a second leakage current (Ilkg2) flowing in a second power transistor (PSW2) that controls the voltage level of the second virtual operating voltage (VVDD2).

According to embodiments, the bias voltage control circuit (101) controls a first frequency of a first non-sinusoidal waveform related to the control of a first bias voltage (BIAS1), and controls a second frequency of a second non-sinusoidal waveform related to the control of a second bias voltage (BIAS2). In the present specification, control means increasing, maintaining, or decreasing.

According to embodiments, the bias voltage control circuit (101) controls the first capacitance of the first group of switched capacitor circuits of FIG. 6A related to the control of the first bias voltage (BIAS1) based on the level of the comparison signal, and controls the second capacitance of the second group of switched capacitor circuits of FIG. 6B related to the control of the second bias voltage (BIAS2) based on the level of the comparison signal.

Each of the first electronic circuit (160_1) and the second electronic circuit (160_2) may be a core of a central processing unit (CPU), a graphic processing unit (GPU), or a neural processing unit (NPU). The structures of each core (160_1 and 160_2) may be identical.

Each of the power transistors (PSW1 and PS32) can be a complementary metal-oxide-semiconductor (CMOS) transistor or a PMOS transistor.

FIG. 1b is a block diagram of a semiconductor integrated circuit that minimizes leakage current of each power switch using a replica voltage detection method according to embodiments of the present invention.

Referring to FIG. 1b, a semiconductor integrated circuit (100A) includes a first power transistor (PSW1a), a second power transistor (PSW2a), a bias voltage control circuit (101), a first electronic circuit (200a), a second electronic circuit (200b), a third power transistor (LPW), and a third electronic circuit (160_3).

The first power transistor (PSW1a) is connected between the power line (PL) and the first node (ND1), and controls the first virtual operating voltage (VVDD1) of the first node (ND1) to which the first electronic circuit (200a) is connected using the first bias voltage (BIAS1).

The second power transistor (PSW2a) is connected between the power line (PL) and the second node (ND2), and controls the second virtual operating voltage (VVDD2) of the second node (ND2) to which the second electronic circuit (200b) is connected using the second bias voltage (BIAS2).

The bias voltage control circuit (101) compares a first virtual operating voltage (VVDD1) and a second virtual operating voltage (VVDD2) with each other, generates a comparison signal based on the comparison result, and controls (or independently controls) each of the first bias voltage (BIAS1) and the second bias voltage (BIAS2) so that a first leakage current (Ilkg1a) flowing in a first power transistor (PSW1a) that controls the voltage level of the first virtual operating voltage (VVDD1) and a second leakage current (Ilkg2a) flowing in a second power transistor (PSW2a) that controls the voltage level of the second virtual operating voltage (VVDD2) are minimized based on the comparison signal.

The third power transistor (LPW) is connected between the power line (PL) and the third node (ND3), and controls the third virtual operating voltage (VVDD3) of the third node (ND3) to which the third electronic circuit (160_3) is connected using the second bias voltage (BIAS2).

When each power transistor (PSW1a, PSW2a, and LPW) is a PMOS transistor, the channel lengths of each PMOS transistor (PSW1a, PSW2a, and LPW) are the same, and the channel widths of each PMOS transistor (PSW1a and PSW2a) are smaller than the channel width of the PMOS transistor (LPW).

The structure of each electronic circuit (200a and 200b) and the structure of the third electronic circuit (160_3) may be different from each other. Each electronic circuit (200a and 200b) may be a replica load circuit, and the third electronic circuit (160_3) may be a core of a CPU, GPU, or NPU. Here, the operating voltages supplied through each power transistor (PSW1a, PSW2a, and LPW) are referred to as virtual operating voltages (VVDD1, VVDD2, and VVDD3).

The semiconductor integrated circuit (100) of FIG. 1A compares virtual operating voltages (VVDD1 and VVDD2) of cores (160_1 and 160_2) using a bias voltage control circuit (101), and controls each bias voltage (BIAS1 and BIAS2) to minimize each leakage current (Ilkg1 and Ilkg2) using the level of a comparison signal corresponding to the comparison result. The level has a first level (e.g., one of a low level and a high level) and a second level (e.g., the other of a low level and a high level).

However, the semiconductor integrated circuit (100A) of FIG. 1B compares the virtual operating voltages (VVDD1 and VVDD2) of the replica load circuits (160_1 and 160_2) using the bias voltage control circuit (101), and controls each bias voltage (BIAS1 and BIAS2) to minimize each leakage current (Ilkg1a and Ilkg2a) using the level of the comparison signal corresponding to the comparison result, and then the third power transistor (LPW) controls the third virtual operating voltage (VVDD3) supplied to the third electronic circuit (160_3) in response to the optimized second bias voltage (BIAS2).

That is, the semiconductor integrated circuit (100A) of FIG. 1B finds an optimized second bias voltage (BIAS2) using a replica voltage detection method, and the third power transistor (LPW) supplies a third virtual operating voltage (VVDD3) to the third electronic circuit (160_3) in response to the optimized second bias voltage (BIAS2). At this time, when the second bias voltage (BIAS2) is supplied to the third power transistor (LPW), the leakage current flowing in the third power transistor (LPW) has a minimum value.

FIG. 2 is a block diagram of a semiconductor integrated circuit using a first algorithm for minimizing leakage current of each power switch using a direct voltage detection method and frequency control according to embodiments of the present invention, FIG. 4a is an embodiment of a circuit diagram of a first bias voltage control circuit of the semiconductor integrated circuit illustrated in FIG. 2, and FIG. 4b is an embodiment of a circuit diagram of a second bias voltage control circuit of the semiconductor integrated circuit illustrated in FIG. 2.

Referring to FIGS. 1A, 2, 4A, and 4B, a bias voltage control circuit (101_1) of a semiconductor integrated circuit (100_1) using a first algorithm to be described with reference to FIGS. 3A to 3H includes a first bias voltage control circuit (110) and a second bias voltage control circuit (120). Each bias voltage control circuit (110, 10A, 120, 120A, 410, and/or 420) may be a charge pump or a voltage doubler.

The first bias voltage control circuit (110) controls the first frequency (f1) of the first non-sinusoidal wave (VCLK1) according to the comparison signal (Vcomp) output from the comparison circuit (140), and controls the first bias voltage (BIAS1) according to the first frequency (f1).

Referring to FIG. 2 and FIG. 4a, the first bias voltage control circuit (110) includes a first controller (112_1), a first nonlinear oscillator (or 'first non-sinusoidal wave generation circuit', 114_1), a first inverter (116_1), and a first bias voltage generator (118_1).

The first controller (112_1) detects the level (e.g., high level or low level) of the comparison signal (Vcomp) and generates a first control signal (CTL1) according to the detection result.

For example, when the comparison signal (Vcomp) transitions (changes) from a preset level to a low level, the first controller (112_1) generates a first control signal (CTL1) indicating an increase in the first frequency (f1), and the first nonlinear oscillator (114_1) generates a first non-sinusoidal wave (VCLK1) having an increased first frequency (f1) in response to the first control signal (CTL1) indicating an increase in the first frequency (f1).

However, when the comparison signal (Vcomp) maintains a preset level, for example, a high level, the first controller (112_1) generates a first control signal (CTL1) indicating a decrease in the first frequency (f1), and the first nonlinear oscillator (114_1) generates a first non-sinusoidal wave (VCLK1) having a decreased first frequency (f1) in response to the first control signal (CTL1) indicating a decrease in the first frequency (f1).

The first inverter (116_1) receives the first non-sinusoidal waveform (VCLK1) and generates the first inverted non-sinusoidal waveform (VCLK1B).

The first bias voltage generator (118_1) controls the first bias voltage (BIAS1) in response to the first non-sinusoidal wave (VCLK1) received through each of the capacitors (C1_1 and C2_1) of the first group and the output signal (VCLK1B) of the first inverter (116_1).

Referring to FIG. 2 and FIG. 4b, the second bias voltage control circuit (120) controls the second frequency (f2) of the second non-sinusoidal wave (VCLK2) according to the comparison signal (Vcomp), and controls the second bias voltage (BIAS2) according to the second frequency (f2).

The second bias voltage control circuit (120) includes a second controller (112_2), a second nonlinear oscillator (or 'second non-sinusoidal wave generation circuit', 114_2), a second inverter (116_2), and a second bias voltage generator (118_2).

The second controller (112_1) detects the level of the comparison signal (Vcomp) and generates a second control signal (CTL2) based on the detection result.

For example, when the comparison signal (Vcomp) transitions from the preset level to the low level, the second controller (112_2) generates a second control signal (CTL2) indicating an increase in the second frequency (f2), and the second nonlinear oscillator (114_2) generates a second non-sinusoidal wave (VCLK2) having an increased second frequency (f2) in response to the second control signal (CTL2) indicating an increase in the second frequency (f2).

However, when the comparison signal (Vcomp) maintains a preset level, for example, a high level, the second controller (112_1) generates a second control signal (CTL2) indicating a decrease in the second frequency (f2), and the second nonlinear oscillator (114_2) generates a second non-sinusoidal wave (VCLK2) having a decreased second frequency (f2) in response to the second control signal (CTL2) indicating a decrease in the second frequency (f2).

The second inverter (116_1) receives the second non-sinusoidal waveform (VCLK2) and generates the second inverted non-sinusoidal waveform (VCLK2B).

The second bias voltage generator (118_2) controls the second bias voltage (BIAS2) in response to the second non-sinusoidal wave (VCLK2) received through each of the second group of capacitors (C1_2 and C2_2) and the output signal (VCLK2B) of the second inverter (116_2).

According to embodiments, the capacitance of each of the capacitors (C1_1 and C2_1) of the first group is the same, the capacitance of each of the capacitors (C1_2 and C2_2) of the second group is the same, and the capacitance of the capacitor (C1_1) and the capacitance of the capacitor (C1_2) may be the same or different from each other.

Referring again to FIG. 2, the bias voltage control circuit (101_1) includes a selection circuit (130) including a first selection circuit (132) and a second selection circuit (134), a comparison circuit (140), a selection signal generation circuit (150), a first bias voltage control circuit (110), and a second bias voltage control circuit (120).

The first selection circuit (132) outputs one of the first virtual operating voltage (VVDD1) and the second virtual operating voltage (VVDD2) in response to the selection signal (SEL).

The second selection circuit (134) outputs the other one of the first virtual operating voltage (VVDD1) and the second virtual operating voltage (VVDD2) in response to the selection signal (SEL). For example, each selection circuit (132 and 134) can be implemented as a multiplexer.

For example, when the selection signal (SEL) is at a low level, the first selection circuit (132) outputs the first virtual operating voltage (VVDD1) as the first output signal (MX1 = VVDD1), and the second selection circuit (134) outputs the second virtual operating voltage (VVDD2) as the second output signal (MX2 = VVDD2).

However, when the selection signal (SEL) is at a high level, the first selection circuit (132) outputs the second virtual operating voltage (VVDD2) as the first output signal (MX1 = VVDD2), and the second selection circuit (134) outputs the first virtual operating voltage (VVDD1) as the second output signal (MX2 = VVDD1).

The comparison circuit (140) receives a first output signal (MX1) of a first selection circuit (132) through a first input terminal (e.g., an inverting input terminal, 141), receives a second output signal (MX2) of a second selection circuit (134) through a second input terminal (e.g., a non-inverting input terminal, 143), and outputs a comparison signal (Vcomp) corresponding to a comparison result of the first output signal (MX1) and the second output signal (MX2) in response to a first sampling clock signal (SCLK1).

The selection signal generation circuit (150) determines the level of the selection signal (SEL) according to the level of the comparison signal (Vcomp), and outputs the comparison signal (Vcomp) having the determined level to each selection circuit (132 and 134).

As described with reference to FIG. 2 and FIG. 4a, the first bias voltage control circuit (110) controls the first frequency (f1) of the first non-sinusoidal wave (VCLK1) according to the level of the comparison signal (Vcomp), controls the first bias voltage (BIAS1) according to the first frequency (f1), and outputs the first bias voltage (BIAS1) to the gate of the first power transistor (PSW1).

As described with reference to FIG. 2 and FIG. 4b, the second bias voltage control circuit (120) controls the second frequency (f2) of the second non-sinusoidal wave (VCLK2) according to the level of the comparison signal (Vcomp), controls the second bias voltage (BIAS2) according to the second frequency (f2), and outputs the second bias voltage (BIAS2) to the gate of the second power transistor (PSW2).

FIGS. 3A to 3H are conceptual diagrams illustrating a first algorithm performed by the semiconductor integrated circuit illustrated in FIG. 2.

In FIGS. 3a to 3h, each arrow represents a change direction (e.g., an increasing direction or a decreasing direction) of each bias voltage (BIAS1 and BIAS2) and each virtual power supply voltage (VVDD1 and VVDD2), VVDD represents each virtual power supply voltage (VVDD1 and VVDD2) in general, and Ilkg represents each leakage current (Ilkg1, Ilkg2, Ilkg1a, and Ilkg2a) in general.

According to embodiments, the preset level of the comparison circuit (140) may be set to a low level, the first input terminal (141) of the comparison circuit (140) may be a non-inverting input terminal, and the second input terminal (143) of the comparison circuit (140) may be an inverting input terminal.

However, as shown in FIG. 2, FIG. 5a, FIG. 7, FIG. 9a, FIG. 11, FIG. 12, and FIG. 13, it is assumed that the preset level of the comparison circuit (140) is a high level, the first input terminal (141) is an inverting input terminal (-), and the second input terminal (143) is a non-inverting input terminal (+).

Referring to FIGS. 2, 3a, and 3b, it is assumed that the level of the selection signal (SEL) is low (L) at the beginning of operation. When the first virtual operating voltage (VVDD1) is higher than the second virtual operating voltage (VVDD2), the comparison circuit (140) outputs a comparison signal (Vcomp, referred to as a first comparison signal) that transitions from a high level (i.e., a preset level) to a low level (L) in response to the first sampling clock signal (SCLK1), for example, a rising edge. The selection signal generation circuit (150) outputs a selection signal (SEL) having a low level (L) to each selection circuit (132 and 134) in response to the first comparison signal (Vcomp).

Referring to FIGS. 3a, 3b, 4a, and 4b, each bias voltage (BIAS1 and BIAS2) increases, the leakage current (Ilkg) flowing through each power transistor (PSW1, PSW2, PSW1a, and PWS2a) decreases, each virtual power voltage (VVDD1 and VVDD2) decreases, and each frequency (f1 and f2) increases. That is, each frequency (f1 and f2) increases as it goes to the right on the X-axis.

According to a selection signal (SEL) having a low level (L), the first selection circuit (132) outputs a first virtual operating voltage (MX1 = VVDD1) to the first input terminal (141), and the second selection circuit (134) outputs a second virtual operating voltage (MX2 = VVDD2) to the second input terminal (143).

Referring to FIG. 3c, if the second virtual operating voltage (MX2 = VVDD2) input to the second input terminal (143) is greater than the first virtual operating voltage (MX1 = VVDD1) input to the first input terminal (141), the comparison circuit (140) outputs a comparison signal (Vcomp, referred to as a second comparison signal) that maintains the preset level (H) in response to the first sampling clock signal (SCLK).

The selection signal generation circuit (150) outputs a selection signal (SEL) having a high level (H) to each selection circuit (132 and 134) in response to the second comparison signal (Vcomp).

According to a selection signal (SEL) having a high level (H), each selection circuit (132 and 134) performs a swap operation (SWAP) to change each virtual operating voltage (VVDD1 and VVDD2) and transmit it to the comparison circuit (140).

As the swap operation (SWAP) is performed, i.e., when the selection signal (SEL) is at a high level, the first selection circuit (132) outputs the second virtual operating voltage (MX1 = VVDD2) to the first input terminal (141), and the second selection circuit (134) outputs the first virtual operating voltage (MX2 = VVDD1) to the second input terminal (143).

Referring to FIGS. 3c and 3d, when the first virtual operating voltage (MX2 = VVDD1) input to the second input terminal (143) after the swap operation (SWAP) is performed is greater than the second virtual operating voltage (MX1 = VVDD2) input to the first input terminal (141), the comparison circuit (140) outputs the second comparison signal (Vcomp) in response to the first sampling clock signal (SCLK).

Referring to FIGS. 3d and 3e, each bias voltage (BIAS1 and BIAS2) that was increasing before the swap operation (SWAP) was performed decreases after the swap operation (SWAP) is performed.

Referring to FIG. 3e, since the first virtual operating voltage (MX2 = VVDD1) input to the second input terminal (143) is still greater than the second virtual operating voltage (MX1 = VVDD2) input to the first input terminal (141), the comparison circuit (140) outputs a second comparison signal (Vcomp), and the selection signal generation circuit (150) outputs a selection signal (SEL) having a high level (H) to each selection circuit (132 and 134).

Referring to FIG. 3f, when the selection signal (SEL) is at a high level (H), when the second virtual operating voltage (MX1 = VVDD2) input to the first input terminal (141) is higher than the first virtual operating voltage (MX2 = VVDD1) input to the second input terminal (143), the comparison circuit (140) outputs the first comparison signal (Vcomp), and the selection signal generation circuit (150) outputs the selection signal (SEL) having a low level (L) to each selection circuit (132 and 134) according to the first comparison signal (Vcomp).

According to a selection signal (SEL) having a low level (L), the first selection circuit (132) outputs a first virtual operating voltage (MX1 = VVDD1) to the first input terminal (141), and the second selection circuit (134) outputs a second virtual operating voltage (MX2 = VVDD2) to the second input terminal (143).

According to a selection signal (SEL) having a low level (L), each selection circuit (132 and 134) performs a swap operation (SWAP) to change each virtual operating voltage (VVDD1 and VVDD2) and transmit it to the comparison circuit (140).

Referring to FIG. 3g, when the selection signal (SEL) is at a low level (L), when the first virtual operating voltage (MX1 = VVDD1) input to the first input terminal (141) is greater than the first virtual operating voltage (MX2 = VVDD1) input to the second input terminal (143), the comparison circuit (140) outputs the first comparison signal (Vcomp), and the selection signal generation circuit (150) outputs the selection signal (SEL) having a low level (L) to each selection circuit (132 and 134) according to the first comparison signal (Vcomp).

Referring to FIG. 3h, when the selection signal (SEL) is at a low level (L), when the second virtual operating voltage (MX2 = VVDD2) input to the second input terminal (143) is higher than the first virtual operating voltage (MX1 = VVDD1) input to the first input terminal (141), the comparison circuit (140) outputs a second comparison signal (Vcomp), and the selection signal generation circuit (150) outputs a selection signal (SEL) having a high level (H) to each selection circuit (132 and 134) according to the second comparison signal (Vcomp).

According to a selection signal (SEL) having a high level (H), each selection circuit (132 and 134) performs a swap operation (SWAP) to change each virtual operating voltage (VVDD1 and VVDD2) and transmit it to the comparison circuit (140).

The bias voltage control circuit (101_1) of the semiconductor integrated circuit (100_1) using the first algorithm performs FIG. 3d again after FIG. 3h is performed. From then on, the bias voltage control circuit (101_1) repeatedly performs FIG. 3d to FIG. 3h to find each bias voltage (BIAS1 and BIS2) at which the leakage current (Ilkg) is minimized.

FIG. 5a is a block diagram of a semiconductor integrated circuit using a first algorithm for minimizing leakage current of each power switch using a direct voltage detection method and capacitance control according to embodiments of the present invention, and FIG. 5b is a flowchart explaining an operating method of the semiconductor integrated circuit using the first algorithm illustrated in FIG. 5a and FIG. 7.

A semiconductor integrated circuit (100_2) using a first algorithm includes a first power transistor (PSW1), a second power transistor (PSW2), a bias voltage control circuit (101_2), a first electronic circuit (160_1), and a second electronic circuit (160_2).

The bias voltage control circuit (101_2) includes a first bias voltage control circuit (410), a second bias voltage control circuit (420), a comparison circuit (430), a control circuit (435), a first up/down counter (440), a second up/down counter (445), and a swap controller (450). The count values output from each up/down counter described herein are digital signals.

Each up/down counter (440 and 445) performs an up-count operation (also called 'count-up') to increase each count value (CNT1 and CNT2) or a down-count operation (also called 'count-down') to decrease each count value (CNT1 and CNT2) whenever the first comparison signal (Vcomp) is input, and outputs each count value (CNT1 and CNT2). However, when the comparison signal (Vcomp) is the second comparison signal (Vcomp) that maintains the preset level (H), the immediately preceding count values (CNT1 and CNT2) are maintained as is.

For convenience of explanation, it is assumed that each up/down counter (440 and 445) is a 4-bit counter, and that the initial count value (CNT1) of the first up/down counter (440) is set to 4b'0000, and the initial count value (CNT2) of the second up/down counter (445) is set to 4b'0001.

Referring to the graphs of FIG. 3a, FIG. 5a, and FIG. 5b, when the first virtual operating voltage (VVDD1) is greater than the second virtual operating voltage (VVDD2), the comparison circuit (430) outputs a first comparison signal (Vcomp) that transitions from a preset level (H) to a low level (L) in response to the first sampling clock signal (SCLK1).

According to the first comparison signal (Vcomp), the control circuit (435) generates a count control signal (UDC) indicating an up-count and transmits it to each up/down counter (440 and 445), and generates a swap control signal (SCS, referred to as a 'first swap control signal') indicating that a swap operation is not in progress and transmits it to the swap controller (450).

Each up/down counter (440 and 445) performs an up-count operation whenever the first comparison signal (Vcomp) is input in response to a count control signal (UDC) indicating an up-count (S110).

When the first comparison signal (Vcomp) is input, the first up/down counter (440) performs an up-count operation to generate a first count value (CNT1=4b'0001), and the second up/down counter (445) performs an up-count operation to generate a second count value (CNT2=4b'0010) (S110).

The swap controller (450), in response to the first swap control signal (SCS), transmits the first count value (CNT1=4b'0001) of the first up/down counter (440) to the first bias voltage control circuit (410) and transmits the second count value (CNT2=4b'0010) of the second up/down counter (445) to the second bias voltage control circuit (420). That is, the swap controller (450) does not perform a swap operation that swaps the count values (CNT1 and CNT2).

FIG. 6a is an embodiment of a circuit diagram of a first bias voltage control circuit of the semiconductor integrated circuit illustrated in FIG. 5a, and FIG. 6b is an embodiment of a circuit diagram of a second bias voltage control circuit of the semiconductor integrated circuit illustrated in FIG. 5a.

The differential clock signals (CLK3 and CLK3B) illustrated in FIG. 6a are input from the outside of the bias voltage control circuit (101_2) of FIG. 5a, and the differential clock signals (CLK4 and CLK4B) illustrated in FIG. 6b are input from the outside of the bias voltage control circuit (101_2) of FIG. 5a.

Referring to FIGS. 5A and 6A, since the first count value (CNT1) increases from 4b'0000 to 4b'0001, among the switches (SW1 to SW8) included in the first group of switched capacitor circuits included in the first bias voltage control circuit (410), the switches (SW4 and SW8) corresponding to 4b'0001 are turned on, so that the first capacitance of the first bias voltage control circuit (410) increases, and thus the first bias voltage (BIAS1) also increases. The capacitors (1C, 2C, 4C, and 8C) included in the first group of switched capacitor circuits have weights.

Referring to FIGS. 5a and 6b, since the second count value (CNT2) increases from 4b'0001 to 4b'0010, among the switches (SW1a to SW8a) included in the second group of switched capacitor circuits included in the second bias voltage control circuit (420), the switches (SW3a and SW7a) corresponding to 4b'0010 are turned on, so that the second capacitance of the second bias voltage control circuit (420) increases, and thus the second bias voltage (BIAS2) also increases. The capacitors (1C, 2C, 4C, and 8C) included in the second group of switched capacitor circuits have weights.

Referring to the graph of FIG. 3b, FIG. 5a, and FIG. 5b, when the first virtual operating voltage (VVDD1) is greater than the second virtual operating voltage (VVDD2), the comparison circuit (430) outputs a first comparison signal (Vcomp) that transitions from a preset level (H) to a low level (L) in response to the first sampling clock signal (SCLK1).

The control circuit (435) maintains a first swap control signal (SCS) and a count control signal (UDC) indicating an up-count in response to a first comparison signal (Vcomp).

Each up/down counter (440 and 445) continues to perform an up-count operation in response to a count control signal (SCS) indicating an up-count (S110).

In response to the first comparison signal (Vcomp) (NO of S120), the first up/down counter (440) performs an up-count operation to generate a first count value (CNT1=4b'0010), and the second up/down counter (445) performs an up-count operation to generate a second count value (CNT2=4b'0011).

In response to the first swap control signal (SCS), the swap controller (450) transmits the first count value (CNT1=4b'0010) of the first up/down counter (440) to the first bias voltage control circuit (410) and transmits the second count value (CNT2=4b'0011) of the second up/down counter (445) to the second bias voltage control circuit (420).

Referring to FIGS. 5A and 6A, since the first count value (CNT1) increases from 4b'0001 to 4b'0010, among the switches (SW1 to SW8) included in the first group of switched capacitor circuits included in the first bias voltage control circuit (410), the switches (SW3 and SW7) corresponding to 4b'0010 are turned on, so that the first capacitance of the first bias voltage control circuit (410) further increases, and thus the first bias voltage (BIAS1) also further increases.

Referring to FIGS. 5a and 6b, since the second count value (CNT2) increases from 4b'0010 to 4b'0011, among the switches (SW1a to SW8a) included in the second group of switched capacitor circuits included in the second bias voltage control circuit (420), the switches (SW3a, SW4a, SW7a, and SW8a) corresponding to 4b'0011 are turned on, so that the second capacitance of the second bias voltage control circuit (420) further increases, and thus the second bias voltage (BIAS2) also further increases.

Referring to the graph of FIG. 3c and FIG. 5a, when the second virtual operating voltage (VVDD2) becomes greater than the first virtual operating voltage (VVDD1), the comparison circuit (430) outputs a second comparison signal (Vcomp) that maintains the preset level (H) in response to the first sampling clock signal (SCLK1) (S120).

According to the second comparison signal (Vcomp) (YES of S120), the control circuit (435) generates a count control signal (UDC) indicating a down-count and transmits it to each up/down counter (440 and 445), and generates a swap control signal (SCS, referred to as a 'second swap control signal') indicating a swap operation and transmits it to the swap controller (450) (S130).

Each up/down counter (440 and 445) responds to a count control signal (UDC) indicating a down-count, maintains its previous count value (CNT1=0010, and CNT2=0011), and then prepares for a down-count operation.

In response to the second swap control signal (SCS), the swap controller (450) transmits the first count value (CNT1=4b'0010) of the first up/down counter (440) to the second bias voltage control circuit (420) and transmits the second count value (CNT2=4b'0011) of the second up/down counter (445) to the first bias voltage control circuit (410). That is, each count value (CNT1=0010, and CNT2=0011) transmitted to each bias voltage control circuit (410 and 420) is swapped.

Referring to FIGS. 5A and 6A, after the swap operation, the count value input to the first bias voltage control circuit (410) increases from 4b'0010 to 4b'0011, but the count value input to the second bias voltage control circuit (420) decreases from 4b'0011 to 4b'0010.

Referring to FIGS. 5A and 6A, since the count value input to the first bias voltage control circuit (410) increases from 4b'0010 to 4b'0011, among the switches (SW1 to SW8) included in the first group of switched capacitor circuits included in the first bias voltage control circuit (410), the switches (SW3, SW4, SW7, and SW8) corresponding to 4b'0011 are turned on, so that the first capacitance of the first bias voltage control circuit (410) further increases, and thus the first bias voltage (BIAS1) also further increases.

However, referring to FIGS. 5a and 6a, since the count value input to the second bias voltage control circuit (420) has decreased from 4b'0011 to 4b'0010, among the switches (SW1a to SW8a) included in the second group of switched capacitor circuits included in the second bias voltage control circuit (420), the switches (SW3a and SW7a) corresponding to 4b'0010 are turned on, so that the second capacitance of the second bias voltage control circuit (420) decreases, and thus the second bias voltage (BIAS2) decreases.

Referring to the graph of FIG. 3e and FIG. 5a, when the first virtual operating voltage (VVDD1) becomes greater than the first virtual operating voltage (VVDD1), the comparison circuit (430) outputs the first comparison signal (Vcomp) in response to the first sampling clock signal (SCLK1).

In response to the first comparison signal (Vcomp), the first up/down counter (440) performs a down-count operation to generate a first count value (CNT1=4b'0001), the second up/down counter (445) performs a down-count operation to generate a second count value (CNT2=4b'0010), and the swap controller (450) transmits the second count value (CNT2=4b'0010) of the second up/down counter (445) to the first bias voltage control circuit (410) and transmits the first count value (CNT1=4b'0001) of the first up/down counter (440) to the second bias voltage control circuit (420) (S140).

As each virtual operating voltage (VVDD1 and VVDD2) is controlled, when the second virtual operating voltage (VVDD2) becomes greater than the first virtual operating voltage (VVDD1) again, the comparison circuit (430) outputs the second comparison signal (Vcomp) (YES of S150).

According to the second comparison signal (Vcomp) (YES of S150), the control circuit (435) generates a count control signal (UDC) indicating an up-count and transmits it to each up/down counter (440 and 445), and generates a second swap control signal (SCS) and transmits it to the swap controller (450). At this time, each up/down counter (440 and 445) maintains its previous count value in response to the count control signal (SCS) indicating an up-count and prepares for an up-count operation.

A swap controller (450) that performs a swap operation in response to a second swap control signal (SCS) transmits a first count value (CNT1) of a first up/down counter (440) to a first bias voltage control circuit (410) and transmits a second count value (CNT2) of a second up/down counter (445) to a second bias voltage control circuit (420) (S160).

As described with reference to FIGS. 5a and 5b, when the second comparison signal (Vcomp) is first output from the comparison circuit (430) while each up/down counter (440 and 445) is performing an up-count operation (YES of S110 and S120), the control circuit (435) generates a count control signal (SCS) indicating a down-count in response to the second comparison signal (Vcomp) and generates a second swap control signal (SCS) in response to the second comparison signal (Vcomp).

Each up/down counter (440 and 445) stops the up-count operation and prepares for the down-count operation in response to a count control signal (SCS) indicating a down-count. Thereafter, each up/down counter (440 and 445) performs the down-count operation whenever the first comparison signal (Vcomp) is input.

A swap controller (450) that performs a swap operation in response to a second swap control signal (SCS) transmits a first count value (CNT1) of a first up/down counter (440) that performs a down-count operation to a second bias voltage control circuit (420) and transmits a second count value (CNT2) of a second up/down counter (445) that performs a down-count operation to a first bias voltage control circuit (410) (S130).

Afterwards, when the second comparison signal (Vcomp) is output from the comparison circuit (430) for the second time while each up/down counter (440 and 445) is performing a down-count operation (YES of S140 and S150), the control circuit (435) generates a count control signal (SCS) indicating an up-count in response to the second comparison signal (Vcomp) and generates a second swap control signal (SCS) in response to the second comparison signal (Vcomp).

Each up/down counter (440 and 445) stops the down-count operation in response to a count control signal (SCS) indicating an up-count and prepares for an up-count operation. Thereafter, each up/down counter (440 and 445) performs an up-count operation whenever the first comparison signal (Vcomp) is input (S110).

A swap controller (450) that performs a swap operation in response to a second swap control signal (SCS) transmits a first count value (CNT1) of a first up/down counter (440) that performs an up-count operation to a first bias voltage control circuit (410) and transmits a second count value (CNT2) of a second up/down counter (445) that performs an up-count operation to a second bias voltage control circuit (420) (S110).

When the second comparison signal (Vcomp) is output for the third time from the comparison circuit (430) while each up/down counter (440 and 445) is performing an up-count operation (YES of S110 and S120), the control circuit (435) generates a count control signal (SCS) indicating a down-count in response to the second comparison signal (Vcomp) and generates a second swap control signal (SCS) in response to the second comparison signal (Vcomp).

Each up/down counter (440 and 445) stops the up-count operation and prepares for the down-count operation in response to a count control signal (SCS) indicating a down-count. Thereafter, each up/down counter (440 and 445) performs the down-count operation whenever the first comparison signal (Vcomp) is input.

A swap controller (450) that performs a swap operation in response to a second swap control signal (SCS) transmits a first count value (CNT1) of a first up/down counter (440) that performs a down-count operation to a second bias voltage control circuit (420) and transmits a second count value (CNT2) of a second up/down counter (445) that performs a down-count operation to a first bias voltage control circuit (410) (S140).

FIG. 7 is a block diagram of a semiconductor integrated circuit using a first algorithm for minimizing leakage current of each power switch using a replica voltage detection method and frequency control according to embodiments of the present invention, FIG. 8a is an embodiment of a circuit diagram of a first bias voltage control circuit of the semiconductor integrated circuit illustrated in FIG. 7, and FIG. 8b is an embodiment of a circuit diagram of a second bias voltage control circuit of the semiconductor integrated circuit illustrated in FIG. 7.

Referring to FIGS. 7, 8a, and 8b, the semiconductor integrated circuit (100_3) includes a first power transistor (PSW1a), a second power transistor (PSW2a), a bias voltage control circuit (101_3), a first electronic circuit (200a), a second electronic circuit (200b), a third power transistor (LPW), and a third electronic circuit (160_3).

The bias voltage control circuit (101_3) includes a first bias voltage control circuit (110A), a second bias voltage control circuit (120A), a comparison circuit (430), a control circuit (435), a first up/down counter (440), a second up/down counter (445), a swap controller (450), a first controller (245), a first nonlinear oscillator (250), a second controller (255), and a second nonlinear oscillator (260).

The operation of each configuration (430, 435, 440, 445, and 450) illustrated in FIG. 7 is the same as the operation of each configuration (430, 435, 440, 445, and 450) illustrated in FIG. 5a, so a description thereof is omitted.

The first controller (245) compares the immediately preceding first count value stored therein with the count value output from the swap controller (450) (CNT1 when the first swap control signal (SCS) is present or CNT2 when the second swap control signal (SCS) is present), and when the first immediately preceding count value is smaller than the count value (CNT1 or CNT2) output from the swap controller (450), generates a third control signal (CTL3) indicating a decrease in the third frequency (f3) and outputs the third control signal (CTL3) to the first nonlinear oscillator (250).

In response to a third control signal (CTL3) indicating a decrease in the third frequency (f3), the first nonlinear oscillator (250) decreases the third frequency (f3) and generates first differential non-sinusoidal waves (CLK1 and CLK1B) having the third frequency (f3).

However, the first controller (245) compares the immediately preceding first count value stored therein with the count value (CNT1 or CNT2) output from the swap controller (450), and when the immediately preceding first count value is greater than the count value (CNT1 or CNT2) output from the swap controller (450), generates a third control signal (CTL3) indicating an increase in the third frequency (f3) and outputs it to the first nonlinear oscillator (250).

In response to a third control signal (CTL3) indicating an increase in the third frequency (f3), the first nonlinear oscillator (250) increases the third frequency (f3) and generates first differential non-sinusoidal waves (CLK1 and CLK1B) having the third frequency (f3).

The second controller (255) compares the immediately preceding second count value stored therein with the count value output from the swap controller (450) (CNT2 when the first swap control signal (SCS) is present or CNT1 when the second swap control signal (SCS) is present), and when the immediately preceding second count value is smaller than the count value (CNT2 or CNT1) output from the swap controller (450), generates a fourth control signal (CTL4) indicating a decrease in the fourth frequency (f4) and outputs the fourth control signal (CTL4) to the second nonlinear oscillator (260).

In accordance with the fourth control signal (CTL4) indicating a decrease in the fourth frequency (f4), the second nonlinear oscillator (260) decreases the fourth frequency (f4) and generates second differential non-sinusoidal waves (CLK2 and CLK2B) having the fourth frequency (f4).

However, the second controller (255) compares the immediately preceding second count value stored therein with the count value (CNT2 or CNT1) output from the swap controller (450), and when the immediately preceding second count value is greater than the count value (CNT2 or CNT1) output from the swap controller (450), generates a fourth control signal (CTL4) indicating an increase in the fourth frequency (f4) and outputs it to the second nonlinear oscillator (260).

In response to the fourth control signal (CTL4) indicating an increase in the fourth frequency (f4), the second nonlinear oscillator (260) increases the fourth frequency (f4) and generates second differential non-sinusoidal waves (CLK2 and CLK2B) having the fourth frequency (f4).

Referring to FIGS. 7 and 8A, the first bias voltage control circuit (110A) decreases the first bias voltage (BIAS1) in accordance with the third control signal (CTL3) instructing a decrease in the third frequency (f3), and increases the first bias voltage (BIAS1) in accordance with the third control signal (CTL3) instructing an increase in the third frequency (f3).

Referring to FIGS. 7 and 8b, the second bias voltage control circuit (120A) decreases the second bias voltage (BIAS2) in accordance with the fourth control signal (CTL4) instructing a decrease in the fourth frequency (f4), and increases the second bias voltage (BIAS2) in accordance with the fourth control signal (CTL4) instructing an increase in the fourth frequency (f4).

FIG. 9a is a block diagram of a semiconductor integrated circuit using a second algorithm for minimizing leakage current of each power switch using a direct voltage detection method and capacitance control according to embodiments of the present invention, FIG. 9b is a flowchart explaining an operating method of a semiconductor integrated circuit using the first algorithm illustrated in FIGS. 9a, 11, 12, and 13, and FIGS. 10a to 10h are conceptual diagrams explaining a second algorithm performed by the semiconductor integrated circuit illustrated in FIG. 9.

The semiconductor integrated circuit (100_4) includes a first power transistor (PSW1), a second power transistor (PSW2), a bias voltage control circuit (101_4), a first electronic circuit (160_1), and a second electronic circuit (160_2).

The first sampling clock signal generation circuit (203) generates a first sampling clock signal (SCLK1), and the second sampling clock signal generation circuit (205) generates a second sampling clock signal (SCLK2) by dividing the frequency of the first sampling clock signal (SCLK1) by N. Here, N is a natural number greater than or equal to 2, and the second sampling clock signal generation circuit (205) may be a D flip-flop. The waveforms of each sampling clock signal (SCLK1 and SCLK2) are exemplarily illustrated in Fig. 9a.

Referring to FIGS. 9a, 9b, and 10a, it is assumed that initially the up/down counter (515) performs an up-count operation, and each memory device (525 and 530) stores an initial value (MM1=4b'0000 and MM2=4b'0000).

Each bias voltage (BIAS1 and BIAS2) generated according to each initial value (MM1=4b'0000 and MM2=4b'0000) stored in each memory device (525 and 530) is the same.

When the up/down counter (515) is enabled in response to an enable signal (EN), the up/down counter (515) performs an up-count operation to generate a count value (CNT=4b'0001) and outputs it to the first memory device (525), so that the count value of the first memory device (525) increases from 4b'0000 to 4b'0001 (S210).

As the first capacitance of the first bias voltage control circuit (410) increases according to the count value (CNT=4b'0001) output from the first memory device (525, or first register), the first bias voltage (BIAS1) increases as shown in FIG. 10b.

As illustrated in FIG. 10b, when the second virtual power supply voltage (VDD2) is greater than the first virtual power supply voltage (VDD1) in an even-numbered period (or cycle) of the first sampling clock signal (SCLK1), the comparison circuit (430) outputs a second comparison signal (Vcomp).

Since the comparison circuit (430) outputs the second comparison signal (Vcomp) in the even-numbered cycle of the first sampling clock signal (SCLK1) (NO of S220), the swap controller (520) performs a swap operation of reading the count value (MM1=4b'0001) stored in the first memory device (525) and storing it in the second memory device (530, or second register), and reading the count value (MM2=4b'0000) stored in the second memory device (530) and storing it in the first memory device (525).

As the swap operation is performed, the second bias voltage (BIAS2) of FIG. 10b changes to the first bias voltage (BIAS1) of FIG. 10c, and the first bias voltage (BIAS1) of FIG. 10b changes to the second bias voltage (BIAS2) of FIG. 10c.

If the first virtual power supply voltage (VDD1) is greater than the second virtual power supply voltage (VDD2) in the odd-numbered cycle of the first sampling clock signal (SCLK1) of FIG. 10c, the comparison circuit (430) outputs the first comparison signal (Vcomp). Accordingly, the up/down counter (515) performing the up-count operation generates a count value (CNT=4b'0010) and outputs it to the first memory device (525) (S210). Accordingly, the count value (MM1) of the first memory device (525) is updated from 4b'0000 to 4b'0010.

The first bias voltage control circuit (410) generates a first bias voltage (BIAS1) corresponding to a count value (MM1=4b'0010, or a first digital signal) stored in the first memory device (525), and the second bias voltage control circuit (420) generates a second bias voltage (BIAS2) corresponding to a count value (MM1=4b'0001, or a second digital signal) stored in the second memory device (525).

When the second virtual power supply voltage (VDD2) is greater than the first virtual power supply voltage (VDD1) in the even-numbered cycle of the first sampling clock signal (SCLK1) of FIG. 10d, as the comparison circuit (430) generates the second comparison signal (Vcomp) (NO of S250), the swap controller (520) performs a swap operation of reading the count value (MM1) stored in the first memory device (525) and storing it in the second memory device (530), and reading the count value (MM2) stored in the second memory device (530) and storing it in the first memory device (525).

If the first virtual power supply voltage (VVDD1) is greater than the second virtual power supply voltage (VVDD2) in the even-numbered cycle of the first sampling clock signal (SCLK1) of FIG. 10e, the comparison circuit (430) outputs the first comparison signal (Vcomp) (YES of S250).

When the first comparison signal (Vcomp) is detected in an even numbered cycle of the first sampling clock signal (SCLK1) (YES of S220), the control circuit (510) generates a count control signal (UDC) indicating a down-count and transmits it to the up/down counter (515). The up/down counter (515) maintains the previous count value according to the count control signal (UDC) indicating a down-count.

As illustrated in FIG. 10f, when the first virtual power supply voltage (VVDD1) is greater than the second virtual power supply voltage (VVDD2) in the odd-numbered cycle of the first sampling clock signal (SCLK1), the comparison circuit (430) outputs the first comparison signal (Vcomp), and the up-down counter (515) performs a down-count operation from the previous count value in response to the first comparison signal (Vcomp) (S240).

As illustrated in FIG. 10g, when the first virtual power supply voltage (VVDD1) is greater than the second virtual power supply voltage (VVDD2) in an even-numbered cycle of the first sampling clock signal (SCLK1), the comparison circuit (430) outputs the first comparison signal (Vcomp).

When the first comparison signal (Vcomp) is detected in an even numbered cycle of the first sampling clock signal (SCLK1) (YES of S250), the control circuit (510) generates a count control signal (UDC) indicating an up-count and transmits it to the up/down counter (515). The up/down counter (515) maintains the previous count value according to the count control signal (UDC) indicating an up-count.

As illustrated in FIG. 10h, when the first virtual power supply voltage (VVDD1) is greater than the second virtual power supply voltage (VVDD2) in an odd-numbered cycle of the first sampling clock signal (SCLK1), the comparison circuit (430) outputs the first comparison signal (Vcomp), and the up-down counter (515) performs an up-count operation from the previous count value in response to the first comparison signal (Vcomp).

As described with reference to FIGS. 9a to 10h, the up/down counter (510) performing the up-count operation performs the up-count operation in response to the first comparison signal (Vcomp) in odd-numbered cycles of the first sampling clock signal (SCLK1) (S210).

When the second comparison signal (Vcomp) is output in an even-numbered cycle of the first sampling clock signal (SCLK1) (NO of S220), the swap controller (520) performs a swap operation (S230). However, when the first comparison signal (Vcomp) is output in an even-numbered cycle of the first sampling clock signal (SCLK1) (YES of S220), the control circuit (510) generates a count control signal (UDC) that instructs a down-count operation and outputs it to the up/down counter (515).

When the first comparison signal (Vcomp) is output in the odd-numbered cycle of the first sampling clock signal (SCLK1), the up/down counter (515) performs a down-count operation in response to the first comparison signal (Vcomp) (S240).

When the second comparison signal (Vcomp) is output in an even-numbered cycle of the first sampling clock signal (SCLK1) (NO of S250), the swap controller (520) performs a swap operation (S230). However, when the first comparison signal (Vcomp) is output in an even-numbered cycle of the first sampling clock signal (SCLK1) (YES of S250), the control circuit (510) generates a count control signal (UDC) that instructs an up-count operation and outputs it to the up/down counter (515).

When the first comparison signal (Vcomp) is output in the odd-numbered cycle of the first sampling clock signal (SCLK1), the up/down counter (515) performs an up-count operation in response to the first comparison signal (Vcomp) (S210).

FIG. 11 is a block diagram of a semiconductor integrated circuit using a second algorithm for minimizing leakage current of each power switch using a replica voltage detection method and capacitance control according to embodiments of the present invention.

Referring to FIGS. 9a to 11, a semiconductor integrated circuit (100_5) includes a first power transistor (PSW1a), a second power transistor (PSW2a), a bias voltage control circuit (101_5), a first electronic circuit (200a), a second electronic circuit (200b), a third power transistor (LPW), and a third electronic circuit (160_3). The structure and operation of the bias voltage control circuit (101_4) illustrated in FIG. 9a are identical to the structure and operation of the bias voltage control circuit (101_5) illustrated in FIG. 11.

FIG. 12 is a block diagram of a semiconductor integrated circuit using a second algorithm for minimizing leakage current of each power switch using a direct voltage sensing method and frequency control according to embodiments of the present invention.

The semiconductor integrated circuit (100_6) includes a first power transistor (PSW1), a second power transistor (PSW2), a bias voltage control circuit (101_6), a first electronic circuit (160_1), and a second electronic circuit (160_2).

The bias voltage control circuit (101_6) includes a first bias voltage control circuit (110A), a second bias voltage control circuit (120A), a comparison circuit (430), a control circuit (510), an up/down counter (515), a swap controller (520), a first memory device (525), a second memory device (530), a first controller (335), a first nonlinear oscillator (340), a second controller (345), and a second nonlinear oscillator (350).

The operation of each configuration (430, 510, 515, 520, 525, and 530) illustrated in FIG. 12 is the same as the operation of each configuration (430, 510, 515, 520, 525, and 530) illustrated in FIG. 9, so a description thereof is omitted.

The first controller (335) compares the previous count value stored therein with the count value (MM1 or MM2) output from the first memory device (525), and when the previous count value is smaller than the count value (MM1 or MM2) output from the first memory device (525), generates a fifth control signal (CTL5) indicating a decrease in the third frequency (f3) and outputs it to the first nonlinear oscillator (340).

In response to the fifth control signal (CTL5) indicating a decrease in the third frequency (f3), the first nonlinear oscillator (340) decreases the third frequency (f3) and generates first differential non-sinusoidal waves (CLK1 and CLK1B) having the third frequency (f3).

However, the first controller (340) compares the previous count value stored therein with the count value (MM1 or MM2) output from the first memory device (525), and when the previous count value is greater than the count value (MM1 or MM2) output from the first memory device (525), generates a fifth control signal (CTL5) indicating an increase in the third frequency (f3) and outputs it to the first nonlinear oscillator (340).

In response to the fifth control signal (CTL5) indicating an increase in the third frequency (f3), the first nonlinear oscillator (250) increases the third frequency (f3) and generates first differential non-sinusoidal waves (CLK1 and CLK1B) having the third frequency (f3).

The second controller (345) compares the previous count value stored therein with the count value (MM2 or MM1) output from the second memory device (530), and when the previous count value is smaller than the count value (MM2 or MM1) output from the second memory device (530), generates a sixth control signal (CTL6) indicating a decrease in the fourth frequency (f4) and outputs it to the second nonlinear oscillator (350).

In accordance with the sixth control signal (CTL6) indicating a decrease in the fourth frequency (f4), the second nonlinear oscillator (350) decreases the fourth frequency (f4) and generates second differential non-sinusoidal waves (CLK2 and CLK2B) having the fourth frequency (f4).

However, the second controller (345) compares the previous count value stored therein with the count value (MM2 or MM1) output from the second memory device (530), and when the previous count value is greater than the count value (MM2 or MM1) output from the second memory device (530), generates a sixth control signal (CTL6) indicating an increase in the fourth frequency (f4) and outputs it to the second nonlinear oscillator (350).

In response to the sixth control signal (CTL6) indicating an increase in the fourth frequency (f4), the second nonlinear oscillator (350) increases the fourth frequency (f4) and generates second differential non-sinusoidal waves (CLK2 and CLK2B) having the fourth frequency (f4).

FIG. 13 is a block diagram of a semiconductor integrated circuit using a second algorithm for minimizing leakage current of each power switch using a replica voltage detection method and frequency control according to embodiments of the present invention.

The semiconductor integrated circuit (100_7) includes a first power transistor (PSW1a), a second power transistor (PSW2a), a bias voltage control circuit (101_7), a first electronic circuit (200a), a second electronic circuit (200b), a third power transistor (LPW), and a third electronic circuit (160_3). The structure and operation of the bias voltage control circuit (101_7) illustrated in FIG. 12 are identical to the structure and operation of the bias voltage control circuit (101_6) illustrated in FIG. 12.

While the present invention has been described with reference to the embodiments illustrated in the drawings, these are merely exemplary, and those skilled in the art will understand that various modifications and equivalent embodiments are possible. Therefore, the true scope of technical protection of the present invention should be determined by the technical spirit of the appended claims.

100, 100A, and 100_1~100_7: Semiconductor Integrated Circuits
101, and 101_1~101_7: Bias voltage control circuit
PSW1 and PSW1a: first power transistors
PSW2 and PSW2a: second power transistors
LPW: Third power transistor
110, 110A, and 410: First bias voltage control circuit
120, 120A, and 420: First bias voltage control circuit
130: Selection circuit
140 and 430: Comparison circuit
150: Selection signal generation circuit
160_1: First core, first electronic circuit
160_2; Second core, second electronic circuit
160_3: Third core
200a: 1st replica load circuit
200b: 21st Replica Load Circuit
435: Control circuit
440: First Up/Down Counter
445: Second Up/Down Counter
450: Swap Controller

Claims (14)

A first electronic circuit connected to the first node;
A second electronic circuit connected to a second node;
A first power transistor that controls a first virtual operating voltage of the first node in response to a first bias voltage;
A second power transistor that controls a second virtual operating voltage of the second node in response to a second bias voltage; and
A semiconductor integrated circuit comprising a bias voltage control circuit that compares the first virtual operating voltage and the second virtual operating voltage to generate a comparison signal and controls the first bias voltage and the second bias voltage, respectively, to minimize the first leakage current of the first power transistor and the second leakage current of the second power transistor, respectively, according to the comparison signal. In the first paragraph,
A semiconductor integrated circuit in which each of the first electronic circuit and the second electronic circuit is a core of a central processing unit (CPU), a graphic processing unit (GPU), or a neural processing unit (NPU). In the first paragraph, the bias voltage control circuit,
A first bias voltage control circuit that controls a first frequency of a first non-sinusoidal waveform according to the comparison signal and controls the first bias voltage according to the first frequency; and
A semiconductor integrated circuit including a second bias voltage control circuit that controls a second frequency of a second non-sinusoidal waveform according to the comparison signal and controls the second bias voltage according to the second frequency. In the first paragraph, the bias voltage control circuit,
A first selection circuit that outputs one of the first virtual operating voltage and the second virtual operating voltage in response to a selection signal;
A second selection circuit that outputs the other one of the first virtual operating voltage and the second virtual operating voltage in response to the selection signal;
A comparison circuit that compares the first output signal of the first selection circuit and the second output signal of the second selection circuit to generate the comparison signal;
A selection signal generation circuit that generates the selection signal according to the comparison signal;
A first bias voltage control circuit that generates a first non-sinusoidal waveform and controls the first frequency of the first non-sinusoidal waveform according to the comparison signal to control the first bias voltage; and
A semiconductor integrated circuit comprising a second bias voltage control circuit that generates a second non-sinusoidal waveform and controls a second frequency of the second non-sinusoidal waveform according to the comparison signal to control the second bias voltage. In the first paragraph, the semiconductor integrated circuit,
Core connected to the third node; and
Further comprising a third power transistor that controls a third virtual operating voltage of the third node in response to the first bias voltage or the second bias voltage,
A semiconductor integrated circuit in which the channel width of each of the first power transistor and the second power transistor is smaller than the channel width of the third power transistor. In the fifth paragraph, the bias voltage control circuit,
A first bias voltage control circuit that generates a first non-sinusoidal waveform and controls the first frequency of the first non-sinusoidal waveform according to the comparison signal to control the first bias voltage; and
A semiconductor integrated circuit comprising a second bias voltage control circuit that generates a second non-sinusoidal waveform and controls a second frequency of the second non-sinusoidal waveform according to the comparison signal to control the second bias voltage. In the first paragraph, the bias voltage control circuit,
A comparison circuit that compares the first virtual operating voltage and the second virtual operating voltage to generate the comparison signal;
A control circuit that detects the level of the above comparison signal and generates a count control signal;
A first up/down counter that generates a first count value by performing an up-count operation or a down-count operation in response to the above count control signal;
A second up/down counter that generates a second count value by performing an up-count operation or a down-count operation in response to the above count control signal;
A first bias voltage control circuit that controls the first bias voltage in response to one of the first count value and the second count value; and
A semiconductor integrated circuit comprising a second bias voltage control circuit that controls the second bias voltage in response to the other one of the first count value and the second count value. In the first paragraph, the semiconductor integrated circuit,
Core connected to the third node; and
Further comprising a third power transistor that controls a third virtual operating voltage of the third node in response to the first bias voltage or the second bias voltage,
The above bias voltage control circuit,
A comparison circuit that compares the first virtual operating voltage and the second virtual operating voltage to generate the comparison signal;
A control circuit that detects the level of the above comparison signal and generates a count control signal and a swap control signal;
A first up/down counter that generates a first count value by performing an up-count operation or a down-count operation in response to the above count control signal; and
A semiconductor integrated circuit comprising a second up/down counter that generates a second count value by performing an up-count operation or a down-count operation in response to the above count control signal. In the first paragraph, the bias voltage control circuit,
A first bias voltage control circuit that generates a first digital signal using the comparison signal and controls a first capacitance using the first digital signal to generate the first bias voltage; and
A semiconductor integrated circuit comprising a second bias voltage control circuit that generates a second digital signal using the comparison signal and controls a second capacitance using the first digital signal to generate the second bias voltage. In the 9th paragraph, the semiconductor integrated circuit,
Core connected to the third node; and
Further comprising a third power transistor that controls a third virtual operating voltage of the third node in response to the first bias voltage or the second bias voltage,
A semiconductor integrated circuit in which the channel width of each of the first power transistor and the second power transistor is smaller than the channel width of the third power transistor. In the first paragraph, the bias voltage control circuit,
A comparison circuit that compares the first virtual operating voltage and the second virtual operating voltage in response to a first sampling clock signal to generate the comparison signal;
A control circuit that detects whether the comparison signal transitions from a preset level to another level in an even-numbered cycle of the first sampling clock signal and generates a count control signal;
An up/down counter that changes the count operation direction in response to the count control signal generated when the comparison signal transitions from the preset level to another level, and maintains the existing count operation direction in response to the count control signal generated when the comparison signal does not transition from the preset level to the other level;
The above bias voltage control circuit,
A first memory device connected to the above up/down counter;
a second memory device; and
A swap controller that swaps a first count value already stored in the first memory device and a second count value stored in the second memory device when the comparison signal does not transition from the preset level to the other level in the even-numbered cycle;
A first bias voltage control circuit that controls a first capacitance using the second count value output from the first memory device to generate the first bias voltage; and
A semiconductor integrated circuit including a second bias voltage control circuit that controls a second capacitance using the first count value output from the second memory device to generate the second bias voltage. In the method of operating a semiconductor integrated circuit,
A step of controlling a first virtual operating voltage of a first node to which a first electronic circuit is connected using a first power transistor that operates according to a first bias voltage;
A step of controlling a second virtual operating voltage of a second node to which a second electronic circuit is connected using a second power transistor that operates according to a second bias voltage; and
A method for operating a semiconductor integrated circuit, comprising the steps of comparing the first virtual operating voltage and the second virtual operating voltage using a bias voltage control circuit to generate a comparison signal, and controlling each of the first bias voltage and the second bias voltage so that the first leakage current of the first power transistor and the second leakage current of the second power transistor are minimized according to the comparison signal. In the 12th paragraph, the step of controlling each of the first bias voltage and the second bias voltage is,
A step of controlling the first frequency of the first non-sinusoidal wave and the second frequency of the second non-sinusoidal wave using the above comparison signal; and
A method of operating a semiconductor integrated circuit, comprising the steps of controlling the first bias voltage using the first frequency and controlling the second bias voltage using the second frequency. In the 12th paragraph, the step of controlling each of the first bias voltage and the second bias voltage is,
A step of generating a first capacitance and a second capacitance using the above comparison signal; and
A method of operating a semiconductor integrated circuit, comprising the step of controlling the first bias voltage using the first capacitance and controlling the second bias voltage using the second capacitance.