KR102762483B1 - 3d stacked semiconductor devices including hybrid bonding and manufacturing methods thereof - Google Patents

Abstract

The present disclosure provides a three-dimensional stacked semiconductor device including hybrid bonding and a method for manufacturing the same. In the present disclosure, the method for manufacturing the three-dimensional stacked semiconductor device includes a step of preparing semiconductor devices, and a step of stacking the semiconductor devices through hybrid bonding, wherein the step of preparing the semiconductor devices may include a step of forming an insulating layer on a chip, a step of forming a stop layer on the insulating layer, a step of forming at least one pad hole penetrating the insulating layer and the stop layer, a step of forming a metal layer on the stop layer while forming a metal pad in the pad hole, a step of planarizing the metal layer while leaving the metal pad, and a step of removing the stop layer.

Description

{3D STACKED SEMICONDUCTOR DEVICES INCLUDING HYBRID BONDING AND MANUFACTURING METHODS THEREOF}

The present disclosure relates to a three-dimensional stacked semiconductor device including hybrid bonding and a method for manufacturing the same.

The miniaturization of semiconductor devices has reached its limit due to physical limitations and increased manufacturing costs. Research is actively being conducted on semiconductors that overcome the limitations of such miniaturization, perform more functions, and have higher performance, and the field that has recently received the most attention is the field of artificial intelligence computing that simulates the human brain. The field that will lead the future 4th industrial revolution is the field of artificial intelligence computing, and for this, artificial intelligence semiconductors that require low power, high integration, various functions, and super speed are essential.

In order to implement all the performance and functions required in AI semiconductors, heterogeneous integration technology utilizing 2.5D or 3D packaging technology must be applied. All of the world's top semiconductor companies are staking their lives on the development of next-generation semiconductor products that apply heterogeneous integration technology using 2.5D or 3D packaging methods. A representative product is an AI-oriented fusion device that combines HBM (high bandwidth memory) devices and logic devices. The heterogeneous integration technology using 2.5D or 3D packaging methods currently applied to mass-produced products is implemented using TSV (through silicon via) process technology, and bonding technology using solder bumps is used to electrically and mechanically connect chips to chips. In order to meet the demand for miniaturization of 2.5D or 3D stacked devices and an increase in the number of I/O (in/out) pads required for inter-chip communication, the size of solder bumps is continuously decreasing. The size of solder bumps has continued to decrease with the application of copper pillar technology and micro-bump technology, but it has currently reached its physical limit (diameter > 10 ㎛), and new technology development is required to implement I/O with a finer pitch.

By implementing fine-pitch I/O, semiconductor devices can be further miniaturized, and by increasing the number of I/O pads, ultra-high-speed semiconductor devices can be implemented by increasing the bandwidth of data transmission between chips. The technology that is receiving the most attention in order to implement fine-pitch I/O of 10 ㎛ or less, which is the limit of the bonding technology using the current solder bump, is the hybrid bonding technology. Since it directly connects the pads of a chip and the pads of an adjacent chip without using bumps, it can implement an ultra-fine pitch of 1 ㎛ or less. According to the metal interconnect roadmap for packaging, the final goal is a 3D heterogeneous integration technology that combines TSV technology and hybrid bonding technology without using bumps. Hybrid bonding makes it possible to manufacture artificial intelligence-oriented fusion semiconductors with low-power, high-density, and high-speed characteristics.

The present disclosure provides a three-dimensional stacked semiconductor device including hybrid bonding and a method for manufacturing the same.

In the present disclosure, a method for manufacturing a three-dimensionally stacked semiconductor device includes a step of preparing semiconductor devices, and a step of stacking the semiconductor devices through hybrid bonding, wherein the step of preparing the semiconductor devices may include a step of forming an insulating layer on the chip, a step of forming the stop layer on the insulating layer, a step of forming at least one pad hole penetrating the insulating layer and the stop layer, a step of forming a metal layer on the stop layer while forming a metal pad in the pad hole, a step of planarizing the metal layer while leaving the metal pad, and a step of removing the stop layer.

According to the present disclosure, when preparing an individual semiconductor device, a global step difference due to an erosion phenomenon that occurs during planarization of a metal layer on the stop layer and the metal pads by forming a stop layer on an insulating layer can be reduced or eliminated. Accordingly, when stacking semiconductor devices through hybrid bonding, problems such as voids, cracks, and delamination that may occur between semiconductor devices can be suppressed or prevented. That is, as the global step difference is reduced or eliminated, the metal pads can be positioned closely without a large gap between them, and can contact each other more effectively. This can improve the reliability of a three-dimensionally stacked semiconductor device that is ultimately manufactured.

FIG. 1 is a flowchart schematically illustrating a method for manufacturing a three-dimensional stacked semiconductor device according to one embodiment.
FIGS. 2 to 9 are exemplary diagrams for explaining a method for manufacturing a three-dimensional stacked semiconductor device according to one embodiment.
FIG. 10 is a flowchart schematically illustrating a method for manufacturing a three-dimensional stacked semiconductor device according to another embodiment.
FIGS. 11 to 20 are exemplary diagrams for explaining a method for manufacturing a three-dimensional stacked semiconductor device according to another embodiment.

Hereinafter, various embodiments of the present disclosure are described with reference to the attached drawings.

FIG. 1 is a flowchart schematically illustrating a method for manufacturing a three-dimensionally stacked semiconductor device according to one embodiment. FIGS. 2 to 9 are exemplary diagrams for explaining a method for manufacturing a three-dimensionally stacked semiconductor device according to one embodiment. In FIGS. 2 to 6, (a) is a cross-sectional view, (b) is a plan view, and FIGS. 7 to 9 are cross-sectional views.

Referring to FIG. 1, in step 110, at least one metal via (215) may be formed in an individual chip (211). At this time, the chip (211) may be implemented on a wafer (213) made of silicon material. Then, the metal via (215) may be formed through a TSV process. Specifically, at least one through hole penetrating the chip (211) and the wafer (213) may be formed, and then the through hole may be filled using a metal material, whereby the metal via (215) may be formed, as illustrated in FIG. 2.

Next, in step 120, an insulating layer (311) may be formed on the individual chip (211). Here, the insulating layer (311) may include an oxide. Specifically, the insulating layer (311) may be deposited on the upper surface of the chip (211). Then, in step 130, at least one pad hole (315) may be formed in the insulating layer (311) on the metal via (215). At this time, the pad hole (315) may be formed through a patterning process. Specifically, the insulating layer (311) may be removed on the metal via (215), thereby forming the pad hole (315). As a result, the pad hole (315) may expose the metal via (215). Therefore, as illustrated in FIG. 3, the insulating layer (311) and the pad hole (315) may be provided on the chip (211).

Next, in step 140, while filling the pad hole (315), a metal layer (410, 510) may be formed on the insulating layer (311). At this time, the metal layer (410, 510) may include an auxiliary metal layer (410) and a pad metal layer (510). Here, the auxiliary metal layer (410) may include a barrier metal layer for preventing out-diffusion of the metal material of the pad metal layer (510) and a seed metal layer for assisting the deposition of the pad metal layer (510). Specifically, a barrier metal layer is formed on the surface of the insulating layer (311) and the surface of the metal via (215) in the pad hole (315) on the chip (211), and then a seed metal layer is formed on the surface of the barrier metal layer, whereby the auxiliary metal layer (410) may be formed, as illustrated in FIG. 4. Here, the auxiliary metal layer (410) can be formed with a generally uniform thickness. Then, as shown in FIG. 5, a pad metal layer (510) can be formed on the surface of the auxiliary metal layer (410), including the inside of the pad hole (315). Here, the pad metal layer (510) can include a metal material, for example, copper. At this time, the pad metal layer (510) can be formed through an electrolytic plating process.

Continuing, at step 150, the metal layer (410, 510) may be planarized while leaving the metal pad (615). Here, the metal pad (615) may be individually electrically connected to the metal via (215). At this time, the metal layer (410, 510) may be planarized through a chemical mechanical planarization (CMP) process. Specifically, as illustrated in FIG. 6, the metal layer (410, 510) may be removed on the insulating layer (311) and the metal pad (615). When there are a plurality of pad holes (315) in the insulating layer (311), as the metal layer (410, 510) is planarized, the plurality of metal pads (615) may remain separated from each other.

However, during flattening, the flattening speed may be uneven due to the presence of the metal pad (615). That is, in the area where the metal pad (615) exists, the flattening speed may be faster than in the area where the metal pad (615) does not exist. The flattening speed may be faster as the arrangement density of the metal pads (615) increases. As a result, as illustrated in FIG. 6, an erosion phenomenon may occur in which a global step is formed between the area where the metal pad (615) exists and the area where the metal pad (615) does not exist. In addition, during flattening, as illustrated in FIG. 6, a dishing phenomenon may occur in which a step is generated depending on the position on the surface of the metal pad (615).

In this way, semiconductor devices (600) can be prepared.

Finally, in step 160, semiconductor elements (600) can be laminated through hybrid bonding. At this time, for two semiconductor elements (600), the insulating layers (311) can be bonded to each other, and the metal pads (615) can be bonded to each other. This will be described in more detail later.

First, as illustrated in FIG. 7, two semiconductor elements (600) may be placed so that their respective insulating layers (311) face each other and their respective metal pads (615) face each other. For example, two semiconductor elements (600) may be placed vertically, but the upper semiconductor element (600) may be inverted to face the lower semiconductor element (600).

Next, as illustrated in FIG. 7, plasma pretreatment may be performed on the insulating layers (311) to activate the surfaces of the insulating layers (311). At this time, a natural oxide film formed on the surfaces of the metal pads (615) may be removed by the plasma pretreatment. Here, the plasma pretreatment may be performed using argon (Ar) gas. Then, as illustrated in FIG. 8, pressure may be applied between the semiconductor elements (600) to bond the surfaces of the insulating layers (311). For example, when the oxide of the insulating layers (311) is SiO ₂ , the surfaces of the insulating layers (311) may be activated to a SiOx state by the plasma pretreatment, so that Si-OH bonds are formed by contact with air, and Si-O-Si bonding may be formed by the pressure.

Next, as illustrated in FIG. 9, heat may be applied between the semiconductor elements (600) to bond the metal pads (615). Here, heat may be applied at a temperature within a range of approximately 200° C. to 400° C. At this time, the metal pads (615) may expand due to the heat and come into contact with each other, and the metal pads (615) may be bonded due to diffusion of the metal material of the metal pads (615).

However, a defect in which the metal pads (615) do not make contact may occur due to an erosion phenomenon that occurs during planarization to prepare the semiconductor elements (600). That is, a large gap is formed between the metal pads (615) due to a global step caused by the erosion phenomenon, so that the metal pads (615) may not make contact despite the application of heat and diffusion of the metal material of the metal pads (615). This may cause problems such as voids, cracks, and delamination between the semiconductor elements (600).

FIG. 10 is a flowchart schematically illustrating a method for manufacturing a three-dimensionally stacked semiconductor device according to another embodiment. FIGS. 11 to 20 are exemplary views for explaining a method for manufacturing a three-dimensionally stacked semiconductor device according to another embodiment. In FIGS. 11 to 17, (a) is a cross-sectional view, (b) is a plan view, and FIGS. 18 to 20 are plan views.

Referring to FIG. 10, in step 1010, at least one metal via (1115) may be formed in an individual chip (1111). At this time, the chip (1111) may be implemented on a wafer (1113) made of silicon material. Then, the metal via (1115) may be formed through a TSV process. Specifically, at least one through hole penetrating the chip (1111) and the wafer (1113) may be formed, and then the through hole may be filled using a metal material, whereby the metal via (1115) may be formed, as illustrated in FIG. 11.

Next, in step 1020, an insulating layer (1211) may be formed on the individual chip (1111). Here, the insulating layer (1211) may include an oxide. Specifically, as illustrated in FIG. 12, the insulating layer (1211) may be deposited on an upper surface of the chip (1111). Then, in step 1030, a stop layer (1213) may be formed on the insulating layer (1211). Here, the stop layer (1213) may include a nitride. Specifically, as illustrated in FIG. 12, the stop layer (1213) may be deposited on an upper surface of the insulating layer (1211).

Next, in step 1040, at least one pad hole (1315) may be formed within the insulating layer (1211) and the stop layer (1213) on the metal via (1115). At this time, the pad hole (1315) may be formed through a patterning process. Specifically, the pad hole (1315) may be formed by removing the insulating layer (1211) and the stop layer (1213) together on the metal via (1115). As a result, the pad hole (1315) may expose the metal via (1115). Therefore, as illustrated in FIG. 13, the insulating layer (1211) and the stop layer (1213) and the pad hole (1315) may be provided on the chip (1111).

Next, in step 1050, while filling the pad hole (1315), a metal layer (1410, 1510) may be formed on the stop layer (1213). At this time, the metal layer (1410, 1510) may include an auxiliary metal layer (1410) and a pad metal layer (1510). Here, the auxiliary metal layer (1410) may include a barrier metal layer to prevent diffusion of a metal material of the pad metal layer (1510) and a seed metal layer to assist in the deposition of the pad metal layer (1510). Specifically, a barrier metal layer is formed on the surface of the insulating layer (1211) and the stop layer (1213) on the chip (1111) and the surface of the metal via (1115) in the pad hole (1315), and then a seed metal layer is formed on the surface of the barrier metal layer, so that an auxiliary metal layer (1410) can be formed, as illustrated in FIG. 14. Here, the auxiliary metal layer (1410) can be formed with a generally uniform thickness. Then, as illustrated in FIG. 15, a pad metal layer (1510) can be formed on the surface of the auxiliary metal layer (1410) while filling the interior of the pad hole (1315). Here, the pad metal layer (1510) can include a metal material, for example, copper. At this time, the pad metal layer (1510) can be formed through an electrolytic plating process.

Next, at step 1060, the metal layers (1410, 1510) can be planarized while leaving the metal pads (1615). Here, the metal pads (1615) can be individually electrically connected to the metal vias (1115). At this time, the metal layers (1410, 1510) can be planarized through a chemical mechanical polishing process. Specifically, as illustrated in FIG. 16, the metal layers (1410, 1510) can be removed on the insulating layer (1211), the stop layer (1213), and the metal pad (1615). When there are a plurality of pad holes (1215) in the insulating layer (1211) and the stop layer (1213), as the metal layers (1410, 1510) are planarized, the plurality of metal pads (1615) can be separated from each other and remain.

During the flattening, the flattening speed may be uneven due to the presence of the metal pad (1615). That is, in the area where the metal pad (1615) exists, the flattening speed may be faster than in the area where the metal pad (1615) does not exist. The flattening speed may be faster as the arrangement density of the metal pads (1615) is higher. As a result, an erosion phenomenon may occur in which a global step is formed between the area where the metal pad (1615) exists and the area where the metal pad (1615) does not exist. As a result, as illustrated in FIG. 16, when the metal layers (1410, 1510) are removed, the stop layer (1213) on the metal pad (1615) is removed, and at least a portion of the stop layer (1213) may remain on the insulating layer (1211). In addition, during this flattening, a dishing phenomenon may occur in which a step is generated depending on the location on the surface of the metal pad (1615), as illustrated in FIG. 16.

Continuing, at step 1070, the stop layer (1213) can be removed. Specifically, as illustrated in FIG. 17, the stop layer (1213) remaining on the insulating layer (1211) in the area where the metal pad (1615) does not exist can be removed. At this time, the stop layer (1213) can be removed using a phosphoric acid (H ₃ PO ₄ ) solution. As a result, the global step between the area where the metal pad (1615) exists and the area where the metal pad (1615) does not exist due to the erosion phenomenon can be reduced or eliminated.

In this way, semiconductor devices (1700) can be prepared.

Finally, at step 1080, semiconductor elements (1700) can be stacked through hybrid bonding. At this time, for two semiconductor elements (1700), insulating layers (1211) can be bonded to each other, and metal pads (1615) can be bonded to each other. This will be described in more detail below.

First, as illustrated in FIG. 18, two semiconductor elements (1700) may be placed so that their respective insulating layers (1211) face each other and their respective metal pads (1615) face each other. For example, the two semiconductor elements (1700) may be placed vertically, but the upper semiconductor element (1700) may be inverted to face the lower semiconductor element (1700).

Next, as illustrated in FIG. 18, plasma pretreatment may be performed on the insulating layers (1211) to activate the surfaces of the insulating layers (1211). At this time, a natural oxide film formed on the surfaces of the metal pads (1615) may be removed by the plasma pretreatment. Here, the plasma pretreatment may be performed using argon (Ar) gas. Then, as illustrated in FIG. 19, pressure may be applied between the semiconductor elements (1700) to bond the surfaces of the insulating layers (1211). For example, when the oxide of the insulating layers (1211) is SiO ₂ , the surface of the insulating layers (1211) may be activated to a SiOx state by the plasma pretreatment, so that a Si-OH bond is formed by contact with air, and a Si-O-Si bond may be formed by the pressure.

Next, as illustrated in FIG. 20, pressure and heat may be applied between the semiconductor elements (1700) to bond the metal pads (1615). Here, heat may be applied at a temperature in the range of approximately 200° C. to 400° C. At this time, since the global step between the area where the metal pads (1615) exist and the area where the metal pads (1615) do not exist due to the erosion phenomenon that occurs when preparing the semiconductor elements (1700) is reduced or eliminated, the metal pads (1615) can be positioned closely together without a large gap therebetween. Accordingly, the metal pads (1615) may expand due to the heat and come into contact with each other, and the metal pads (1615) may be bonded due to the diffusion of the metal material of the metal pads (1615). In addition, problems such as voids, cracks, and peeling that may occur between the semiconductor elements (1700) can be suppressed or prevented.

According to the present disclosure, when preparing an individual semiconductor device (1700), by forming a stop layer (1213) on an insulating layer (1211), a global step difference due to an erosion phenomenon that occurs during planarization of a metal layer (1410, 1510) on the stop layer (1213) and the metal pad (1615) can be reduced or eliminated. Accordingly, when stacking the semiconductor devices (1700) through hybrid bonding, problems such as voids, cracks, and delamination that may occur between the semiconductor devices (1700) can be suppressed or prevented. That is, as the global step difference is reduced or eliminated, the metal pads (1615) can be positioned closely together without a large gap therebetween, thereby more effectively contacting each other. This can improve the reliability of a three-dimensionally stacked semiconductor device that is manufactured as a result.

In summary, the present disclosure provides a method for manufacturing a three-dimensionally stacked semiconductor device.

In the present disclosure, a method for manufacturing a three-dimensionally laminated semiconductor device includes a step of preparing semiconductor devices (1700), and a step of laminating the semiconductor devices (1700) through hybrid bonding (step 1080), wherein the step of preparing the semiconductor devices (1700) includes a step of forming an insulating layer (1211) on a chip (1111) (step 1020), a step of forming a stop layer (1213) on the insulating layer (1211) (step 1030), a step of forming at least one pad hole (1315) penetrating the insulating layer (1211) and the stop layer (1213) (step 1040), a step of forming a metal layer (1410, 1510) on the stop layer (1213) while forming a metal pad (1615) in the pad hole (1315) (step 1050), and a step of planarizing the metal layer (1410, 1510) while leaving the metal pad (1615). step (step 1060), and a step of removing the stop layer (step 1070).

In the present disclosure, the step of planarizing the metal layer (1410, 1510) (step 1060) can remove the stop layer (1213) on the metal pad (1615) while removing the metal layer (1410, 1510) and leave the stop layer (1213) on the insulating layer (1211) to at least a portion of its thickness.

In the present disclosure, the step of removing the stop layer (1213) (step 1070) can remove the stop layer (1213) remaining on the insulating layer (1211).

In the present disclosure, the stationary layer (1213) may include a nitride.

In the present disclosure, the step of removing the stationary layer (1213) (step 1070) may include a step of removing the stationary layer (1213) using a phosphoric acid solution.

In the present disclosure, the step (step 1080) of stacking semiconductor elements (1700) through hybrid bonding may include the steps of arranging two semiconductor elements (1700) such that their respective insulating layers (1211) face each other and their respective metal pads (1615) face each other, the step of bonding the insulating layers (1211), and the step of bonding the metal pads (1615).

In the present disclosure, the step of bonding the insulating layers (1211) may include the step of performing plasma pretreatment on the insulating layers (1211) to activate the surfaces of the insulating layers (1211), and the step of applying pressure between the semiconductor elements (1700) to bond the surfaces of the insulating layers (1211).

In the present disclosure, the step of bonding the metal pads (1615) may include the step of bonding the metal pads (1615) by applying pressure and heat between the semiconductor elements (1700).

In the present disclosure, the insulating layer (1211) may include an oxide.

In the present disclosure, the step of preparing semiconductor devices (1700) may further include a step (step 1010) of forming at least one metal via (1115) within a chip (1111) before the step of forming an insulating layer (1211).

In the present disclosure, the step of forming a pad hole (1315) (step 1040) includes the step of forming the pad hole (1315) by removing the insulating layer (1211) and the stop layer (1213) on the metal via (1115), thereby allowing the metal pad (1615) to communicate with the metal via (1115).

In addition, the present disclosure provides a three-dimensionally stacked semiconductor device manufactured according to the manufacturing method described above.

The various embodiments of this document and the terminology used herein are not intended to limit the technology described in this document to the specific embodiments, but should be understood to encompass various modifications, equivalents, and/or substitutes of the embodiments. In connection with the description of the drawings, similar reference numerals may be used for similar components. The singular expressions may include plural expressions unless the context clearly indicates otherwise. In this document, expressions such as "A or B", "at least one of A and/or B", "A, B, or C" or "at least one of A, B and/or C" can include all possible combinations of the items listed together. Expressions such as "first", "second", "first" or "second" can modify the corresponding components, regardless of order or importance, and are only used to distinguish one component from another component and do not limit the corresponding components. When it is said that a certain (e.g., a first) component is "(functionally or communicatively) connected" or "connected" to another (e.g., a second) component, said certain component may be directly connected to said other component, or may be connected via another component (e.g., a third component).

According to various embodiments, each component of the described components may include a single or multiple entities. According to various embodiments, one or more components or steps of the aforementioned components may be omitted, or one or more other components or steps may be added. Alternatively or additionally, the plurality of components may be integrated into one component. In such a case, the integrated component may perform one or more functions of each component of the plurality of components identically or similarly to those performed by the corresponding component of the plurality of components prior to integration.

Claims (10)

In a method for manufacturing a three-dimensionally laminated semiconductor device,
Step of preparing semiconductor devices; and
A step of stacking the above semiconductor elements through hybrid bonding
Including,
The steps for preparing the above semiconductor devices are:
A step of forming an insulating layer on a chip;
A step of forming a stop layer on the above insulating layer;
A step of forming at least one pad hole penetrating the insulating layer and the stop layer;
A step of forming a metal layer on the stop layer while forming a metal pad within the pad hole;
a step of flattening the metal layer while leaving the metal pad; and
Step for removing the above-mentioned stop layer
Including,
On the chip, a first region having the metal pad and a second region of the remainder are defined,
The step of flattening the above metal layer is:
Since the speed of planarizing the metal layer is different in the first region and the second region, the stop layer in the first region is removed while removing the metal layer, and the stop layer in the second region is left with a certain thickness, thereby generating a step between the first region and the second region.
The step of removing the above-mentioned stop layer is:
By removing the remaining stop layer on the insulating layer, the step is reduced or eliminated.
A method for manufacturing a three-dimensionally laminated semiconductor device.
delete In paragraph 1,
The above-mentioned stop layer comprises a nitride,
A method for manufacturing a three-dimensionally laminated semiconductor device.
In paragraph 1,
The step of removing the above-mentioned stop layer is:
Step of removing the above-mentioned stationary layer using a phosphoric acid solution
Including,
A method for manufacturing a three-dimensionally laminated semiconductor device.
In paragraph 1,
The step of stacking the semiconductor elements through the above hybrid bonding is:
A step of arranging two semiconductor elements so that their respective insulating layers face each other and their respective metal pads face each other;
a step of bonding the above insulating layers; and
Step of bonding the above metal pads
Including,
A method for manufacturing a three-dimensionally laminated semiconductor device.
In paragraph 5,
The step of bonding the above insulating layers is:
A step of activating the surfaces of the insulating layers by performing plasma pretreatment on the insulating layers; and
A step of bonding the surfaces of the insulating layers by applying pressure between the semiconductor elements.
Including,
A method for manufacturing a three-dimensionally laminated semiconductor device.
In paragraph 5,
The step of bonding the above metal pads is:
A step of bonding the metal pads by applying pressure and heat between the semiconductor elements.
Including,
A method for manufacturing a three-dimensionally laminated semiconductor device.
In paragraph 1,
The above insulating layer comprises an oxide,
A method for manufacturing a three-dimensionally laminated semiconductor device.
In paragraph 1,
The steps for preparing the above semiconductor devices are:
Before the step of forming the above insulating layer,
A step of forming at least one metal via within the chip
Including more,
The step of forming the above pad hole is:
A step of forming the pad hole by removing the insulating layer and the stop layer on the metal via.
, and thereby, the metal pad is in communication with the metal via.
A method for manufacturing a three-dimensionally laminated semiconductor device.
A three-dimensional stacked semiconductor device manufactured according to the manufacturing method described in any one of claims 1 to 9.