KR102365470B1 - Capacitance-based sequential matrix multiplication neural network by controlling weights with transistor-capacitor pair - Google Patents

Abstract

A capacitance-based sequential matrix multiplication neural network capable of adjusting a weight with a transistor-capacitor pair according to an embodiment of the present invention includes a word line, a bit line, and a transistor connected to a capacitor, and a capacitor connected to the transistor, wherein the bit line The input is connected to the pulse generator and the output is connected to the sense amplifier.

Description

CAPACITANCE-BASED SEQUENTIAL MATRIX MULTIPLICATION NEURAL NETWORK BY CONTROLLING WEIGHTS WITH TRANSISTOR-CAPACITOR PAIR

The present invention relates to a neural network, and more particularly, to a capacitance-based sequential matrix multiplication neural network capable of adjusting a weight by a transistor-capacitor pair.

The mobile neural processor performs learning by a server or computer, and stores the learning results in the mobile neural processor to perform inference. At this time, it is preferable that the value stored in the weight of the neural processor be multi-level, but there is a limit to the multi-level value. width) and then store the value as the mobile neural processor weight. This weight may be stored in a non-volatile memory or a volatile memory.

For servers, there is Google's Tensor Processing Unit (TPU), which stores weight values in DRAM, fetches them, and sends them to the matrix multiply unit (MMU). The output calculation result is sent back to the matrix multiplier input together with the new weight value stored in DRAM, and circulated until the final output result is obtained.

When the weights are stored and used in the nonvolatile memory, the reasoning speed is fast, but there is a disadvantage in that the circuit overhead increases because all hidden layers must be manufactured. In the case of Google's TPU, weight information is stored outside the neural network, and the inference speed is reduced, but circuit overhead can be reduced because it is sequentially calculated while using the same neural network again.

Capacitance-based matrix multiplication uses capacitance as a weight. There are ways to group capacitors or change the size of capacitors to determine the weight.

The above description is only for helping the understanding of the background for the technical ideas of the present invention, and therefore it cannot be understood as the content corresponding to the prior art known to those skilled in the art.

The present invention is a neural network configuration and operating principle related to a weight adjustment method for performing learning results in artificial intelligence learning

Since there is a physical limit to manufacturing a weight element in multi-level using hardware, it cannot follow the weight bit-width used in software. For example, a 16-bit wide multilevel resistive memory material with 65,536 resistance levels is currently difficult to implement. Therefore, it is necessary to devise a structure and operation method of a matrix multiplier that can perform matrix multiplication while inputting weight values as flexibly as software.

The method of changing the size of a capacitor is a method of selecting the required size after manufacturing capacitors of various sizes, and the method of tying capacitors is a method of operating several capacitors at the same time. In this case, the circuit becomes complicated, and in particular, it is affected by parasitic capacitance such as bit line capacitance. In addition, manufacturing as many hidden layers as necessary is another problem that limits the size of a chip.

In order to achieve the above object, according to an embodiment of the present invention, there is provided a capacitance-based sequential matrix multiplication neural network capable of adjusting a weight by a transistor-capacitor pair, comprising: a transistor connected to a word line, a bit line, and a capacitor; and a capacitor connected to the transistor, wherein an input of the bit line is connected to a pulse generator and an output is connected to a sense amplifier.

A selection transistor may be further included between the sense amplifier and the bit line.

The display device may further include a diode disposed between the sense amplifier and the selection transistor.

An accumulator disposed between the sense amplifier and the diode may be further included.

A selection transistor for selection disposed between the sense amplifier and the accumulator may be further included.

A discriminator may be further included between the sense amplifier and the selection transistor for selection.

A diode may be further included between the bit line and the pulse oscillator.

A wiring connecting a P-well corresponding to a ground of the selection transistor between the diode and the pulse oscillator may be further included.

A voltage applied to the word line may be a constant voltage, and a voltage applied to the bit line may correspond to an input signal.

The pulse voltage applied to the bit line may be twice or more of the constant voltage applied to the capacitor plate.

Transistor-capacitor pair according to an embodiment of the present invention provides a capacitance-based sequential matrix multiplication neural network capable of adjusting weights, comprising: a transistor connected to a word line, a bit line, and a capacitor; a capacitor connected to the transistor; and a plate coupled to the capacitor, wherein the input of the bit line is coupled to a pulse generator and the output includes weight cells coupled to a sense amplifier.

By sequentially applying voltages to the word lines of the weight cells, matrix multiplication may be sequentially performed.

Matrix multiplication may be performed using the output information of the matrix multiplication as input information of the next hidden layer.

The apparatus may further include a storage medium external to the neural network for storing iteration number information, weight information, input information, output information, and hidden layer information for a result of repeatedly performing matrix multiplication.

Matrix multiplication may be sequentially performed by selecting two or more word lines of the weight cells and simultaneously applying gate voltages.

According to an embodiment of the present invention, a capacitance-based sequential matrix multiplication neural network capable of adjusting a weight using a transistor-capacitor pair includes: a word line, a bit line, and a transistor connected to a capacitor; a capacitor connected to the transistor; and a plate connected to the capacitor, wherein an input of the bit line is connected to a pulse generator and an output is connected to a sense amplifier; a transistor coupled to the word line, the bit line, and the capacitor; a capacitor connected to the transistor; and a plate connected to the capacitor, wherein the bit line includes output of the first weight cells and second weight cells connected to a sense amplifier.

The display device may further include a diode disposed between an output of the first weight cells and an input of the second weight cells.

By sequentially applying voltages to the word lines of the first weight cells, matrix multiplication may be sequentially performed.

Matrix multiplication may be performed by storing output information of the matrix multiplication in the second weight cells and using it as input information of a next hidden layer.

The second weight cells may collect charges discharged from the first weight cells.

As described above, the capacitance-based sequential matrix multiplication neural network capable of adjusting the weight by a transistor-capacitor pair according to the embodiment of the present invention can flexibly adjust the weight and the number of hidden layers, and can reduce the circuit load and the size of the matrix multiplication unit chip (matrix multiplication unit chip size) can also be minimized.

1 is a circuit diagram schematically illustrating a neural network according to an embodiment of the present invention.
2 is a circuit diagram schematically illustrating a weight cell of a neural network according to an embodiment of the present invention.
3 is a circuit diagram schematically illustrating an operation principle of a weight cell of a neural network according to an embodiment of the present invention.
4 is a circuit diagram schematically illustrating a configuration of a neural network according to an embodiment of the present invention.
5, 6, and 7 are circuit diagrams for explaining the operation of a neural network according to an embodiment of the present invention.

The content described in the technical field that is the background of the present invention is only for helping the understanding of the background for the technical idea of the present invention, and therefore it can be understood as the content corresponding to the prior art known to those skilled in the art of the present invention. none.

In the following description, for purposes of explanation, numerous specific details are set forth to aid in understanding various embodiments. It will be evident, however, that various embodiments may be practiced without these specific details or in one or more equivalent manners. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring the various embodiments.

In the drawings, the size or relative size of layers, films, panels, regions, etc. may be exaggerated for clarity. Also, like reference numbers indicate like elements.

Throughout the specification, when a part is "connected" with another part, this includes not only the case where it is "directly connected" but also the case where it is "indirectly connected" with another element interposed therebetween. . However, if it is described that a part is "directly connected" to another part, this will mean that there is no other element between the part and the other part. “At least any one of X, Y, and Z” and “at least any one selected from the group consisting of X, Y, and Z” means one X, one Y, one Z, or two of X, Y, and Z or Any further combination (eg, XYZ, XYY, YZ, ZZ) will be understood. Herein, “and/or” includes any combination of one or more of the components.

Although terms such as first, second, etc. may be used herein to describe various elements, elements, regions, layers, and/or sections, such elements, elements, regions, layers, and/or or sections are not limited to these terms. These terms are used to distinguish one element, element, region, layer, and/or section from another element, element, region, layer, and/or section. Accordingly, a first element, element, region, layer, and/or section in one embodiment may be referred to as a second element, element, region, layer, and/or section in another embodiment.

Spatially relative terms such as "below", "above", etc. may be used for descriptive purposes, thereby describing the relationship of one element or feature to another element(s) or feature(s) as shown in the drawings. do. This is only used to indicate the relationship of one component to another component in the drawing, and does not mean an absolute position. For example, if the device shown in the figures is turned over, elements depicted as being "below" other elements or features are positioned "above" the other elements or features. Thus, in one embodiment, the term “below” may include both up and down. In addition, the device may be otherwise oriented (eg, rotated 90 degrees or in other orientations), and such spatially relative terms used herein are interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments and not for the purpose of limitation. Throughout the specification, when a part "includes" a certain component, it means that other components may be further included, rather than excluding other components, unless otherwise stated. Unless otherwise defined, terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs.

1 is a circuit diagram schematically illustrating a neural network according to an embodiment of the present invention.

Referring to FIG. 1 , a neural network according to an embodiment of the present invention includes an input neuron 10 , an output neuron 20 , and a weight cell 30 . The synapse 30 device is to be disposed at the intersection of a row line (R) extending horizontally from the input neuron 10 and a column line (C) extending vertically from the output neuron 20 can For convenience of explanation, four input neurons 10 and four output neurons 20 are illustrated in FIG. 1 , respectively, but the present invention is not limited thereto.

The input neuron 10 transmits electrical pulses to the weight cell 30 through the row line R in a learning mode, a reset mode, a correction or a reading mode. can

The output neuron 20 may receive an electrical pulse from the weight cell 30 through the column line C in the learning mode, the reset mode, or the correction or read mode.

2 is a circuit diagram schematically illustrating a weight cell of a neural network according to an embodiment of the present invention. 3 is a circuit diagram schematically illustrating an operating principle of a weight cell of a neural network according to an embodiment of the present invention.

In order to flexibly apply the weight bit width according to the embodiment of the present invention, the weight is newly defined. Until now, C was multi-leveled by applying Q=CV (charge=capacitance×voltage) to the weight based on capacitance. Here, the linear multilevel can be expressed as C=nC _O using a multiple of n. At this time, _CO , which is the ground capacitance, becomes the resolution of the weight, and _CO V becomes the resolution of the amount of charge. Here, since n can be converted from a multiple concept to a number concept, a method of applying _CO n times can be introduced. Therefore, the weight can be defined as n.

2 and 3 , a weight cell of a neural network according to an embodiment of the present invention includes a word line (WL), a bit line (BL), a transistor connected to a capacitor, and a capacitor connected to the transistor and the word line is disposed perpendicular to the bit line. As an embodiment, the input of the bit line may be connected to a pulse oscillator and the output may be connected to a sense amplifier.

) 동안 게이트 전압을 인가함으로써 뉴럴 네트위크의 가중치 셀에 펄스 트레인이 인가되는 시간, 즉 인가되는 펄스 횟수(n_j)를 조절할 수 있다. j는 가중치 셀 어레이의 열의 개수이다.According to an embodiment of the present invention, a selection transistor ST is disposed between the bit line and the sense amplifier. As an embodiment, the gate of the selection transistor is

), it is possible to control the time for which the pulse train is applied to the weight cells of the neural network, that is, the number of pulses applied (n _j ). j is the number of columns in the weight cell array.

According to an embodiment of the present invention, the amount of charge discharged for a predetermined time by repeatedly charging and discharging a capacitor using a weight cell composed of a transistor and a capacitor is an output value. As an embodiment, the voltage applied to the word line of the weight cell is a constant voltage, and the voltage applied to the bit line is a pulse voltage corresponding to the input signal. As an embodiment, the voltage applied to the bit line may be at least twice the constant voltage applied to the capacitor plate.

4 is a circuit diagram schematically illustrating a configuration of a neural network according to an embodiment of the present invention.

Referring to FIG. 4 , a weight cell of a neural network according to an embodiment of the present invention includes a word line WL, a bit line BL, and a transistor connected to a capacitor, a capacitor connected to the transistor, and a capacitor connected to the capacitor. and a plate coupled thereto, the input of the bit line coupled with the pulse oscillator and the output coupled with the sense amplifier.

3 and 4 , a pulse train of an input voltage Vpj corresponding to an input signal is applied to a bit line of a transistor, and a voltage Vg is applied to a word line, but sequentially applied row by row. As an embodiment, two, three, or more rows can be operated simultaneously to increase the amount of discharge linearly.

According to an embodiment of the present invention, a self voltage divider is disposed between the common pulse oscillator and each bit line to adjust the pulse train voltage input to each bit line. As an embodiment, the pulse voltage V _pj input to the bit line may be determined by adjusting the gate voltage Vj of the self voltage divider.

) 동안 게이트 전압을 인가함으로써 펄스 트레인 전압이 인가되는 시간을 조절한다.A selection transistor is disposed at the output of the bit line, and each of the gates of the selection transistor is

), by applying the gate voltage, the time for which the pulse train voltage is applied is controlled.

)C(Vpj-Vcc/2)가 된다. n(

)는 펄스 폭

에 의해 선형적으로 결정되는 입력 펄스 횟수(count)이다. 이 관계에 의해 입력 전압과 가중치에 해당하는 n과의 곱셈(multiplication)이 가능해진다.

의 최소 기본 단위를

라고 하면 n(

)C(Vpj-Vcc/2)는 Q의 해상도(resolution)가 된다. 행을 묶어서 작동하는 경우는 행 수만큼의 비율로 가중치의 선형성(linearity)을 확장할 수 있다. The amount of charge emitted from each weight cell of the neural network according to the embodiment of the present invention is Q = n (

)C(Vpj-Vcc/2). n (

) is the pulse width

It is the number of input pulses linearly determined by . This relationship enables multiplication between the input voltage and n corresponding to the weight.

the smallest basic unit of

If n (

)C(Vpj-Vcc/2) becomes the resolution of Q. In the case of operating by grouping rows, the linearity of the weights can be extended by a ratio equal to the number of rows.

As an embodiment, a diode may be disposed between the bit line and the self voltage divider in order to prevent a discharge charge discharged from the bit line from flowing back to the pulse oscillator during an input pulse delay of the pulse oscillator.

As an embodiment, in order to prevent a pulse from being directly transmitted to the bit line to the selector while the pulse voltage of the pulse oscillator is applied, a P-well corresponding to the ground of the select transistor and between the diode and the self voltage divider You can make a wiring that connects them. When a pulse voltage is applied, a voltage is also applied to the selection transistor P well, thereby canceling the gate voltage applied to the selection transistor or turning the selection transistor off beyond that, thereby preventing the pulse from going directly to the selector. Accordingly, the input pulse voltage Vpj may be greater than the gate voltage Vg applied to the selection transistor. (Vpj ≥Vg)

The output bit lines accumulate charges by connecting one array to another 1T-1C transistor-capacitor pair that collects the output charges. In this case, a diode may be added between the selection transistor and the accumulator to prevent a reverse flow of charges due to a reverse voltage that may occur in the accumulator.

5, 6, and 7 are circuit diagrams for explaining the operation of a neural network according to an embodiment of the present invention.

5, 6, and 7, in the neural network according to an embodiment of the present invention, weight cells are configured as an array, the weight cells are manufactured as a network layer, and then each row of the weight cell array is configured. A recurrent or iteration method that operates sequentially and uses the output value as input information for the next hidden layer is applied.

5 and 6, the time for applying an input voltage to each weight cell in a specific row of the neural network according to an embodiment of the present invention is the width of the gate voltage pulse applied to the gates of the selection transistors connected for each column. Adjust. The voltage dynamic range of the self voltage divider is designed according to the dynamic range condition of the voltage input to the bit line. As an embodiment, matrix multiplication may be sequentially performed for each row by sequentially applying voltages to word lines, and weight information and input information for each hidden layer may be stored in a storage medium external to the neural network. Weight information and input information for each layer are stored in an external storage medium and used for cyclic computing during inference.

Referring to FIGS. 5 and 6 , an embodiment in which the second row is selected among i rows can be confirmed, but the present invention is not limited thereto, and the amount of charge and discharge charges can be expanded by selecting several rows at the same time.

It is activated when the amount of accumulated charges exceeds a certain value, and the voltage in the accumulator increases while these charges are accumulated. Since this reverse voltage can prevent charges discharged from the first weight cell array, the 1T-1C cell array constituting the accumulator is manufactured to be sufficiently large. In addition, the accumulated charges are discharged for a certain period of time, and when charges remain in the accumulator, they are used as input information for the next hidden layer. If there are no charges left in the accumulator, there is no input to the next hidden layer. Determination of residual charge is performed by a sense amplifier, and dissipation of charges in the accumulator for a predetermined time is performed by a pair of NMOS-PMOS transistors.

Referring to FIG. 7 , a method of screening and detecting residual charge can be confirmed. In order to send the charge accumulated in the accumulator to the inverter, Vcc/2 voltage is applied to the plate of the accumulator, voltage Vg' is applied to the inverter, and then voltage Vg is applied to the gate of the selection transistor (DT) for selection in front of the inverter. do. When the voltage Vg' is applied to the inverter, the NMOS transistor is turned on, and the accumulated charges are discharged through the NMOS transistor and disappear. If the inverter voltage is removed after a certain period of time, the PMOS transistor operates and residual charge flows toward the sense amplifier, which can detect whether there is a residual charge.

According to the embodiments of the present invention as described above, in the weight cell to which the weight bit width according to the embodiment of the present invention can be flexibly applied, the weight and the number of hidden layers can be flexibly adjusted, and circuit overhead can be reduced. Also, the matrix multiplication unit chip size can be minimized.

As described above, in the present invention, specific matters such as specific components, etc., and limited embodiments and drawings have been described, but these are only provided to help a more general understanding of the present invention, and the present invention is not limited to the above embodiments. , various modifications and variations are possible from these descriptions by those of ordinary skill in the art to which the present invention pertains.

Therefore, the spirit of the present invention should not be limited to the described embodiments, and not only the claims described below, but also all of the claims and all equivalents or equivalent modifications to the claims will be said to belong to the scope of the spirit of the present invention. .

10: input neuron 20: output neuron
30: weight cell

Claims (20)

a transistor coupled to the word line, the bit line, and the capacitor; and
a capacitor connected to the transistor;
An input of the bit line is connected to a pulse generator and an output is connected to a sense amplifier,
a select transistor disposed between the sense amplifier and the bit line;
a diode disposed between the sense amplifier and the selection transistor;
an accumulator disposed between the sense amplifier and the diode;
a selection transistor for selection disposed between the sense amplifier and the accumulator; and
A discriminator between the sense amplifier and the selection transistor for selection,
further comprising,
A capacitance-based sequential matrix multiplicative neural network with tunable weights with transistor-capacitor pairs. delete delete delete delete delete The method of claim 1,
A capacitance-based sequential matrix multiplication neural network capable of adjusting weight with a transistor-capacitor pair, further comprising a diode positioned between the bit line and the pulse oscillator. 8. The method of claim 7,
A capacitance-based sequential matrix multiplication neural network capable of adjusting a weight with a transistor-capacitor pair further comprising a wiring connecting a P-well corresponding to the ground of the selection transistor between the diode and the pulse oscillator. The method of claim 1,
A voltage applied to the word line is a constant voltage, and the voltage applied to the bit line is a pulse voltage corresponding to an input signal. A capacitance-based sequential matrix multiplication neural network whose weight can be adjusted by a transistor-capacitor pair. The method of claim 1,
A capacitance-based sequential matrix multiplication neural network in which the weight of a pulse voltage applied to the bit line can be adjusted by a transistor-capacitor pair that is at least twice a normal voltage applied to a plate connected to the capacitor. a transistor coupled to the word line, the bit line, and the capacitor;
a capacitor connected to the transistor; and
a plate connected to the capacitor;
The input of the bit line includes weight cells connected to a pulse generator and the output connected to a sense amplifier,
sequentially performing matrix multiplication by sequentially applying a voltage to the word lines of the weight cells,
A capacitance-based sequential matrix multiplicative neural network with tunable weights with transistor-capacitor pairs. delete 12. The method of claim 11,
A capacitance-based sequential matrix multiplication neural network capable of adjusting a weight by a transistor-capacitor pair that performs matrix multiplication by using the output information of the matrix multiplication as input information of the next hidden layer. 14. The method of claim 13,
A transistor-capacitor pair that further includes a storage medium external to the neural network for storing iteration number information, weight information, input information, output information, and hidden layer information for a result of repeatedly performing the matrix multiplication. A capacitance-based sequential matrix multiplication neural network. 12. The method of claim 11,
A capacitance-based sequential matrix multiplication neural network capable of adjusting weights using a transistor-capacitor pair that sequentially performs matrix multiplication by selecting two or more word lines of the weight cells and simultaneously applying gate voltages. a transistor coupled to the word line, the bit line, and the capacitor; a capacitor connected to the transistor; and a plate connected to the capacitor, wherein an input of the bit line is connected to a pulse generator and an output is connected to a sense amplifier; and
a transistor coupled to the word line, the bit line, and the capacitor; a capacitor connected to the transistor; and a plate connected to the capacitor, wherein the bit line is a transistor-capacitor pair comprising output of the first weight cells and second weight cells connected to a sense amplifier and a capacitance adjustable in weight Based sequential matrix multiplication neural networks. 17. The method of claim 16,
A capacitance-based sequential matrix multiplication neural network capable of adjusting weight with a transistor-capacitor pair, further comprising a diode disposed between an output of the first weight cells and an input of the second weight cells. 17. The method of claim 16,
A capacitance-based sequential matrix multiplication neural network capable of adjusting weights using a transistor-capacitor pair that sequentially performs matrix multiplication by sequentially applying voltages to word lines of the first weight cells. 19. The method of claim 18,
A capacitance-based sequential matrix multiplication neural network capable of adjusting weights with a transistor-capacitor pair that performs matrix multiplication by storing output information of the matrix multiplication in the second weight cells and using it as input information for a next hidden layer. 20. The method of claim 19,
A capacitance-based sequential matrix multiplication neural network in which the weight of the second weight cells can be adjusted as a transistor-capacitor pair that collects charges discharged from the first weight cells.

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