KR102123999B1 - Device for generating ultra wideband pulse - Google Patents

Abstract

The present invention comprises: a plurality of delay cells providing a square wave voltage to a plurality of transistors according to a specific time period; the plurality of transistors transmitting current to an oscillator according to the specific time period; the oscillator receiving the current to generate a plurality of sinusoidal voltages that are exponentially attenuated; and an output terminal outputting ultra-wide-band pulse. According to the present invention, since the side lobe of the ultra-wide-band pulse generated by an ultra-wide-band pulse generating device is suppressed so as not to exceed a federal communication commission (FCC) spectrum mask, so that the ultra-wide-band pulse corresponds to the FCC spectrum mask.

Description

DEVICE FOR GENERATING ULTRA WIDEBAND PULSE

The present invention relates to a device for generating ultra-wideband pulses required for ultra-wideband (UWB) communication.

The Bluetooth technology, which is currently actively used for short-range communication, has difficulty in real-time transmission when there are many users, and because the communication protocol is complicated and power consumption is large, it is difficult to use for a long time.

Accordingly, communication methods have been proposed to overcome this. Among them, research and development on ultra-wideband communication technologies have been conducted worldwide since the approval of the Federal Communications Commission (FCC) for frequency allocation and commercialization in April 2002. As is actively progressing. In 2007, the IEEE 802.15.4a international standardization group enacted UWB standardization for low-speed, low-power wireless personal area networks (W-PANs) with wireless positioning functions, adding speed to commercial product development.

Unlike conventional wireless communication systems that use continuous sinusoidal waves, at the transmitting end of the Impulse Radio UWB (IR-UWB) system, a pulse with a very narrow width of about 1 nsec or a Gaussian monocycle pulse Intermittently. The ultra-wideband pulse generator is for transmitting a large amount of digital data over a wide spectrum frequency with low power in a short distance section, and is a spectrum mask (ie, a U.S. Federal Communications Commission's protocol to prevent harming a commercially available bandwidth signal). FCC Spectrum Mask).

Among conventional ultra-wideband pulse generating devices, there is one that uses a band pass filter to match the power spectral density (PSD) of the generated pulses to the FCC spectrum mask. However, such a pulse generating apparatus has a problem in that the shape and duration of the pulse are dependent on the transient response characteristics of the band pass filter, so that the desired shape of the pulse is not easy, and an impedance matching circuit for interfacing with the transmitting end antenna is additionally required. .

In addition, among the conventional ultra-wideband pulse generators, a differential structure is adopted, and a balun is used for the interface between the differential output and the final single output of the differential structure. However, such a pulse generating device requires an additional balloon, so there is a problem that energy efficiency is low. In addition, the generation and distribution of a multiphase clock is required according to the desired number of pulses, so there is a problem that the power consumption is large and the system is also large.

Published Patent Publication No. 2010-0068809

The present invention has been devised to solve the above problems, and has an object to provide an ultra-wideband pulse generating device that can easily generate a desired type of pulse while conforming to the FCC spectrum mask.

In addition, an object of the present invention is to provide an ultra-wideband pulse generating device capable of low power operation, low cost, and high energy efficiency.

In order to achieve the above object, the ultra-wideband pulse generating apparatus according to the present invention, a plurality of delay cells for converting the input step voltage to a square wave voltage; A plurality of transistors generating a current by using the square wave voltage converted by each of the plurality of delay cells as an input voltage; An oscillator that receives a current generated by each of the plurality of transistors and generates a plurality of sinusoidal voltages that are exponentially attenuated; And an output terminal which is connected to the plurality of transistors and the oscillator, and outputs an ultra-wideband pulse by synthesizing a plurality of sinusoidal voltages generated by the oscillator.

Here, each of the plurality of delay cells may delay the step voltage by a predetermined time to output a delayed step voltage to a neighboring delay cell, or each of the plurality of delay cells may receive the delayed step voltage from an adjacent delay cell. have.

In addition, each of the plurality of delay cells may delay the step voltage by a predetermined time using an inverter.

In addition, each of the plurality of delay cells may convert the step voltage to a square wave voltage using the inverter and the AND gate.

In addition, the plurality of transistors may be connected to correspond to the plurality of delay cells 1:1.

In addition, the shape of the ultra-wideband pulse output from the output terminal is characterized by being changed according to the magnitude of the current generated in each of the plurality of transistors.

The oscillator may include resistors, inductors, and capacitors connected in parallel with each other.

In addition, a bypass capacitor may be connected to the output terminal to remove a DC component from the ultra-wideband pulse.

In the present invention, a plurality of delay cells provide a square wave voltage to a plurality of transistors according to a specific time period, the plurality of transistors transmit current to the oscillator according to the specific time period, and the oscillator receives the current to exponentially function It is configured to generate a plurality of sinusoidal voltages that are attenuated by and output an ultra-wideband pulse from the output terminal. According to the present invention, since the side lobe of the ultra-wide-band pulse generated by the ultra-wide-band pulse generating device is suppressed so as not to exceed the FCC spectrum mask, it is possible to conform to the FCC spectrum mask.

Further, according to the present invention, since the center frequency of the ultra-wideband pulse spectrum can be changed simply by adjusting the combined impedance of the resistor, inductor, and capacitor constituting the oscillator, it is possible to easily generate a pulse of a desired shape.

In addition, according to the present invention, it is possible to easily perform impedance matching with an antenna through an oscillator even without a separate impedance matching circuit. In addition, the present invention not only does not require a separate balloon or impedance matching circuit, but also generates ultra-wideband pulses through digital pulses generated by a plurality of delay cells, so that low-power operation of the device is possible and can be implemented at low cost. Energy efficiency.

1 is a view for explaining the principle of generating an ultra-wideband pulse using an oscillator based on an LC tank.
2 is a view for explaining the output voltage generation principle of the RLC tank-based oscillator used in the present invention.
3 is a view showing a state in which a triangle envelope pulse is generated due to synthesis of an output voltage generated by the oscillator shown in FIG. 2.
4 is a view showing an ultra-wideband pulse generating apparatus according to an embodiment of the present invention.
5 is a view showing the internal structure of the delay cell shown in FIG.
FIG. 6 is a view showing a first delay cell among a plurality of delay cells shown in FIG. 4.
7 is a timing diagram for each zone of the delay cell shown in FIG. 6.
FIG. 8 is a view showing a second delay cell among the plurality of delay cells shown in FIG. 4.
9 is a timing diagram for each zone of the delay cell shown in FIG. 8.
10 is a timing diagram for each zone of the ultra-wideband pulse generator shown in FIG.
11 is a simulation result of ultra-wideband pulses generated through the apparatus shown in FIG.
12 is a simulation result of matching the device shown in FIG. 4 with the impedance of the antenna.
13 is a simulation result of the power spectrum density of the ultra-wideband pulse shown in FIG. 11.

Hereinafter, an ultra-wideband pulse generator according to the present invention will be described in detail with reference to the accompanying drawings. The accompanying drawings are provided by way of example only to ensure that the technical spirit of the present invention can be sufficiently transmitted to a person skilled in the art, and the present invention is not limited to the drawings presented below and can be embodied in any other form. have.

Before describing the apparatus for generating ultra-wideband pulses according to the present invention, the principle of generating the ultra-wideband pulse in the present invention will be described with reference to FIGS. 1 to 3.

Pulses in a multi-band IR-UWB system have a longer duration than pulses in a single-band system, and consist of a plurality of sinusoids. In a multi-band IR-UWB system, pulses are generated by adjusting the amplitude of the oscillator, which can have a pulse envelope in the form of a rectangle, triangular, sine, or the like. And the center frequency of the oscillator defines the center frequency of the pulse spectrum.

Depending on the shape of the pulse envelope, the pulse spectrum provides different sidelobe suppression functions. Here, the sidelobe suppression function means a difference between the main lobe and the sidelobe in the pulse spectrum. For example, a rectangular envelope pulse provides about 12.86 dB of sidelobe suppression, a triangular envelope pulse provides about 26.61 dB of sidelobe suppression, and a sine-shaped envelope pulse suppresses about 23 dB of sidelobe suppression. Function. The sidelobe suppression function is related to the frequency assigned by the Federal Communications Commission (FCC). That is, in order for the power spectrum density (PSD) of the pulse generated by the ultra-wideband pulse generator to conform to the FCC spectrum mask, the larger the sidelobe suppression function, the more advantageous.

In addition, generating a triangular envelope pulse may be advantageous in terms of power consumption or energy efficiency of the device, compared to generating a rectangular envelope pulse or a sinusoidal envelope pulse. Accordingly, hereinafter, a method of generating a triangle envelope pulse as illustrated in FIG. 1 will be described, but the method of generating a triangle envelope pulse also includes generating a rectangular, sine, or other shaped envelope pulse. Likewise, it can be applied.

1 is a view for explaining the principle of generating an ultra-wideband pulse using an oscillator based on an LC tank.

As shown in Fig. 1, a triangle envelope pulse can be generated by controlling the amount of oscillation amplitude of an oscillator based on an LC tank through a transconductor (Gm). In the present invention, the transconductor (Gm) may be formed of a plurality of transistors connected in parallel to each other, and each transistor has a transconductance that varies linearly.

A digital pulse of a square wave is input to an input terminal of the transconductor Gm, and the digital pulse of the square wave may be generated from cascade-coupled delay lines. Here, the delay line may be manufactured based on an inverter. And, by tuning the propagation delay of the delay line and the oscillation frequency of the LC tank, it is possible to generate an ultra-wideband pulse having a triangular envelope of a desired shape.

2 is a view for explaining the output voltage generation principle of the RLC tank-based oscillator used in the present invention.

The RLC tank-based oscillator shown on the left side of FIG. 2 is configured such that the resistor R _T , the inductor L _T and the capacitor C _T are connected in parallel with each other, and the parasitic resistance R _ser of the inductor is the inductor L _T. It is configured to be connected in series with. Here, the energy delivered to the RLC tank is in the form of a current I _inj depending on the switching frequency f _SWITCH of the switching voltage V _SWITCH .

In the graphs ① and ② shown on the right side of FIG. 2, the x-axis represents time and the y-axis represents voltage. Graph ① shows the switching voltage (V _SWITCH ) and graph ② shows the output voltage of the RLC tank-based oscillator.

When the current I _inj is transmitted to the RLC tank according to the switching voltage V _SWITCH of the square wave form, the natural response of the RLC tank can be expressed in the form of a second order differential equation as shown in Equation 1 below. have.

[Equation 1]

는 RLC 탱크 기반 발진기의 출력 전압이고,

이며,

이다. In Equation 1 above

Is the output voltage of the RLC tank based oscillator,

And

to be.

In addition, assuming that α<ω _o (ie, underdamped system) in Equation 1, the solution of Equation 1 may be expressed as Equation 2 below.

[Equation 2]

는 출력 전압의 위상을 나타낸다. 상기 수학식 2 및 그래프 ②에서 알 수 있듯이, RLC 탱크 기반 발진기의 출력 전압은 지수함수적으로 감쇠되는 정현파 형태를 갖는다.In Equation 2, V _p is the amplitude of the output voltage,

Denotes the phase of the output voltage. As can be seen from Equation 2 and graph ②, the output voltage of the RLC tank-based oscillator has a sinusoidal form that is exponentially attenuated.

3 is a view showing a state in which a triangle envelope pulse is generated due to synthesis of an output voltage generated by the oscillator shown in FIG. 2. In FIG. 3, the x-axis represents time and the y-axis represents voltage.

동안만 온(on) 상태이며, 도 3ⓒ는 도 3ⓐ에 나타낸 구형파 형태의 스위칭 전압(V_{SWITCH,1ST STAGE})에 따라 RLC 탱크 기반 발진기에 전류(I_inj,a)가 전달될 경우, RLC 탱크 기반 발진기의 출력 전압을 나타낸 것이다.The switching voltage (V _{SWITCH, 1ST STAGE} ) in the form of a square wave shown in FIG. 3ⓐ is time

It is ON only for a while, and Fig. 3ⓒ shows RLC when the current I _inj,a is transmitted to the RLC tank-based oscillator according to the square wave type switching voltage (V _{SWITCH, 1ST STAGE} ) shown in Fig. 3ⓐ. It shows the output voltage of a tank-based oscillator.

동안만 온(on) 상태이며, 다만 도 3ⓑ에 나타낸 구형파 형태의 스위칭 전압(V_{SWITCH,2nd STAGE})은 도 3ⓐ에 나타낸 구형파 형태의 스위칭 전압(V_{SWITCH,1ST STAGE})에 비해 2τ 만큼의 시간 딜레이가 존재한다. 그리고 도 3ⓓ는 도 3ⓑ에 나타낸 구형파 형태의 스위칭 전압(V_{SWITCH,2nd STAGE})에 따라 RLC 탱크 기반 발진기에 전류(I_inj,b)가 전달될 경우, RLC 탱크 기반 발진기의 출력 전압을 나타낸 것이다.The switching voltage (V _{SWITCH, 2nd STAGE} ) in the form of a square wave shown in FIG. 3ⓑ is also time

It is ON only for a while, but the switching voltage (V _{SWITCH, 2nd STAGE} ) in the form of a square wave shown in FIG. 3ⓑ is 2τ compared to the switching voltage (V _{SWITCH, 1ST STAGE} ) in the form of a square wave shown in FIG. There is a time delay. And FIG. 3ⓓ shows the output voltage of the RLC tank-based oscillator when the current (I _inj,b ) is transmitted to the RLC tank-based oscillator according to the square wave type switching voltage (V _{SWITCH, 2nd STAGE} ) shown in FIG. 3ⓑ. will be.

As can be seen in FIGS. 3ⓒ and 3ⓓ, the output voltages (V _{OUT, 1ST STAGE} , V _{OUT, 2ND STAGE} ) of the RLC tank-based oscillator have a sinusoidal form that is exponentially attenuated. However, since the switching voltage (V _{SWITCH,2nd STAGE} ) has a time delay of 2τ compared to the switching voltage (V _{SWITCH,1ST STAGE} ), the ON time of the output voltage (V _{OUT,2ND STAGE} ) is output There is a time delay of 2 tau compared to the on time of the voltage (V _{OUT, 1ST STAGE} ).

And the output voltage (V _{OUT,2ND STAGE} ) shown in FIG. 3ⓓ is larger in amplitude (V _p ) than the output voltage (V _{OUT,1ST STAGE} ) shown in FIG. 3ⓒ. This is because the current delivered to the RLC tank-based oscillator (I _inj,a ) in FIG. 3ⓒ is larger than the current delivered to the RLC tank-based oscillator (I _inj,b ) in FIG. 3ⓓ (ie, I _inj,a <I _inj,b ).

On the other hand, Figure 3ⓔ shows the output voltage (V _OUT,COMBINED ) of the output voltage (V _{OUT, 1ST STAGE} ) shown in Figure 3ⓒ and the output voltage (V _{OUT, 2ND STAGE} ) shown in Figure 3ⓓ. As shown in Fig. 3ⓔ, when combining the output voltage (V _{OUT, 1ST STAGE} ) shown in Fig. 3ⓒ and the output voltage (V _{OUT, 2ND STAGE} ) shown in Fig. 3ⓓ, a triangle envelope pulse can be generated. , The triangular envelope pulse generated as described above may provide a sidelobe suppression function of the pulse spectrum so as not to exceed the power spectrum density (PSD) of the FCC spectrum mask.

4 is a view showing an ultra-wideband pulse generating apparatus according to an embodiment of the present invention. As shown in FIG. 4, the ultra-wideband pulse generator according to an embodiment of the present invention includes a plurality of delay cells 100, a plurality of transistors 200, an oscillator 300, and an output terminal 400.

The plurality of delay cells 100 convert the input step voltage to a square wave voltage. Here, the delay cell 101 located at the leftmost of the plurality of delay cells 100 receives a step voltage from the outside, and the remaining delay cells 102-107 receive step voltages from neighboring delay cells 101-106. Receive input.

5 is a view showing the internal structure of the delay cell shown in FIG. 5 shows the delay cell 101 located at the leftmost of the plurality of delay cells 100, but other delay cells 102 to 107 may have the same internal structure.

Referring to FIG. 5, the delay cell 101 includes a first delay line 11, a second delay line 21 and an end gate 31. The first delay line 11 delays the input step voltage by time τ, for example, and outputs the second delay line 21 delays the voltage received from the first delay line 11 by time τ again. Output as V _out .

The AND gate 31 AND-operates the step voltage input to the first delay line 11 and the voltage input to the second delay line 21 and outputs it as V _SWITCH . And a first delay line 11 and the second delay line 21 is a time delay (time delay) of the respective tuning voltage V _TUNE and the receive input, the tuning voltage V _TUNE is each delay line (11, 21) It serves to tune.

The delay cell 100 delays the input step voltage by a predetermined time and outputs it as V _out , and also converts the step voltage to a square wave voltage and outputs it as a V _SWITCH . To this end, the delay line included in the delay cell 100 may be made based on an inverter.

FIG. 6 is a view showing a first delay cell among a plurality of delay cells shown in FIG. 4, and FIG. 7 is a timing diagram for each region of the delay cell shown in FIG. 6.

6, the delay lines 11 and 21 of the first delay cell 101 include the inverters 11-1 and 21-1, and the propagation delay of the inverters 11-1 and 21-1 In order to adjust (propagation delay), NMOS transistors 11-2 and 21-2 may be connected to inverters 11-1 and 21-1.

7( a) shows the step voltage input to the first delay line 11 of the first delay cell 101. When the step voltage as shown in Fig. 7(a) is input to the first delay line 11, the first inverter 11-1 of the first delay line 11 delays and inverts the step voltage by a time τ. The voltage waveform as shown in Fig. 7(a) ₁ is output.

Subsequently, when a voltage waveform as shown in FIG. 7(a) ₁ is input to the second delay line 21 of the first delay cell 101, the second inverter 21-1 of the second delay line 21 Delays and inverts the voltage waveform again by τ to output a voltage waveform as shown in FIG. 7(b)', that is, a step voltage delayed by 2τ compared to FIG. 7(a) as V _out . In addition, the step voltage V _out output from the first delay cell 101 is input to the second delay cell 102.

The AND gate 31 of the first delay cell 101 includes a step voltage (FIG. 7(a)) input to the first delay line 11 and a voltage input to the second delay line 21 (FIG. 7 ( a) AND operation is performed on ₁ ) to output a voltage waveform as shown in FIG. 7(b), that is, a square wave voltage having a duration of τ as V _SWITCH . Also, the square wave voltage V _SWITCH output from the first delay cell 101 is input to the gate electrode of the transistor 201 described later.

Although FIG. 6 shows that the first delay line 11 includes only one inverter 11-1 and the second delay line 21 also includes only one inverter 21-1, each delay line The number of inverters included in (11, 21) may be two or more. At this time, two or more inverters may be cascaded together. In addition, when two or more inverters are cascaded with each other, the on time of the step voltage V _out output from the first delay cell 101 is delayed more than 2τ, and the square wave voltage output from the first delay cell 101 The on time of V _SWITCH may also be delayed by the same time.

FIG. 8 is a view showing a second delay cell among the plurality of delay cells shown in FIG. 4, and FIG. 9 is a timing diagram for each region of the delay cell shown in FIG. 8.

8, the delay lines 12 and 22 of the second delay cell 102 include inverters 12-1 and 22-1, and propagation delay of the inverters 12-1 and 22-1 The NMOS transistors 12-2 and 22-2 may be connected to the inverters 12-1 and 22-1 to adjust.

9(b)' shows the step voltage input to the first delay line 12 of the second delay cell 102, which is the same as that shown in FIG. 7(b)'. When the step voltage as shown in FIG. 9(b)' is input to the first delay line 12, the first inverter 12-1 of the first delay line 12 delays and inverts the step voltage by a time τ. To output a voltage waveform as shown in Fig. 9(b)' ₁ .

Subsequently, when the voltage waveform as shown in FIG. 9(b)′ ₁ is input to the second delay line 22 of the second delay cell 102, the second inverter 22-1 of the second delay line 22 ) and outputs the step voltage delayed by 2τ relative to FIG. 9 (c), and the voltage waveform, that is, FIG. 9 (b), such as, by delaying and inverting again by τ the voltage waveform as V _out. In addition, the step voltage V _out output from the second delay cell 102 is input to the third delay cell 103.

The AND gate 32 of the second delay cell 102 includes a step voltage (FIG. 9(b)') input to the first delay line 12 and a voltage input to the second delay line 22 (FIG. 9). (b)' ₁ ) is AND-operated to output the voltage waveform as shown in FIG. 9(c), that is, the duration is τ, but the square wave voltage delayed by a time 2τ compared to the square wave voltage shown in FIG. 7(b) as V _SWITCH . In addition, the square wave voltage V _SWITCH output from the second delay cell 102 is input to the gate electrode of the transistor 202.

Although FIG. 8 shows that the first delay line 12 includes only one inverter 12-1 and the second delay line 22 also includes only one inverter 22-1, as in FIG. , The number of inverters included in each of the delay lines 12 and 22 may be two or more. At this time, two or more inverters may be cascaded together. When two or more inverters are cascaded together, the on-time of the step voltage V _out output from the second delay cell 102 is delayed more than 2τ, and the square wave voltage V output from the second delay cell 102 _SWITCH on time may also be delayed by the same time.

In addition, in the same manner as described above, the third delay cell 103 delays the step voltage received from the second delay cell 102 by a predetermined time (for example, 2τ) to the fourth delay cell 104. Output, and convert the step voltage received from the second delay cell 102 to a square wave voltage V _SWITCH and input it to the gate electrode of the transistor 203. That is, in the present invention, each of the delay cells 101 to 106 is configured to delay the input step voltage by a predetermined time (for example, 2τ) to output the delayed step voltage to neighboring delay cells 102 to 107. .

However, the seventh delay cell 107 located at the far right in FIG. 4 only converts the step voltage received from the sixth delay cell 106 to a square wave voltage V _SWITCH and inputs it to the gate electrode of the transistor 207. , The step voltage received from the sixth delay cell 106 is delayed by a predetermined time (for example, 2τ) and is not output to another delay cell. That is, in the present invention, each delay cell 102 to 107 receives the delayed step voltage from neighboring delay cells 101 to 106.

10 is a timing diagram for each zone of the ultra-wideband pulse generator shown in FIG. More specifically, FIG. 10(a) is a timing diagram of the step voltage input to the first delay cell 101, and FIGS. 10(b) to (h) are square waves output from each of the delay cells 101 to 107. It is a timing diagram of the voltage, and V _OUT in FIG. 10 is a timing diagram for a triangle envelope pulse output from the output terminal 400 described later.

10(b) to (h), the square wave voltage output from each delay cell 101 to 107 has a delay time of 2τ. Further, the square wave voltages shown in FIGS. 10(b) to 10(h) are individually applied to the plurality of transistors 200 (201 to 207).

The plurality of transistors 200 generate a current by using the square wave voltage converted by each of the plurality of delay cells 100 as an input voltage. Here, the plurality of transistors 200 may be connected so as to correspond 1:1 with the plurality of delay cells 100. Accordingly, the square wave voltage output from the first delay cell 101 may be input to the gate electrode of the first transistor 201. In addition, when the first transistor 201 receives the square wave voltage as described above, a channel is formed between the drain electrode and the source electrode of the first transistor 201 so that a current of a predetermined size can flow. Similarly, square wave voltages output from other delay cells 102 to 107 may be input to the gate electrodes of the transistors 202 to 207. In addition, when the transistors 202 to 207 receive the square wave voltage as described above, a channel is formed between the drain electrode and the source electrode of the transistors 202 to 207 to allow current to flow.

At this time, the magnitudes of the currents generated by each of the plurality of transistors 200 may all be different. For example, the transistor 204 disposed at the center among the plurality of transistors 200 generates the largest current, and the transistors 201, 202, 203, 205, 206, and 207 disposed at both sides based on the center. May generate a current having a linearly reduced size from the center to the two sides. This is to generate a triangular envelope pulse by adjusting the amplitude of the oscillator 300 by supplying a current of a different size to the oscillator 300 at a time interval of 2τ as shown in FIGS. 10(b) to (h). It is for sake.

Here, it is preferable to increase the size of the transistor 204 in order for the transistor 204 disposed at the center of the plurality of transistors 200 to generate the largest current. And the transistors 201, 202, 203, 205, 206, and 207 disposed on both sides with respect to the center linearly decrease the size of the transistor as it goes from the center to both sides. It is desirable to allow the current to be reduced in size.

More specifically, as one of the schemes for the transistor 204 disposed at the center of the plurality of transistors 200 to generate the largest current, the channel width W compared to the channel length L of the transistor 204 is determined. Other transistors 201, 202, 203, 205, 206, and 207 may have a larger channel width (L) compared to the channel length (L). That is, the W/L of the transistor 204 disposed at the center can be made larger than the W/L of the other transistors 201, 202, 203, 205, 206, and 207. In this case, the transistors 201, 202, 203, 205, 206, and 207 disposed on both sides of the center relative to the channel length (L) of the transistor as it goes from the center to both sides linearly By reducing, it is possible to generate a current having a linearly reduced magnitude from the center to the two sides.

In addition, the channel length (L) can be made the same in all the transistors 200, so in this case, the magnitude of the current generated in each transistor 200 is approximately proportional to the channel width (W) of the transistor 200 Is decided. For example, when the channel length L of all the transistors 200 is the same, and the nominal size of the transistor width is 12 μm, the size of the fourth transistor 204 disposed centrally in FIG. 4 is nominal. It is configured to be 3.5 times the size, and the third transistor 203 and the fifth transistor 205 disposed on both sides may be configured to be 2.5 times the nominal size. In addition, the second transistor 202 and the sixth transistor 206 are configured to be 1.5 times the nominal size, and the sizes of the first transistor 201 and the seventh transistor 207 disposed at the outermost are 0.5 times the nominal size. can do. When the size of the plurality of transistors 200 is configured to decrease linearly from the center to both sides, the pulse spectrum of the triangle envelope pulse output from the output terminal 400 can provide an improved sidelobe suppression function.

However, in the case of generating a triangular envelope pulse, it is preferable to configure the sizes of the plurality of transistors 200 to decrease linearly from the center to both sides. No, the size of the plurality of transistors 200 may be variously configured.

On the other hand, when generating a sinusoidal envelope pulse, the magnitude of the current generated in each of the plurality of transistors 200 may be configured differently from the case of generating the triangle envelope pulse. Therefore, in this case, it is required to determine the size of each of the plurality of transistors 200 unlike that shown in FIG. 4. In addition, when generating a rectangular envelope pulse, it is possible to make all of the magnitudes of the currents generated in each of the plurality of transistors 200 the same. Therefore, in this case, the sizes of the plurality of transistors 200 may all be the same.

The oscillator 300 may be configured based on an RLC tank in which a resistor R _T , an inductor L _T , and a capacitor C _T are connected to each other in parallel, as described above with reference to FIG. 2, and the resistor R _T , The inductor L _T and the capacitor C _T may operate by the operating voltage of the operating voltage source V _DD of the oscillator 300.

The oscillator 300 receives a current generated by each of the plurality of transistors 200 to generate a plurality of sinusoidal voltages that are exponentially attenuated. Specifically, in the time interval of 0 to 2τ shown in FIG. 10, a current corresponding to 0.5 times the nominal size of the transistor is transmitted to the oscillator 300, and the amplitude of the output voltage of the oscillator 300 is adjusted as shown in FIG. In the time period of ˜4τ, a current corresponding to 1.5 times the nominal size of the transistor is transmitted to the oscillator 300, so that the amplitude of the output voltage of the oscillator 300 can be adjusted as shown in FIG. In addition, the amplitude of the output voltage of the oscillator 300 can be adjusted in a time period of 0 to 14τ in this manner.

The output terminal 400 is connected to the plurality of transistors 200 and the oscillator 300. Accordingly, the output terminal 400 synthesizes a plurality of sinusoidal voltages generated by the oscillator 300 to output a triangle envelope pulse. do. The envelope pulse of the triangle output from the output terminal 400 has the form of V _OUT shown in FIG. 10.

Meanwhile, a bypass capacitor C _BYPASS may be connected to the output terminal 400 to remove the DC component from the triangle envelope pulse. More specifically, the bypass capacitor C _BYPASS may be connected between the oscillator 300 and the output terminal 400, and due to the passage characteristic of the high frequency band, it performs a blocking function of not only the DC component but also the low frequency component in the triangle envelope pulse. can do.

Meanwhile, a triangle envelope pulse output from the output terminal 400 is transmitted through an antenna. At this time, when the impedance of the antenna is, for example, 50Ω, the combined impedance of the resistor (R _T ), the inductor (L _T ), and the capacitor (C _T ) constituting the oscillator 300 is also matched to 50 Ω, so that the antenna transmits efficiency. Can be maximized.

11 is a simulation result of ultra-wideband pulses generated through the apparatus shown in FIG. The simulation result of FIG. 11 was performed at an operating voltage (V _DD ) of 900 mV, and the peak-to-peak voltage V _pp of the ultra-wideband pulse was measured to be 577 mV, and the amplitude of the ultra-wideband pulse was It decreased linearly toward both sides with respect to the center. And the effective pulse width t _pulse of the ultra-wideband pulse was measured to be 1.6 ns.

12 is a simulation result of matching the device shown in FIG. 4 with the impedance of the antenna. The synthesized impedance of the resistor (R _T ), the inductor (L _T ) and the capacitor (C _T ) constituting the oscillator 300 was adjusted to match the antenna impedance to 50 Ω, and the synthesized impedance was adjusted to control the pulse spectrum. Impedance matching is performed with the antenna at the point where the center frequency of is 4 GHz. That is, the center frequency of the ultra-wideband pulse spectrum can be varied only by adjusting the combined impedance of the resistor (R _T ), the inductor (L _T ), and the capacitor (C _T ) constituting the oscillator 300, and accordingly It is possible to easily generate a pulse of a desired shape. In addition, even if a separate impedance matching circuit is not provided, impedance matching with the antenna may be easily performed through the oscillator 300.

Meanwhile, FIG. 13 is a simulation result of the power spectrum density of the ultra-wideband pulse shown in FIG. 11. As shown in FIG. 13, the center frequency of the main lobe is 4 GHz, and the power level at this time is -60.39 dBm. And the center frequency of the first side lobe was 3.1 GHz, and the power level at this time was -81.8 dBm. The dotted line shown in FIG. 13 shows the FCC spectrum mask, and the power spectrum density of the ultra-wideband pulse should not exceed the FCC spectrum mask. According to FIG. 13, it can be seen that the power spectrum density of the ultra-wideband pulse generated in FIG. 11 conforms to the FCC spectrum mask, and in particular, it is found that the sidelobe is properly suppressed so as not to exceed the FCC spectrum mask.

As described above, although the present invention has been described by limited embodiments and drawings, the present invention is not limited to the above embodiments, and various modifications and variations from these descriptions are made by those skilled in the art to which the present invention pertains. It is possible. Therefore, the technical idea of the present invention should be understood only by the claims, and all equivalent or equivalent modifications thereof will be said to fall within the scope of the technical idea of the present invention.

11, 12: first delay cell
11-1, 21-1: Inverter
11-2, 21-2: NMOS transistor
21, 22: second delay cell
31, 32: and gate
100 (101, 102, 103, 104, 105, 106, 107): delay cell
200 (201, 202, 203, 204, 205, 206, 207): transistor
300: oscillator
400: output stage

Claims (8)

A plurality of delay cells that convert the input step voltage to a square wave voltage;
A plurality of transistors generating a current by using the square wave voltage converted by each of the plurality of delay cells as an input voltage;
An oscillator that receives a current generated by each of the plurality of transistors and generates a plurality of sinusoidal voltages that are exponentially attenuated; And
It includes; and an output terminal that is connected to the plurality of transistors and the oscillator and outputs an ultra-wideband pulse by synthesizing a plurality of sinusoidal voltages generated by the oscillator.
Each of the plurality of delay cells delays the step voltage by a predetermined time to output a delayed step voltage to a neighboring delay cell,
Each of the plurality of delay cells receives the delayed step voltage from a neighboring delay cell,
Each of the plurality of delay cells delays the step voltage by a predetermined time using an inverter,
Each of the plurality of delay cells is an ultra-wideband pulse generator, characterized in that for converting the step voltage to the square wave voltage using the inverter and the end gate.
delete delete delete According to claim 1,
The plurality of transistors are connected to the plurality of delay cells 1:1, characterized in that the ultra-wideband pulse generator.
The method of claim 5,
The shape of the ultra-wideband pulse output from the output terminal varies depending on the magnitude of the current generated in each of the plurality of transistors.
According to claim 1,
The oscillator is an ultra-wideband pulse generator comprising a resistor, an inductor and a capacitor connected in parallel to each other.
According to claim 1,
A device for generating an ultra-wideband pulse, wherein a bypass capacitor is connected to the output terminal to remove a DC component from the ultra-wideband pulse.

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