KR101922937B1 - Thin film transistor array substrate and method for fabricating the same - Google Patents

Abstract

The present invention provides a semiconductor device comprising a base layer; An oxide semiconductor pattern disposed on the base layer, the oxide semiconductor pattern having a channel region and source and drain regions disposed on both sides of the channel region, respectively; A gate insulating pattern exposing both the source and drain regions and disposed at a position corresponding to the channel region of the oxide semiconductor pattern; A gate electrode disposed only at a position corresponding to the gate insulating pattern; A protective layer disposed on the base layer including the gate electrode and having first and second contact holes exposing the source and drain regions of the oxide semiconductor pattern, respectively; A source electrode disposed on the protection layer and in contact with the source region through the first contact hole; A drain electrode disposed on the protection layer and in contact with the drain region through the second contact hole; And a pixel electrode disposed on the passivation layer and formed by extending a part of the drain electrode, and a method of manufacturing the thin film transistor substrate.

Description

[0001] The present invention relates to a thin film transistor substrate and a manufacturing method thereof,

The present invention relates to a thin film transistor substrate and a method of manufacturing the same, and is a thin film transistor substrate of a coplanar structure having an oxide semiconductor pattern and a method of manufacturing the same.

2. Description of the Related Art In recent years, the importance of flat panel displays (FPDs) has been increasing with the development of multimedia. Examples of the flat panel display device include a liquid crystal display device, an electronic paper, and an organic light emitting display device.

A passive matrix method and an active matrix method using a thin film transistor are used for driving the flat panel display device. In the passive matrix method, an anode and a cathode are formed so as to be orthogonal to each other and a line is selected and driven. In the active matrix method, a thin film transistor is connected to each pixel electrode and driven according to a voltage maintained by a capacitor capacitance connected to a gate electrode of the thin film transistor .

In particular, among the flat panel display devices, the organic light emitting display device includes a switching thin film transistor and a driving thin film transistor in one pixel. Further, the organic light emitting display device may further include a compensation circuit including a thin film transistor for a minute current value correction.

Such a thin film transistor is mainly formed of a coplanar structure in which a gate electrode is disposed on a semiconductor layer. This is because the coplanar structure of the thin film transistor can reduce the signal delay due to the parasitic capacitance of the thin film transistor itself as compared with other thin film transistors.

On the other hand, the semiconductor layer of the thin film transistor has been mainly formed of amorphous silicon or polycrystalline silicon. However, amorphous silicon is advantageous in that the film forming process is simple and the production cost is low, but there is a problem that electrical reliability can not be secured. In addition, due to the high process temperature, polycrystalline silicon is very difficult to apply in a large area, and uniformity due to the crystallization method can not be secured. As a result, an oxide semiconductor layer capable of achieving high mobility even at low temperature and capable of large area application has been developed.

However, since an array substrate having a thin film transistor having a nose platter structure having an oxide semiconductor layer has to be formed through at least seven mask processes, there is a problem that the number of processes increases as compared with an array substrate having thin film transistors having other structures.

The present invention provides a thin film transistor substrate having a coplanar structure having an oxide semiconductor layer capable of reducing the number of process steps and a method of manufacturing the thin film transistor substrate, There is a purpose.

A thin film transistor substrate of a solution according to the present invention is provided. A thin film transistor substrate according to the present invention includes a base layer; An oxide semiconductor pattern disposed on the base layer, the oxide semiconductor pattern having a channel region and source and drain regions disposed on both sides of the channel region, respectively; A gate insulating pattern exposing both the source and drain regions and disposed at a position corresponding to the channel region of the oxide semiconductor pattern; A gate electrode disposed only at a position corresponding to the gate insulating pattern; A protective layer disposed on the base layer including the gate electrode and having first and second contact holes exposing the source and drain regions of the oxide semiconductor pattern, respectively; A source electrode disposed on the protection layer and in contact with the source region through the first contact hole; A drain electrode disposed on the protection layer and contacting the drain region through the second contact hole; And a pixel electrode disposed on the passivation layer and formed by extending a part of the drain electrode.

Another method of manufacturing a thin film transistor substrate according to the present invention is provided. A manufacturing method according to the present invention includes: providing a base layer; Forming an oxide semiconductor pattern, a gate insulating pattern, and a gate electrode on the base layer using one mask; Forming a protective layer on the base layer including the gate electrode and having first and second contact holes exposing source and drain regions of the oxide semiconductor pattern, respectively; And forming a source electrode and a drain electrode, which are disposed on the protective layer and contact the source and drain regions of the oxide semiconductor pattern through the first and second contact holes, respectively, and a pixel electrode electrically connected to the drain electrode, . ≪ / RTI >

The thin film transistor substrate according to the embodiment of the present invention can reduce the number of mask processes compared to the conventional one by forming the semiconductor pattern and the gate electrode using one mask.

In addition, the thin film transistor substrate according to the embodiment of the present invention can eliminate the misalignment problem between the channel region of the semiconductor pattern and the gate electrode by forming the semiconductor pattern and the gate electrode using the same mask.

In addition, since the semiconductor pattern and the gate electrode are formed using the same mask, the thin film transistor substrate according to the embodiment of the present invention can be easily manufactured due to self-alignment between the channel region of the semiconductor pattern and the gate electrode .

In addition, since the source and drain electrodes and the pixel electrode are formed using a single mask, the number of mask processes can be reduced compared with the conventional one.

In addition, the thin film transistor substrate according to the embodiment of the present invention can increase the contact stability between the semiconductor pattern and the drain electrode by forming a semiconductor with oxide and directly contacting the drain electrode formed of the conductive oxide with the oxide semiconductor pattern , Reliability of the thin film transistor can be improved.

1 is a circuit diagram of one pixel region of an organic light emitting display according to a first embodiment of the present invention.
2 is a cross-sectional view of a thin film transistor substrate according to a first embodiment of the present invention.
FIGS. 3 to 9 are cross-sectional views illustrating a manufacturing process of a thin film transistor substrate according to a second embodiment of the present invention.

Embodiments of the present invention will be described in detail with reference to the drawings of thin film transistors. The following embodiments are provided by way of example so that those skilled in the art can fully understand the spirit of the present invention.

Therefore, the present invention is not limited to the embodiments described below, but may be embodied in other forms. In the drawings, the size and thickness of an apparatus may be exaggerated for convenience. Like reference numerals designate like elements throughout the specification.

1 is a circuit diagram of one pixel region of an organic light emitting display according to a first embodiment of the present invention.

Referring to FIG. 1, the organic light emitting display according to the first embodiment of the present invention may define one pixel region P by a gate line GL and a data line DL intersecting with each other. Further, a power supply line PL disposed in parallel with the data line DL may be further disposed. Here, the power supply line PL may serve to apply power to the organic light emitting diode E, which will be described later.

A switching thin film transistor STr, a driving thin film transistor DTr, a storage capacitor StgC, and an organic light emitting diode E may be disposed in each pixel region P.

Here, the switching thin film transistor STr and the driving thin film transistor DTr may include a gate electrode, a semiconductor pattern, and a source and a drain electrode, respectively.

At this time, the gate electrode of the switching thin film transistor STr is electrically connected to the gate line GL, and the source electrode of the switching thin film transistor STr may be electrically connected to the data line DL. The drain electrode of the switching thin film transistor STr may be electrically connected to the gate electrode of the driving thin film transistor DTr.

Here, the source electrode of the driving thin film transistor DTr may be electrically connected to the power supply line PL. In addition, the drain electrode of the driving thin film transistor DTr may be electrically connected to the organic light emitting diode E.

Here, the organic electroluminescent diode E may include an organic light emitting layer interposed between the first and second electrodes and the first and second electrodes. Here, the recombination of the first and second charges provided in each of the first and second electrodes in the organic light emitting layer is performed, and the recombined first and second charges are transited from the excited state to the ground state to generate and emit light.

At this time, the drain electrode of the driving thin film transistor DTr may be electrically connected to the first electrode of the organic light emitting diode E. At this time, the power supply line PL may be electrically connected to the second electrode of the organic light emitting diode element E.

Further, the storage capacitor StgC may be formed between the gate electrode and the source electrode of the driving thin film transistor DTr.

Accordingly, when a gate signal is applied through the gate line GL, the switching thin film transistor STr is turned on and the data signal of the data line DL is transmitted to the gate electrode of the driving thin film transistor DTr. At this time, since the driving thin film transistor DTr is turned on by the data signal, light can be output through the organic light emitting diode E. At this time, when the driving thin film transistor DTr is turned on, the level of the current flowing from the power supply line PL to the organic electroluminescent diode E is determined, A gray scale can be realized. At this time, the storage capacitor StgC maintains the gate voltage of the driving thin film transistor DTr constant when the switching thin film transistor STr is turned off, so that the switching thin film transistor STr is turned off the level of the current flowing through the organic electroluminescent diode E can be maintained constant until the next frame even if the off state is established.

Hereinafter, the thin film transistor substrate provided in the organic light emitting display will be described in more detail with reference to FIG. Here, the switching thin film transistor has the same configuration as that of the driving thin film transistor and will be omitted here.

2 is a cross-sectional view of a thin film transistor substrate corresponding to one pixel region in FIG.

2, the thin film transistor substrate includes an oxide semiconductor pattern 131 disposed on the base layer 100, a gate insulating pattern 141 disposed on the oxide semiconductor pattern 131, A protective layer 160 disposed on the base layer 100 including the gate electrode 151 and source and drain electrodes SE and DE disposed on the protective layer 160, And a thin film transistor including the thin film transistor.

Specifically, examples of the material constituting the base layer 100 may be glass, metal, or plastic. The base layer 100 can be a flat substrate or a flexible film that can be warped by force.

The oxide semiconductor pattern 131 may be an oxide semiconductor material including indium, zinc, gallium, and hafnium. For example, the oxide semiconductor pattern may be formed of any one of IGZO, ZnO, InZnO, InGaZnO4, CdO, GaO, InO, InO, and SnO.

The oxide semiconductor pattern 131 may include source and drain regions 131b and 131c disposed on both sides of the channel region 131a and the channel region 131a.

The gate insulating pattern 141 may be disposed on the oxide semiconductor pattern 131. Here, the gate insulating pattern 141 may be disposed on the oxide semiconductor pattern 131 at a position corresponding to the channel region. Accordingly, the gate insulating pattern 141 can be formed to expose both the source and drain regions. The gate electrode 151 may be disposed only at a position corresponding to the gate insulating pattern 141. [ In other words, the gate electrode 151 may be disposed on the gate insulating pattern 141. This is because the gate insulating pattern 141 and the gate electrode 151 are formed through an etching process using a single mask, so that they can have the same pattern structure.

The protective layer 160 may be disposed on the base layer 100 including the gate electrode 151. Here, the passivation layer 160 may have first and second contact holes 161 and 162, respectively, which expose the source and drain regions of the oxide semiconductor pattern 131, respectively.

The source electrode SE may be disposed on the protection layer 160 and may contact the source region through the first contact hole 161. [ Here, the source electrode SE is formed of a first transparent conductive oxide pattern 171 that directly contacts the source region 131b and a first metal pattern 181 that is disposed on the first transparent conductive oxide pattern 171 . At this time, the first transparent conductive oxide pattern 171 may be ITO or IZO. Here, since the oxide semiconductor pattern 131 of the source region and the first transparent conductive oxide pattern 171 are formed in the oxide series, the contact reliability between the oxide semiconductor pattern 131 and the source electrode SE can be improved.

The drain electrode DE may be disposed on the protection layer 160 and may contact the drain region 131c through the second contact hole 162. [ Here, the drain electrode DE is formed of a second transparent conductive oxide pattern 172 directly contacting the drain region 131c and a second metal pattern 182 disposed on the second transparent conductive oxide pattern 172 . At this time, the second transparent conductive oxide pattern 172 may be ITO or IZO. Since the oxide semiconductor pattern 131 and the second transparent conductive oxide pattern 172 of the drain region 131c are formed in oxide series, the contact reliability between the oxide semiconductor pattern 131 and the drain electrode DE can be improved .

The pixel electrode 173 may be formed by extending a part of the drain electrode DE. At this time, the pixel electrode 173 may be formed by extending the second transparent conductive oxide pattern 172 of the drain electrode DE. That is, the pixel electrode 173 and the second transparent conductive oxide pattern 172 of the drain electrode DE may be formed integrally. Accordingly, the pixel electrode 173 may be formed of the same material as the first and second transparent conductive oxide patterns 171 and 172 of the source and drain electrodes SE and DE, respectively.

The pixel electrode 173 is formed by extending a part of the drain electrode DE and the second transparent conductive oxide pattern 172 of the drain electrode DE is directly connected to the oxide semiconductor pattern 131, 173, the drain electrode DE, and the oxide semiconductor pattern 131 can be improved.

In addition, storage electrodes may be further disposed in each pixel region. Here, the storage electrode may include first and second storage electrodes 152, 174 and 183 stacked with an insulating layer, for example, a protective layer 160 interposed therebetween. Specifically, the first storage electrode 152 may be formed of the same material as the gate electrode 151. Here, the first storage electrode 152 may be formed by extending a part of the gate electrode 151. At this time, the first story electrode 152 may be formed in the process of forming the gate electrode 151. Accordingly, the first dummy gate insulating pattern 142 and the first dummy oxide semiconductor pattern 132 may be disposed under the first storage electrode 152.

The second storage electrodes 174 and 183 are disposed on the protective layer 160. The second storage electrodes 174 and 183 may be formed as an extension of the drain electrode DE of the thin film transistor. That is, the second storage electrodes 174 and 183 may be formed of a third transparent conductive oxide pattern 174 and a third metal pattern 183 disposed on the third transparent conductive oxide pattern 174.

In addition, although not shown in the drawings, a plurality of wirings may be disposed on the thin film transistor substrate. For example, the plurality of wirings may be arranged crossing each other to include a gate wiring and a data wiring which define a pixel region, and a power wiring parallel to the data wiring.

Here, the gate wiring may be formed in the step of forming the gate electrode 151. [ Accordingly, a dummy gate insulating pattern of the same material as the gate insulating pattern 141 and a dummy oxide semiconductor pattern of the same material as the oxide semiconductor pattern 131 of the channel region 131a may be further disposed under the gate wiring. Here, the gate wiring may be electrically connected to the gate electrode of the switching thin film transistor. Here, the gate wiring and the gate electrode of the switching thin film transistor may be integrally formed.

A gate lower pad 153 may be further disposed at one end of the gate wiring. Here, the gate wiring and the gate lower pad 153 may be integrally formed. A second dummy gate insulating pattern 143 formed of the same material as the dummy gate insulating pattern and a second dummy oxide semiconductor pattern 133 formed of the same material as the dummy oxide semiconductor pattern are formed under the gate lower pad 153 Can be further disposed.

A gate top pad 175 may be disposed on the gate bottom pad 153. Here, the gate upper pad 175 may be made of the same material as the pixel electrode, and may have corrosion resistance against oxygen or moisture.

The data lines can be formed in the process of forming the source and drain electrodes SE and DE. Accordingly, the data wiring can be formed of a metal pattern disposed on the transparent conductive oxide pattern and the transparent conductive oxide pattern, such as the source and drain electrodes SE and DE.

A data pad 176 may be disposed at one end of the data line. Here, the data pad 176 may be formed as a part of the data line. At this time, the data pad 176 may be formed of a transparent conductive oxide pattern of the data line. That is, the data pad 176 may be made of the same material as the pixel electrode. Accordingly, the data pad 176 may be formed of a material having corrosion resistance against external oxygen or moisture.

In addition, the shield pattern 110 is disposed under the oxide semiconductor pattern 131, that is, on the base layer 100. The shield pattern 110 serves to shield light incident on the oxide semiconductor pattern 131. As an example of the material for forming the shield pattern 110, metal, for example, molybdenum may be used. However, the material of the shield pattern 110 is not limited to the embodiment of the present invention. For example, aluminum and chromium may be used .

The buffer layer 120 may further intervene between the shield pattern 110 and the oxide semiconductor pattern 131 to insulate the shield pattern 110 from the oxide semiconductor pattern 131. In addition, the buffer layer 120 can prevent impurities from being injected into the oxide semiconductor pattern 131 from the base layer 100.

In addition, the bank layer 190 may be further disposed on the passivation layer 160 including the pixel electrode 173. Here, the bank layer 190 may have an opening exposing a part of the pixel electrode 173. At this time, the bank layer 190 is covered along the edge of the pixel electrode 173. The bank layer 190 may also have first and second openings 191 and 192 exposing the gate top pad 175 and the data pad 176, respectively.

The bank layer 190 may serve to planarize the surface of the thin film transistor substrate. Alternatively, the bank layer 190 may prevent the ink solution for forming the organic light emitting layer from overflowing to another pixel region in the inkjet printing process for forming the organic light emitting layer of the organic light emitting display device.

In the embodiments of the present invention, the thin film transistor substrate is described as an organic light emitting display device among the flat panel display devices, but the present invention is not limited thereto. For example, the thin film transistor substrate can be applied to a liquid crystal display or an electronic paper. At this time, the thin film transistor substrate may include a switching thin film transistor and a storage capacitor in a pixel region.

The thin film transistor substrate according to the embodiment of the present invention can increase the contact stability between the semiconductor pattern and the drain electrode by forming a semiconductor with an oxide and directly contacting the drain electrode formed of the conductive oxide with the oxide semiconductor pattern, The reliability of the transistor can be improved.

Hereinafter, a method for fabricating a thin film transistor substrate according to an embodiment of the present invention will be described in detail with reference to FIGS. 3 to 9. FIG. Here, the manufacturing process of the thin film transistor substrate according to the first embodiment described above will be described, and the first embodiment and the repeated description will be omitted.

FIGS. 3 to 9 are cross-sectional views illustrating a manufacturing process of a thin film transistor substrate according to a second embodiment of the present invention.

Referring to FIG. 3, a base layer 100 is first provided to fabricate a thin film transistor substrate.

Here, the shield pattern 110 may be further disposed on the base layer 100. At this time, the shield pattern 110 may be formed on a region corresponding to the oxide semiconductor pattern 131 to be formed in a subsequent process. The shield pattern 110 may be formed by depositing a metal, for example, molybdenum on the base layer 100, and then patterning the deposited metal.

Referring to FIG. 4, a buffer layer 120 may be further disposed on the base layer 100 including the shield pattern 110. Here, examples of the material for forming the buffer layer 120 may be silicon oxide, but the present invention is not limited thereto. The buffer layer 120 may be formed by chemical vapor deposition.

An oxide semiconductor layer 130, a gate insulating layer 140, and a first metal layer 150 are sequentially formed on the base layer 100. Here, the oxide semiconductor layer 130 may include any one of indium, zinc, gallium, and hafnium. For example, the oxide semiconductor layer 130 may be formed of any one of IGZO, ZnO, InZnO, InGaZnO4, CdO, GaO, InO, InO, and SnO. Examples of the method for forming the oxide semiconductor layer 130 include a sputtering method, a chemical vapor deposition method, a coating method, and an atomic layer deposition method.

The gate insulating layer 140 may be formed of silicon oxide, but the present invention is not limited thereto. The gate insulating layer 140 may be formed by chemical vapor deposition.

The first metal layer 150 may be formed by a sputtering method. Examples of the material for forming the first metal layer 150 include molybdenum, aluminum, titanium, chromium, copper, and the like, but the present invention is not limited thereto.

 Thereafter, a photoresist layer is formed on the first metal layer 150, and then a first photoresist pattern P1 having steps is formed through an exposure process and a development process using a mask. Here, the first photoresist pattern P1 may be formed using a halftone mask or a diffraction mask.

5, the first metal layer 150, the gate insulating layer 140, and the oxide semiconductor layer 130 are patterned using the first photoresist pattern P1 as an etch mask to form a preliminary gate pattern, A preliminary gate insulating pattern and an oxide semiconductor pattern 131 may be formed. Since the first metal layer 150, the gate insulating layer 140 and the oxide semiconductor layer 130 use the first photoresist pattern P1 as an etch mask, the oxide semiconductor layer 130 is formed under the preliminary gate pattern and the preliminary gate insulating pattern. Part of the layer may remain.

In addition, by etching the first metal layer 150 using the first photoresist pattern P1 as an etch mask, the first storage electrode 152, the gate wiring, the gate lower pad 153 ) Can be further formed. At this time, the gate insulating layer 140 and the oxide semiconductor layer 130 may also be etched by etching the first metal layer 150. Accordingly, a portion of the gate insulating layer 140 and the oxide semiconductor layer 130 may be left under the first storage electrode 152, the gate wiring, and the gate lower pad 153, respectively. That is, a first dummy gate insulating pattern 142 and a first dummy oxide semiconductor pattern 132 are formed under the first storage electrode 152. Further, a dummy gate insulating pattern and a dummy oxide semiconductor pattern are formed under the gate wiring. A second dummy gate insulating pattern 143 and a second dummy oxide semiconductor pattern 133 are formed under the gate lower pad 153.

Then, an ashing process is performed on the first photoresist pattern P1 to remove the step of the first photoresist pattern P1. 5, the gate electrode 151 may be formed by etching the preliminary gate pattern and the preliminary gate insulation pattern using the first photoresist pattern from which the step is removed as an etching mask. At this time, since the preliminary gate pattern and the preliminary gate insulation pattern are etched using the first photoresist pattern with the step removed as the same etching mask, the gate insulation pattern 141 may be disposed under the gate electrode 151.

The gate insulating pattern 141 may be formed through a dry etching process of a preliminary gate insulating pattern. Here, the plasma used for etching the preliminary gate insulating pattern can be irradiated onto the oxide semiconductor pattern 131. [ At this time, the plasma may be irradiated onto the oxide semiconductor pattern 131 exposed to the gate electrode 151. Here, the plasma can reduce the content of oxygen contained in the oxide semiconductor pattern 131. Thus, the region where the plasma is not irradiated, that is, the region irradiated with plasma as compared with the channel region 131a, that is, the source and drain regions 131b and 131c, can have a conductor characteristic. That is, the source and drain regions 131b and 131c of the oxide semiconductor pattern 131 may be formed through a dry etching process of a preliminary gate insulating pattern. At this time, a channel region may be formed in the oxide semiconductor pattern 131 in the region corresponding to the gate electrode 151.

In the embodiment of the present invention, since the gate electrode 151 and the oxide semiconductor pattern 131 are formed by using the same mask, when the oxide semiconductor pattern and the gate electrode are formed using different masks, The problem of misalignment between the channel region 131a of the oxide semiconductor pattern 131 and the gate electrode 151 can be solved.

In addition, the source and drain regions 131b and 131c of the oxide semiconductor pattern 131 can be formed by dry etching for etching the preliminary gate insulating pattern, and an oxide semiconductor pattern (for example, 131 is not required to proceed, so that the process can be further simplified.

Thereafter, the first photoresist pattern from which the step is removed is completely removed.

6, a protective layer 160 is formed on the base layer 100 including the gate electrode 151, the gate wiring, the gate lower pad 153, and the first storage electrode 152. Referring to FIG. Here, an example of the material forming the protective layer 160 may be silicon oxide. Here, the protective layer 160 may be formed by chemical vapor deposition. The first and second contact holes 161 and 162 exposing the source and drain regions 131b and 131c of the oxide semiconductor pattern 131 are formed through a selective etching process of the passivation layer 160. [ At this time, the protective layer 160 may further include a third contact hole 163 exposing the gate lower pad 153.

The selective etching of the passivation layer 160 may be performed by forming a photoresist pattern on the passivation layer 160 and then dry-etching the passivation layer 160 using the photoresist pattern as an etching mask.

Referring to FIG. 7, a transparent conductive oxide layer 170 and a second metal layer 180 are sequentially formed on the passivation layer 160 after the passivation layer 160 is formed. Here, the transparent conductive oxide layer 170 may be ITO or IZO. In addition, examples of the material for forming the second metal layer 180 may be molybdenum, aluminum, titanium, chromium, copper, and the like, but the present invention is not limited thereto.

Thereafter, a second photoresist pattern P2 having a step on the second metal layer 180 is formed. Here, the second photoresist pattern P2 may be formed using a halftone mask or a diffraction mask. Thereafter, the transparent conductive oxide layer 170 and the second metal layer 180 are etched using the second photoresist pattern P2 as an etch mask to form source and drain electrodes SE and DE, 2 storage electrodes 174 and 183 can be formed. Further, in the step of etching the transparent conductive oxide layer 170 and the second metal layer 180, a spare pixel electrode, a spare gate upper pad, and a spare data pad may be further formed.

Since the source and drain electrodes SE and DE are formed by etching the transparent conductive oxide layer 170 and the second metal layer 180, the source and drain electrodes SE and DE are formed by the transparent conductive oxide pattern 171 , 172 and the metal patterns 181, The transparent conductive oxide patterns 171 and 172 of the source and drain electrodes SE and DE can be in direct contact with the source and drain regions 131b and 131c of the oxide semiconductor pattern 131, ) And the source and drain electrodes SE and DE can be improved.

Further, since the preliminary pixel electrode, the preliminary gate upper pad, and the preliminary data pad are formed by etching the transparent conductive oxide layer 170 and the second metal layer 180, the preliminary pixel electrode, the preliminary gate upper pad, And may have a laminated structure of a conductive oxide pattern and a metal pattern.

Thereafter, the step of the second photoresist pattern is removed through the ashing process. Thereafter, the metal pattern of the preliminary pixel electrode is removed using the second photoresist pattern from which the step is removed as an etching mask, so that the pixel electrode 173 can be formed as shown in FIG. At this time, the metal pattern of the spare gate upper pad and the spare data pad may be removed to form the gate upper pad 175 and the data pad 176. That is, the gate upper pad 175 and the data pad 176 may be formed of a transparent conductive oxide having the same material as that of the pixel electrode 173. At this time, the dummy first and second metal patterns 184 and 185 may be formed by leaving the metal pattern along the upper edges of the gate upper pad 175 and the data pad 176, respectively. Here, the dummy first and second metal patterns 184 and 185 may be completely removed in the process of forming the gate top pad 175 and the data pad 175.

Thereafter, the second photoresist pattern from which the step is removed is completely removed.

Referring to FIG. 9, a bank layer 190 may be further formed on the passivation layer 160 including the pixel electrode 173. Here, examples of the material for forming the bank layer 190 may be an acrylic resin for photoresist. The material of the bank layer 190 is not limited in the embodiment of the present invention, and other examples of the material forming the bank layer 190 may be a polyimide resin, a phenol resin, a benzocyclobutene resin, or the like.

Here, the bank layer 190 is subjected to an exposure and development process using a mask to form an opening exposing the pixel electrode 173. At this time, first and second openings 191 and 192 for exposing the gate lower pad 175 and the data pad 176 may be formed in the bank layer 190, respectively.

Therefore, as in the embodiment of the present invention, the thin film transistor substrate according to the embodiment of the present invention is formed by using the single oxide semiconductor pattern 131 and the gate electrode 151, Can be reduced.

The oxide semiconductor pattern 131 and the gate electrode 151 are formed using the same mask so that the channel region 131a of the oxide semiconductor pattern 131 and the gate electrode It is possible to solve the misalignment problem between the semiconductor chip 151 and the semiconductor chip 151.

The oxide semiconductor pattern 131 and the gate electrode 151 are formed using the same mask so that the channel region 131a of the oxide semiconductor pattern 131 and the gate electrode The manufacturing process can be further facilitated due to the self-alignment between the semiconductor chips 151.

In addition, in the thin film transistor substrate according to the embodiment of the present invention, the oxide semiconductor pattern 131 and the gate electrode 151 are formed using the same mask, and dry etching is performed to etch the gate insulating layer without a separate conducting process The source and drain regions of the oxide semiconductor pattern can be formed by using the oxide semiconductor pattern, and the process can be further simplified.

In addition, since the source and drain electrodes SE and DE and the pixel electrode 173 are formed by using one mask, the thin film transistor substrate according to the embodiment of the present invention has another mask process number Can be reduced.

100: base layer 110: shield pattern
120: buffer layer 131: oxide semiconductor pattern
132: first dummy oxide semiconductor pattern
133: second dummy oxide semiconductor pattern
141: Gate insulation pattern
142: first dummy gate insulation pattern
143: Second dummy gate insulation pattern
SE: source electrode DE: drain electrode
160: protective layer 173: pixel electrode
152: storage electrode 174, 183: second storage electrode
190: bank layer

Claims (15)

A base layer;
An oxide semiconductor pattern disposed on the base layer, the oxide semiconductor pattern having a channel region and source and drain regions disposed on both sides of the channel region, respectively;
A first dummy oxide semiconductor pattern formed of the same material as the oxide semiconductor pattern,
A gate insulating pattern exposing both the source and drain regions and disposed at a position corresponding to the channel region of the oxide semiconductor pattern;
A first dummy gate insulating pattern disposed at a position corresponding to the first dummy oxide semiconductor pattern;
A gate electrode disposed only at a position corresponding to the gate insulating pattern;
A first storage electrode disposed only at a position corresponding to the first dummy gate insulation pattern;
A protective layer disposed on the base layer including the gate electrode and having first and second contact holes exposing the source and drain regions of the oxide semiconductor pattern, respectively;
A source electrode disposed on the protection layer and in contact with the source region through the first contact hole;
A drain electrode disposed on the protection layer and in contact with the drain region through the second contact hole;
A pixel electrode disposed on the protective layer and having a portion of the drain electrode extended; And
And a second storage electrode overlapped with the first storage electrode and disposed on the protective layer.
The method according to claim 1,
Wherein each of the source electrode and the drain electrode is formed of a transparent conductive oxide pattern formed of the same material as the pixel electrode and a metal pattern disposed on the transparent conductive oxide pattern.
3. The method of claim 2,
Wherein the transparent conductive oxide pattern of the pixel electrode and the drain electrode is formed integrally.
delete The method according to claim 1,
Gate wiring;
A gate lower pad arranged at one end of the gate wiring;
A second dummy gate insulation pattern disposed under the gate lower pad;
A second dummy oxide semiconductor pattern disposed under the second dummy gate insulated pattern;
A gate upper pad disposed on the gate lower pad and formed of the same material as the pixel electrode;
A data line crossing the gate line; And
And a data pad disposed at one end of the data line and formed of the same material as the pixel electrode.
The method according to claim 1,
A shield pattern disposed on the base layer corresponding to the oxide semiconductor pattern; And
And a buffer layer disposed between the shield pattern and the oxide semiconductor pattern.
Providing a base layer;
Sequentially forming an oxide semiconductor layer, a gate insulating layer, and a metal layer on the base layer;
Forming a photoresist pattern having a step on the metal layer;
Etching the oxide semiconductor layer, the gate insulating layer, and the metal layer using the photoresist pattern as an etching mask to form an oxide semiconductor pattern, a preliminary gate insulating pattern, and a preliminary gate electrode;
Removing a step of the photoresist pattern;
Forming a gate insulation pattern and a gate electrode by etching the preliminary gate insulation pattern and the preliminary gate electrode using the photoresist pattern from which the step is removed as an etching mask to form source and drain regions of the oxide semiconductor pattern;
Forming a protective layer on the base layer including the gate electrode and having first and second contact holes exposing source and drain regions of the oxide semiconductor pattern, respectively; And
Forming source and drain electrodes and a pixel electrode electrically connected to the drain electrode, the source electrode and the drain electrode being in contact with the source and drain regions of the oxide semiconductor pattern through the first and second contact holes, respectively, Wherein the method comprises the steps of:
8. The method of claim 7,
Wherein the source and drain electrodes are formed of a transparent conductive oxide pattern formed of the same material as the pixel electrode and a metal pattern disposed on the transparent conductive oxide pattern and each of which is in direct contact with the source region and the drain region, Way.
9. The method of claim 8,
Wherein the source and drain electrodes and the pixel electrode are formed using a single mask.
9. The method of claim 8,
Wherein a transparent conductive oxide pattern of the pixel electrode and the drain electrode is formed integrally.
8. The method of claim 7,
Wherein the first dummy oxide semiconductor pattern, the first dummy gate insulating pattern, and the first storage electrode are sequentially formed in the step of forming the oxide semiconductor pattern, the gate insulating pattern, and the gate electrode,
Forming a pixel electrode electrically connected to the source and drain electrodes and the drain electrode; and forming a second storage electrode overlapping the first storage electrode on the protective layer.
8. The method of claim 7,
Wherein the step of forming the oxide semiconductor pattern, the gate insulating pattern and the gate electrode comprises the steps of: forming a gate wiring, a gate lower pad disposed at one end of the gate wiring, a second dummy gate insulating pattern disposed under the gate lower pad, A second dummy oxide semiconductor pattern disposed under the second dummy gate insulating pattern is further formed,
Forming a pixel electrode electrically connected to the source and drain electrodes and the drain electrode, the gate upper pad formed on the gate lower pad and formed of the same material as the pixel electrode, the data line crossing the gate wiring, And a data pad formed on one end of the data line and formed of the same material as the pixel electrode.
8. The method of claim 7,
In the step of providing the base layer
A shield pattern disposed on the base layer and corresponding to the oxide semiconductor pattern; And a buffer layer on the base layer including the shield pattern.
delete 8. The method of claim 7,
Wherein the source and drain regions of the oxide semiconductor pattern are formed in a dry etching process for etching the preliminary gate insulating pattern.

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