KR101895817B1 - 실리콘 웨이퍼 및 그 제조 방법 - Google Patents
실리콘 웨이퍼 및 그 제조 방법 Download PDFInfo
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Abstract
Description
도 2는, 돌출부의 형태의 LPD의 SEM상이다.
도 3은, 오목부의 형태의 LPD의 SEM상이다.
도 4는, 붕소 농도 및, 산소 도너 농도와, LPD 발생의 유무의 관계를 나타내는 도면이다.
도 5는, 잉곳의 종별과, 결정 육성 완료 후 웨이퍼를 잘라내기까지의 일수의 관계를 나타내는 도면이다.
Claims (14)
- 미(未)열처리 실리콘 웨이퍼에 대해서, 붕소 농도가, 5×1014atoms/㎤ 이상, 또한 7×1014atoms/㎤ 이하이고, 또한, 산소 도너 농도가, 4×1014개/㎤ 이상, 또한 8×1014개/㎤ 이하인 경우에, 상기 미열처리 실리콘 웨이퍼에 대하여, 산소 도너 농도가, 4×1014개/㎤ 미만이 되도록, 300℃ 이상의 온도에서의 열처리를 실시하는 것을 특징으로 하는 실리콘 웨이퍼의 제조 방법.
- 실리콘 단결정의 잉곳, 또는 당해 잉곳으로부터 잘라낸 블록에 대해서, 붕소 농도가, 5×1014atoms/㎤ 이상, 또한 7×1014atoms/㎤ 이하이고, 또한, 산소 도너 농도가, 4×1014개/㎤ 이상, 또한 8×1014개/㎤ 이하인 경우에, 상기 잉곳의 결정 육성 완료 후 50일 이내에, 상기 잉곳 또는 블록으로부터 웨이퍼를 잘라내는 것을 특징으로 하는 실리콘 웨이퍼의 제조 방법.
- 제1항 또는 제2항에 있어서,
도너 킬러 열처리한 경우의 저항률이, 19Ω·㎝ 이상, 또한 26Ω·㎝이하인 것을 특징으로 하는 실리콘 웨이퍼의 제조 방법. - 삭제
- 삭제
- 액셉터로서 붕소를 함유하는 실리콘 단결정을 슬라이스하여, 미열처리 실리콘 웨이퍼를 얻는 공정과,
상기 미열처리 실리콘 웨이퍼에 대해서, 붕소 농도를 구하는 공정과,
상기 미열처리 실리콘 웨이퍼에 대해서, 산소 도너 농도를 구하는 공정을 포함하고,
상기 붕소 농도를 구하는 공정에서 구해진 붕소 농도 및, 상기 산소 도너 농도를 구하는 공정에서 구해진 산소 도너 농도에 기초하여, 상기 미열처리 실리콘 웨이퍼에 대하여, 300℃ 이상의 온도에서의 열처리를 실시할지 여부를 판단하고,
상기 판단이, 상기 미열처리 실리콘 웨이퍼에 대해서, 상기 붕소 농도가, 5×1014atoms/㎤ 이상, 또한 7×1014atoms/㎤ 이하이고, 또한, 상기 산소 도너 농도가, 4×1014개/㎤ 이상, 또한 8×1014개/㎤ 이하라는 요건을 만족하는 경우는, 상기 미열처리 실리콘 웨이퍼에 대하여, 산소 도너 농도가, 4×1014개/㎤ 미만이 되도록, 300℃ 이상의 온도에서의 열처리를 실시한 후, 연마를 행한다고 판단하는 것인 것을 특징으로 하는 실리콘 웨이퍼의 제조 방법. - 제6항에 있어서,
상기 미열처리 실리콘 웨이퍼에 대하여, 300℃ 이상의 온도에서의 상기 열처리를 실시할지 여부를, 로트 단위로 판단하는 것을 특징으로 하는 실리콘 웨이퍼의 제조 방법. - 삭제
- 액셉터로서 붕소를 함유하는 실리콘 단결정의 잉곳, 또는 당해 잉곳으로부터 잘라낸 블록에 대해서, 붕소 농도를 구하는 공정과,
상기 잉곳 또는 블록에 대해서, 산소 도너 농도를 구하는 공정을 포함하고,
상기 붕소 농도를 구하는 공정에서 구해진 붕소 농도 및, 상기 산소 도너 농도를 구하는 공정에서 구해진 산소 도너 농도에 기초하여, 상기 잉곳의 결정 육성 완료 후 50일 이내에 상기 잉곳 또는 블록으로부터 웨이퍼를 잘라낼지 여부를 판단하고,
상기 판단이, 상기 잉곳 또는 블록에 대해서, 상기 붕소 농도가, 5×1014atoms/㎤ 이상, 또한 7×1014atoms/㎤ 이하이고, 또한, 상기 산소 도너 농도가, 4×1014개/㎤ 이상, 또한 8×1014개/㎤ 이하라는 요건을 만족하는 경우는, 상기 잉곳의 결정 육성 완료 후 50일 이내에 상기 잉곳 또는 블록으로부터 웨이퍼를 잘라낸다고 판단하는 것인 것을 특징으로 하는 실리콘 웨이퍼의 제조 방법. - 제9항에 있어서,
상기 잉곳의 결정 육성 완료 후 50일 이내에 상기 잉곳 또는 블록으로부터 웨이퍼를 잘라낼지 여부를, 로트 단위로 판단하는 것을 특징으로 하는 실리콘 웨이퍼의 제조 방법. - 액셉터로서 붕소를 함유하는 실리콘 단결정의 잉곳, 또는 당해 잉곳으로부터 잘라낸 블록에 대해서, 붕소 농도가, 5×1014atoms/㎤ 이상, 또한 7×1014atoms/㎤ 이하이고, 또한, 산소 도너 농도가, 4×1014개/㎤ 이상, 또한 8×1014개/㎤ 이하라는 요건을 만족하는 경우로서, 상기 잉곳의 결정 육성 완료 후 50일을 초과하여 상기 잉곳 또는 블록으로부터 웨이퍼를 잘라낸 경우에, 당해 잘라내어진 웨이퍼에 대하여, 산소 도너 농도가, 4×1014개/㎤ 미만이 되도록, 300℃ 이상의 온도에서의 열처리를 실시하는 것을 특징으로 하는 실리콘 웨이퍼의 제조 방법.
- 액셉터로서 붕소를 함유하는 실리콘 단결정의 잉곳, 또는 당해 잉곳으로부터 잘라낸 블록에 대해서, 붕소 농도가, 5×1014atoms/㎤ 이상, 또한 7×1014atoms/㎤ 이하이고, 또한, 산소 도너 농도가, 4×1014개/㎤ 이상, 또한 8×1014개/㎤ 이하라는 요건을 만족하는 경우로서, 상기 잉곳의 결정 육성 완료 후 50일 이내에 상기 잉곳 또는 블록으로부터 웨이퍼를 잘라낸 경우에는, 당해 잘라내어진 웨이퍼에 대하여, 300℃ 이상의 온도에서의 열처리를 실시하지 않는 것을 특징으로 하는 실리콘 웨이퍼의 제조 방법.
- 반도체 디바이스 제조 라인에 있어서 파티클을 모니터하기 위한 파티클 모니터 웨이퍼로서,
제1항, 제2항, 제6항, 제9항, 제11항 및 제12항 중 어느 한 항의 제조방법에 의해 제조된 것을 특징으로 하는 실리콘 웨이퍼. - COP 및 전위 클러스터를 포함하지 않는 실리콘 웨이퍼로서,
제1항, 제2항, 제6항, 제9항, 제11항 및 제12항 중 어느 한 항의 제조방법에 의해 제조된 것을 특징으로 하는 실리콘 웨이퍼.
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| JP2014114335 | 2014-06-02 | ||
| JPJP-P-2014-114335 | 2014-06-02 | ||
| PCT/JP2015/002025 WO2015186288A1 (ja) | 2014-06-02 | 2015-04-10 | シリコンウェーハおよびその製造方法 |
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| KR101895817B1 true KR101895817B1 (ko) | 2018-09-07 |
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| WO2015186288A1 (ja) * | 2014-06-02 | 2015-12-10 | 株式会社Sumco | シリコンウェーハおよびその製造方法 |
| JP6614066B2 (ja) * | 2016-08-22 | 2019-12-04 | 株式会社Sumco | シリコン接合ウェーハの製造方法 |
| JP6711327B2 (ja) | 2017-07-18 | 2020-06-17 | 株式会社Sumco | シリコンウェーハ製造工程の評価方法およびシリコンウェーハの製造方法 |
| JP6841202B2 (ja) * | 2017-10-11 | 2021-03-10 | 株式会社Sumco | 半導体ウェーハの評価方法および半導体ウェーハの製造方法 |
| JP7677127B2 (ja) * | 2021-11-29 | 2025-05-15 | 株式会社Sumco | モデル検証方法、モデル検証プログラム、情報処理装置、モデル、ウェーハの製造方法、及びウェーハ |
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| US20060263967A1 (en) * | 2005-05-19 | 2006-11-23 | Memc Electronic Materials, Inc. | High resistivity silicon structure and a process for the preparation thereof |
| US20120012983A1 (en) | 2009-03-25 | 2012-01-19 | Sumco Corporation | Silicon wafer and method of manufacturing same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6031232A (ja) * | 1983-07-29 | 1985-02-18 | Toshiba Corp | 半導体基体の製造方法 |
| JPH0786289A (ja) * | 1993-07-22 | 1995-03-31 | Toshiba Corp | 半導体シリコンウェハおよびその製造方法 |
| US5629216A (en) * | 1994-06-30 | 1997-05-13 | Seh America, Inc. | Method for producing semiconductor wafers with low light scattering anomalies |
| JP2862229B2 (ja) | 1996-01-26 | 1999-03-03 | ローム株式会社 | 半導体装置製造計画作成装置および半導体装置製造計画作成方法 |
| KR100240023B1 (ko) * | 1996-11-29 | 2000-01-15 | 윤종용 | 반도체 웨이퍼 열처리방법 및 이에 따라 형성된 반도체 웨이퍼 |
| DE19983188T1 (de) * | 1998-05-01 | 2001-05-10 | Nippon Steel Corp | Siliziumhalbleitersubstrat und Verfahren zu dessen Herstellung |
| TW505710B (en) * | 1998-11-20 | 2002-10-11 | Komatsu Denshi Kinzoku Kk | Production method for silicon single crystal and production device for single crystal ingot, and heat treating method for silicon single crystal wafer |
| JP4078782B2 (ja) | 2000-03-14 | 2008-04-23 | 株式会社Sumco | 高品質シリコン単結晶の製造方法 |
| US6663708B1 (en) * | 2000-09-22 | 2003-12-16 | Mitsubishi Materials Silicon Corporation | Silicon wafer, and manufacturing method and heat treatment method of the same |
| JP4607304B2 (ja) | 2000-09-26 | 2011-01-05 | 信越半導体株式会社 | 太陽電池用シリコン単結晶及び太陽電池用シリコン単結晶ウエーハ並びにその製造方法 |
| JP4822582B2 (ja) * | 2000-12-22 | 2011-11-24 | Sumco Techxiv株式会社 | ボロンドープされたシリコンウエハの熱処理方法 |
| KR101313326B1 (ko) * | 2006-12-29 | 2013-09-27 | 에스케이하이닉스 주식회사 | 후속 열처리에 의해 산소 침전물로 되는 유핵의 분포가제어된 실리콘 웨이퍼 및 그 제조방법 |
| JP5568837B2 (ja) * | 2008-02-29 | 2014-08-13 | 株式会社Sumco | シリコン基板の製造方法 |
| JP5561918B2 (ja) * | 2008-07-31 | 2014-07-30 | グローバルウェーハズ・ジャパン株式会社 | シリコンウェーハの製造方法 |
| JP5537802B2 (ja) * | 2008-12-26 | 2014-07-02 | ジルトロニック アクチエンゲゼルシャフト | シリコンウエハの製造方法 |
| US8263484B2 (en) * | 2009-03-03 | 2012-09-11 | Sumco Corporation | High resistivity silicon wafer and method for manufacturing the same |
| JP5515406B2 (ja) | 2009-05-15 | 2014-06-11 | 株式会社Sumco | シリコンウェーハおよびその製造方法 |
| JP2010283144A (ja) * | 2009-06-04 | 2010-12-16 | Sumco Corp | シリコンウェーハ及びその製造方法、並びに、半導体デバイスの製造方法 |
| JP5707682B2 (ja) | 2009-08-21 | 2015-04-30 | 株式会社Sumco | エピタキシャルシリコンウェーハの製造方法 |
| WO2011105255A1 (ja) * | 2010-02-26 | 2011-09-01 | 株式会社Sumco | 半導体ウェーハの製造方法 |
| FR2959351B1 (fr) * | 2010-04-26 | 2013-11-08 | Photowatt Int | Procede de preparation d’une structure de type n+pp+ ou de type p+nn+ sur plaques de silicium |
| DE112011102297B4 (de) * | 2010-07-08 | 2020-10-08 | Sumco Corporation | Verfahren zum Polieren von Siliziumwafern |
| JP5993550B2 (ja) * | 2011-03-08 | 2016-09-14 | 信越半導体株式会社 | シリコン単結晶ウェーハの製造方法 |
| MY181635A (en) * | 2011-06-03 | 2020-12-30 | Memc Singapore Pte Ltd | Processes for suppressing minority carrier lifetime degradation in silicon wafers |
| JP5682471B2 (ja) | 2011-06-20 | 2015-03-11 | 信越半導体株式会社 | シリコンウェーハの製造方法 |
| KR101246493B1 (ko) * | 2011-07-08 | 2013-04-01 | 주식회사 엘지실트론 | 웨이퍼의 결함 평가방법 |
| WO2013056186A1 (en) * | 2011-10-12 | 2013-04-18 | The Regents Of The University Of California | Semiconductor processing by magnetic field guided etching |
| JP5772553B2 (ja) * | 2011-12-06 | 2015-09-02 | 信越半導体株式会社 | シリコン単結晶の評価方法およびシリコン単結晶の製造方法 |
| JP5621791B2 (ja) * | 2012-01-11 | 2014-11-12 | 信越半導体株式会社 | シリコン単結晶ウェーハの製造方法及び電子デバイス |
| JP6111572B2 (ja) * | 2012-09-12 | 2017-04-12 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
| FR2997096B1 (fr) * | 2012-10-23 | 2014-11-28 | Commissariat Energie Atomique | Procede de formation d'un lingot en silicium de resistivite uniforme |
| JP2014236093A (ja) * | 2013-05-31 | 2014-12-15 | サンケン電気株式会社 | シリコン系基板、半導体装置、及び、半導体装置の製造方法 |
| JP6115651B2 (ja) * | 2014-01-14 | 2017-04-19 | 株式会社Sumco | シリコンウェーハの製造方法 |
| JP6156188B2 (ja) * | 2014-02-26 | 2017-07-05 | 株式会社Sumco | エピタキシャルシリコンウェーハの製造方法 |
| WO2015186288A1 (ja) * | 2014-06-02 | 2015-12-10 | 株式会社Sumco | シリコンウェーハおよびその製造方法 |
-
2015
- 2015-04-10 WO PCT/JP2015/002025 patent/WO2015186288A1/ja not_active Ceased
- 2015-04-10 CN CN201580029564.0A patent/CN106463403B/zh active Active
- 2015-04-10 JP JP2016525673A patent/JP6187689B2/ja active Active
- 2015-04-10 US US15/306,860 patent/US10526728B2/en active Active
- 2015-04-10 DE DE112015002599.5T patent/DE112015002599B4/de active Active
- 2015-04-10 KR KR1020167035181A patent/KR101895817B1/ko active Active
- 2015-06-01 TW TW105126517A patent/TWI580826B/zh active
- 2015-06-01 TW TW104117600A patent/TWI571541B/zh active
-
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- 2017-06-15 JP JP2017118148A patent/JP6388058B2/ja active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060263967A1 (en) * | 2005-05-19 | 2006-11-23 | Memc Electronic Materials, Inc. | High resistivity silicon structure and a process for the preparation thereof |
| US20120012983A1 (en) | 2009-03-25 | 2012-01-19 | Sumco Corporation | Silicon wafer and method of manufacturing same |
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|---|---|
| DE112015002599T5 (de) | 2017-04-06 |
| JP2017200878A (ja) | 2017-11-09 |
| DE112015002599B4 (de) | 2025-12-18 |
| TWI580826B (zh) | 2017-05-01 |
| JPWO2015186288A1 (ja) | 2017-04-20 |
| CN106463403B (zh) | 2020-05-05 |
| CN106463403A (zh) | 2017-02-22 |
| KR20170005107A (ko) | 2017-01-11 |
| TW201643281A (zh) | 2016-12-16 |
| US20170044688A1 (en) | 2017-02-16 |
| TW201608064A (zh) | 2016-03-01 |
| JP6388058B2 (ja) | 2018-09-12 |
| TWI571541B (zh) | 2017-02-21 |
| JP6187689B2 (ja) | 2017-08-30 |
| WO2015186288A1 (ja) | 2015-12-10 |
| US10526728B2 (en) | 2020-01-07 |
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