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KR101726568B1 - 회로기판 제조방법 - Google Patents

회로기판 제조방법 Download PDF

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Publication number
KR101726568B1
KR101726568B1 KR1020160021772A KR20160021772A KR101726568B1 KR 101726568 B1 KR101726568 B1 KR 101726568B1 KR 1020160021772 A KR1020160021772 A KR 1020160021772A KR 20160021772 A KR20160021772 A KR 20160021772A KR 101726568 B1 KR101726568 B1 KR 101726568B1
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South Korea
Prior art keywords
insulating layer
cavity
copper foil
bump pad
exposed
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KR1020160021772A
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English (en)
Inventor
고영주
고태혁
이형도
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대덕전자 주식회사
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Priority to KR1020160021772A priority Critical patent/KR101726568B1/ko
Priority to US15/172,279 priority patent/US10103113B2/en
Priority to CN201610519447.9A priority patent/CN107124833B/zh
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Publication of KR101726568B1 publication Critical patent/KR101726568B1/ko
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09036—Recesses or grooves in insulating substrate
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
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    • H05K2203/10—Using electric, magnetic and electromagnetic fields; Using laser light
    • H05K2203/107—Using laser light
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    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
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Abstract

본 발명은 캐비티 영역에 대응하는 기판 표면에 범프패드를 형성하고, 그 위에 제2 절연층(예를 들어, 유리섬유질이 함유되지 않은 레진과 같이 샌드블라스트 공정으로 식각 가능한 절연층)을 전면 적층하고, 캐비티 영역에 대응한 제2 절연층 표면에 제2 절연층을 보호하는 동박 배리어를 형성하고, 다시 그 위에 제3 절연층(예를 들어 프리프레그)을 전면 적층하고, 그 위에 동박회로를 형성한다.
캐비티 영역만을 노출하는 마스크를 외층의 동박회로 위에 형성하고, 표면이 노출된 제3 절연층을 레이저 드릴 가공하여 캐비티를 형성한다. 이 때에 하단에는 동박 배리어가 있어서, 레이저가 제2 절연층 또는 하부의 범프패드를 손상하는 것을 방지한다. 레이저 드릴이 끝나고 나면 동박 배리어를 화학적 습식 식각 방식으로 제거하고, 하부에 표면이 노출된 제2 절연층을 샌드블라스트 방식으로 제거함으로써, 미리 제작하여 놓은 범프패드를 노출한다.

Description

회로기판 제조방법{METHOD OF MANUFACTURING PRINTED CIRCUIT BOARD}
본 발명은 칩 실장을 위한 캐비티(Cavity) 제조방법에 관한 것으로서, 더욱 상세하게는 캐비티를 단순히 칩을 매립(embed)하기 위한 공간으로만 사용하는 것이 아니라, 캐비티에 실장되는 칩을 캐비티 하단부의 패키지 기판 표면과 직접 플립칩(flip-chip) 방식으로 전기 접속될 수 있도록, 캐비티 하단부 기판 표면에 범프패드(bunp pad)를 제작하는 공법에 관한 것이다.
반도체 패키지 기술이 나날이 고도화되고 있다. 반도체 패키지 기술은 종래의 2차원(2-D) 패키지기술로부터, 2.5 차원(2.5-D) 내지 3차원(3-D) 패키지 기술로 발전하고 있다. 즉, 기판 위에 칩을 실장하는 기술로부터 기판 속과 기판 위의 3차원 공간을 모두 입체적으로 활용하는 기술로 발전하고 있다.
패키지 공간을 축소하고 다이 스택을 집적화하기 위해서는 캐비티(cavity) 가공을 통한 임베드 공법(Embedding Process)이 견인기술(leading technology)로서 관심을 끌고 있다.
도1a 내지 도1c는 종래기술에 따라 제작된 캐비티에 칩이 매립 실장된 모습을 나타낸 도면이다.
도1a 및 도1b를 참조하면, 캐비티(10) 제작을 위해서 프리프레그(5)를 레이저로 드릴 가공을 하는데, 레이저 드릴 가공 시에 식각되는 프리프레그(5)의 식각 단면이 평탄하지 않기 때문에 칩(30)을 바로 실장하는 것이 용이하지 않다. 이러한 문제를 해결하기 위하여, 종래기술은 동박 배리어(Copper barrier; 20)를 바닥에 형성한 상태에서 적층된 프리프레그를 레이저로 드릴 가공함으로써 프리프레그 바닥면이 손상되는 것을 방지한다.
다시 설명하면, 동박 배리어(20) 없이 레이저 가공을 할 경우에, 하부의 레진층이 레이저로 손상(damage)를 입어서 바닥면이 평탄하지 않게 되어 칩(30) 실장이 용이하지 않게 된다.
그런데 종래기술에 따라 동박 배리어 위에 칩(30)을 실장 할 경우에, 단순히 캐비티 속에 칩(30)을 실장하는 것은 가능하지만, 칩 단자를 패키지기판에 직접 플립칩(flip-chip) 방식으로 전기 접속하는 것이 용이하지 않다. 종래기술은 칩 상부면의 패드와 기판의 패드를 와이어본딩(40) 방식으로 서로 연결하는 기술을 적용하고 있다.
최근 들어, 실장 할 칩은 많은 수량의 단자를 가지고 있고, 다량의 단자를 와이어 본딩 하기 위해서는 많은 면적과 많은 수량의 패드가 패키지 기판에 필요하므로, 칩을 와이어본딩 방식만으로 기판에 접속할 경우 패키지 사이즈도 증가하고, 패키지 비용도 증가한다. 게다가, 특히 도1c에 도시한 대로 캐비티 속에 다이 스택(die stack; 50)을 구성하려고 할 경우, 전기적 접속문제가 더욱 기술적으로 어렵게 된다.
따라서, 캐비티 바닥면에 범프패드(bump pad)를 제작하여 플립칩 본딩을 할 수 있도록 해주는 공법의 개발이 필요하다. 기존기술을 응용해서, 단순히 동박 배리어(20)에 패턴이 전사된 식각 마스크를 피복하고, 선택 에칭을 해서 범프패드를 만들 수 있을 것으로 기대할 수 있으나, 이 경우 패드 사이에 발생하는 불균일한 레진 식각으로 인하여 범프패드가 쉽게 박리되거나, 식각된 범프의 레진 깊이에 있어 불균일이 발생하게 되는 문제점이 있다.
1. 대한민국 특허공개 제10-2013-0096381호. 2. 대한민국 특허등록 제139,273호. 3. 대한민국 특허등록 제101,580,472호.
본 발명의 제1 목적은 캐비티 속에 플립칩 실장이 가능하도록 범프패드를 제작하는 기술을 제공하는데 있다.
본 발명의 제2 목적은 상기 제1 목적에 부가하여, 캐비티 속에 다이 스택이 가능하도록 하는 기술을 제공하는데 있다.
본 발명은 캐비티 영역에 대응하는 기판 표면에 범프패드를 형성하고, 그 위에 제2 절연층(예를 들어, 유리섬유질이 함유되지 않은 레진과 같이 샌드블라스트 공정으로 식각 가능한 절연층)을 전면 적층하고, 캐비티 영역에 대응한 제2 절연층 표면에 제2 절연층을 보호하는 동박 배리어를 형성하고, 다시 그 위에 제3 절연층(예를 들어 프리프레그)을 전면 적층하고, 그 위에 동박회로를 형성한다.
이어서, 캐비티 영역만을 노출하는 마스크를 외층의 동박회로 위에 형성하고, 표면이 노출된 제3 절연층을 레이저 드릴 가공하여 캐비티를 형성한다. 이 때에 하단에는 동박 배리어가 있어서, 레이저가 제2 절연층 또는 하부의 범프패드를 손상하는 것을 방지한다. 레이저 드릴이 끝나고 나면 동박 배리어를 화학적 습식 식각 방식으로 제거하고, 하부에 표면이 노출된 제2 절연층을 샌드블라스트 방식으로 제거함으로써, 미리 제작하여 놓은 범프패드를 노출한다.
본 발명은 캐비티 하부 바닥면에 평탄하고 균일한 범프패드를 제공함으로써, 칩을 단순히 캐비티 속에 삽입하여 패티지 공간을 절약할 뿐 아니라, 플립칩 본딩이 가능하게 함으로써 패키지기판의 집적도를 더욱 배가하고 다이 스택도 가능하게 한다. 그 결과 저비용 고집적도의 패키지기판 제작을 가능하게 한다.
도1a 내지 도1c는 종래기술에 따라 제작된 캐비티에 칩이 실장된 모습을 나타낸 도면.
도2a 내지 도2f는 본 발명에 따른 캐비티 제조공법을 나타낸 도면이다.
본 발명은 (a) 캐비티를 제작할 영역에 대응하는 제1 절연층 위에 소정의 회로패턴을 전사하여 범프패드를 포함한 제1 동박을 형성하는 단계; (b) 상기 단계 (a)의 결과 구조물 위에 제2 절연층과 제2 동박을 적층 형성하는 단계; (c) 제2 동박을 소정의 패턴에 따라 선택적으로 식각해서, 상기 캐비티 영역에 대응한 제2 절연층 표면에 동박 배리어를 형성하는 단계; (d) 상기 단계 (c)의 결과 구조물 표면에 제3 절연층을 적층하여 형성하는 단계; (e) 제3 절연층 위에 소정의 회로패턴이 전사된 제3 동박을 형성하는 단계; (f) 레이저 드릴 가공을 해서 표면이 노출된 제3 절연층을 선택적으로 제거함으로써 캐비티를 개구하는 단계; (g) 캐비티를 형성하고자 하는 영역만을 노출하는 식각마스크를 표면에 피복하는 단계; (h) 표면이 노출된 동박 배리어를 제거하는 단계; 및 (i) 표면이 노출된 제2 절연층을 샌드블라스트 식각으로 제거함으로써, 캐비티 하부의 제1 절연층 위에 형성된 범프패드를 노출하는 단계를 포함하는 회로기판 제조방법을 제공한다.
본 발명에 따른 제2 절연층은 유리섬유질을 포함하지 않은 레진을 주원료로 하는 자재이고, 제3 절연층은 유리섬유질을 포함한 레진 또는 프리프레그를 주원료로 하는 자재로서, 샌드블라스 식각이 가능한 자재인 것을 특징으로 한다.
이하, 첨부도면 도2a 내지 도2f를 참조하여, 본 발명에 따른 캐비티 제작공법 및 이를 적용한 회로기판 기술을 상세히 설명한다.
본 발명에 따른 회로기판 제조공법은, 중앙에 레진 또는 에폭시 수지층 등을 재질로 하는 제1 절연층 위에 동박이 피복된 구조물을 시작재로 사용할 수 있다. 본 발명의 양호한 실시예로서, 동박적층판(CCL; copper cladded laminate) 또는 캐리어동박을 사용하여 코어리스 가공을 할 수도 있다.
도2a는 본 발명에 따른 패키지기판 제조의 중간 결과물을 보이는 도면이다. 도2a를 참조하면, 제1 절연층(100) 표면에 회로패턴이 전사된 제1 동박을 형성한다. 기존의 마스크 피복, 사진, 현상, 식각 등 일련의 이미지 프로세스를 동시에 진행해서, 제1 절연층(100) 표면에 도면부호 110a로 표기한 일반 회로와, 캐비티 바닥면의 범프패드(110b)를 구성할 패턴을 동시에 제작하는 것을 특징으로 한다.
일반 동박회로(110a)와 범프패드(110b) 위에 제2 절연층과 제2 동박을 적층한다. 본 발명에 따른 제2 절연층의 양호한 실시예로서, 유리 섬유질(glass fiber) 성분은 없고 필라 성분만을 함유한 특수 레진(resin)이 바람직하다. 본 발명에 따른 제2 절연층은 글래스 파이버가 함침되어 있지 않기 때문에, 샌드블라스트(sand blast) 공정에 의해 식각이 가능하다.
제2 동박을 소정의 회로패턴에 따라 식각함으로써, 동박 배리어(copper barrier; 130)를 형성한다. 대략적으로 동박 배리어(130)가 남아 있는 영역은, 캐비티 영역에 대응된다. 레진 또는 일반 에폭시수지 재질의 제3 절연층(140)을 적층한다. 제3 절연층(140)의 양호한 실시예로서 프리프레그(PREPREG)를 사용할 수 있다.
여기서, 제2 절연층(130)은 글래스 파이버 성분이 없어 후공정 단계에서 샌드블라스트 공정으로 식각이 가능한 반면에, 제3 절연층(140)은 글래스 파이버 성분을 함침하고 있어서 샌드블라스트 공정으로는 쉽게 식각이 되지 아니하는 것을 특징으로 한다. 필요 시에 홀가공을 해서 층간 접속을 위한 비아홀을 제작하고 동도금을 실시해서 외층 표면에 동박회로(150)를 형성할 수 있다.
도2a를 참조하면, 기판 외층을 형성하는 동박회로(150)는 캐비티가 생성될 부위에 대응하는 제3 절연층(140) 표면을 노출하고 있으며, 나머지 영역을 솔더레지스트와 같은 보호용 절연막(160)으로 피복되어 있다.
도2b를 참조하면, 레이저 드릴(laser drill) 공정을 실시해서 표면이 노출된 제3 절연층을 태워 제거함으로써 캐비티(cavity) 영역을 개구한다. 이때에 바닥의 동박 배리어(130)가 하부층이 레이저에 의해 손상을 입는 것을 방지한다.
이어서, 도2c를 참조하면, 드라이필름(D/F; dryfilm)과 같은 마스크 재료를 피복하고 사진, 현상, 식각 등 일련의 이미지 프로세스를 진행함으로써, 동박 배리어(130)만을 제거할 수 있도록 캐비티 영역만을 노출하는 식각마스크(170)를 형성한다. 식각마스크(170)가 피복된 상태에서 화학적 습식식각 공정을 진행해서 동박 배리어(130)을 벗겨낼 수 있다. 도2d는 동박 배리어(130)을 벗겨낸 후, 캐비티 영역에 대응한 제2 절연층 표면이 노출된 기판 단면을 도시하고 있다.
도2e를 참조하면, 식각마스크(170)을 피복한 상태에서 샌드블라스트(sand blast) 공정을 진행해서 표면이 노출된 제2 절연층(130)을 제거한다. 그 결과, 제1 절연층(100) 위의 캐비티 바닥면에 범프패드(110b)가 노출되어 형성된다. 도2f를 참조하면, 최종적으로 식각마스크(170)을 박리제거한다.
그 결과, 도2f를 참조하면 캐비티 바닥면에는 플립칩 접속이 가능한 범프패드(110b)들이 형성되어 있음을 확인할 수 있다.
전술한 내용은 후술할 발명의 특허청구범위를 더욱 잘 이해할 수 있도록 본 발명의 특징과 기술적 장점을 다소 폭넓게 개선하였다. 본 발명의 특허청구범위를 구성하는 부가적인 특징과 장점들이 이하에서 상술 될 것이다. 개시된 본 발명의 개념과 특정 실시예는 본 발명과 유사 목적을 수행하기 위한 다른 구조의 설계나 수정의 기본으로서 즉시 사용될 수 있음이 당해 기술 분야의 숙련된 사람들에 의해 인식되어야 한다.
또한, 본 발명에서 개시된 발명 개념과 실시예가 본 발명의 동일 목적을 수행하기 위하여 다른 구조로 수정하거나 설계하기 위한 기초로서 당해 기술 분야의 숙련된 사람들에 의해 사용될 수 있을 것이다. 또한, 당해 기술 분야의 숙련된 사람에 의한 그와 같은 수정 또는 변경된 등가 구조는 특허 청구 범위에서 기술한 발명의 사상이나 범위를 벗어나지 않는 한도 내에서 다양한 진화, 치환 및 변경이 가능하다.
본 발명은 캐비티 하부 바닥면에 평탄하고 균일한 범프패드를 제공함으로써, 칩을 단순히 캐비티 속에 삽입하여 패티지 공간을 절약하는 효과뿐 아니라, 플립칩 본딩이 가능하게 함으로써, 패키지기판의 집적도를 더욱 배가하고 다이 스택도 가능하게 한다.

Claims (2)

  1. 칩을 캐비티에 매립하되 캐비티 바닥면에 범프패드를 제작하여 칩단자를 바닥면의 범프패드와 플립칩 연결을 하는 회로기판을 제조하는 방법에 있어서,
    (a) 캐비티를 제작할 영역에 대응하는 제1 절연층 위에 소정의 회로패턴을 전사하여 범프패드를 포함한 제1 동박을 형성하는 단계;
    (b) 상기 단계 (a)의 결과 구조물 위에 제2 절연층과 제2 동박을 차례로 적층 형성하되, 상기 제2 절연층은 유리섬유질(glass fiber)를 포함하지 않은 자재로서, 후속하는 샌드블라스트 식각 공정으로 제거가 가능한 자재인 것을 특징으로 하는 형성단계;
    (c) 제2 동박을 소정의 패턴에 따라 선택적으로 식각해서, 상기 캐비티를 제작할 영역에 대응한 제2 절연층 표면에 동박 배리어를 형성하는 단계;
    (d) 상기 단계 (c)의 결과 구조물 표면에 제3 절연층을 적층하여 형성하는 단계;
    (e) 제3 절연층 위에 소정의 회로패턴이 전사된 제3 동박을 형성하는 단계;
    (f) 레이저 드릴 가공을 해서 표면이 노출된 제3 절연층을 선택적으로 제거함으로써 캐비티를 제작할 영역만을 개구하는 단계;
    (g) 캐비티를 제작할 영역만을 노출하는 식각마스크를 표면에 피복하는 단계;
    (h) 표면이 노출된 동박 배리어를 화학적 식각 방식으로 제거하는 단계; 및
    (i) 표면이 노출된 제2 절연층을 샌드블라스트 식각으로 제거하여 캐비티 바닥면을 형성하는 제1 절연층 위에 형성된 범프패드를 노출하는 단계
    를 포함하는 회로기판 제조방법.
  2. 삭제
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CN113411977A (zh) * 2021-06-30 2021-09-17 生益电子股份有限公司 一种阶梯槽的制作方法及电路板
CN113411977B (zh) * 2021-06-30 2022-07-12 生益电子股份有限公司 一种阶梯槽的制作方法及电路板
CN115190697A (zh) * 2022-07-19 2022-10-14 常州海弘电子有限公司 一种印制电路板通孔与盲孔快速金属化工艺
CN115190697B (zh) * 2022-07-19 2023-08-08 常州海弘电子有限公司 一种印制电路板通孔与盲孔快速金属化工艺
CN119653639A (zh) * 2025-02-18 2025-03-18 珠海杰赛科技有限公司 一种改善金层塌陷或镀金焊盘破损的pcb制作方法

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