KR101707849B1 - Semiconductor device having asymmetric dual-gate structure and fabrication method thereof - Google Patents

Abstract

In the present invention, two gates are formed to have an asymmetric structure by a separate separate process, so that different electrical characteristics can be obtained according to gates in a single device, whereby a memory device having both a volatile / non- A TFET capable of easily adjusting a threshold voltage, and a synapse mimic element capable of short-term memory switching, and a method of manufacturing the semiconductor device.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having an asymmetric dual gate structure,

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having an asymmetric dual gate structure that can be independently controlled and a method of manufacturing the same.

A semiconductor device having a conventional dual gate structure can be formed in the channel length direction on the channel region between the source and the drain as in Korean Patent No. 10-1286707 or on the source / drain and channel regions Body) and two independent gates are formed.

However, all conventional dual gates are symmetrically formed, so that different electrical characteristics can not be obtained according to two independent gates in one semiconductor device, and thus various kinds of devices can be utilized such as a synapse mimic element having a short-term memory switching function There is no problem.

Therefore, it is an object of the present invention to provide a semiconductor device structure which can be variously used for a synapse mimetic device or the like by making two gates have an asymmetric structure with each other, And to provide a process method capable of manufacturing an asymmetric dual gate device by only a CMOS process.

In order to achieve the above object, a semiconductor device having an asymmetric dual gate structure according to the present invention includes: a source region and a drain region spaced apart from a semiconductor substrate by a predetermined distance; A fin body connecting the source region and the drain region; A first gate formed on one side of the pin body with a first gate insulating film interposed therebetween; An insulating film side wall formed on the pin body and on one side of the first gate; And a second gate formed on the sidewall of the insulating film and on the opposite side of the pin body with a second gate insulating film interposed therebetween, wherein any one of the first gate insulating film and the second gate insulating film is a single material layer And the other is formed of a laminated structure of two or more material layers including a charge storage layer.

The first gate insulating film may be a silicon oxide film, and the second gate insulating film may be formed of a stacked structure of an oxide film, a nitride film, and an oxide film.

The source region and the drain region may have opposite conductivity types.

The semiconductor substrate may be an SOI substrate, and the first gate and the second gate insulating film may be formed on the buried insulating film.

A method of fabricating a semiconductor device having an asymmetric dual gate structure according to the present invention includes a first step of forming a hard mask on an SOI substrate and etching a silicon layer of the SOI substrate to form a groove for a first gate; A second step of oxidizing the silicon layer exposed at the side of the first gate groove to form a first gate oxide film and filling the first gate material with the first gate material to form a first gate; A third step of removing the hard mask; A fourth step of depositing an insulation film on the entire surface of the SOI substrate and etching the insulation film to form a side wall of the insulation film on the side of the first gate; A fifth step of forming an etch mask for defining an active region in the silicon layer facing one side of the first gate; A sixth step of etching the silicon layer with the etching mask to form an active region connected to a fin body; Depositing a second gate insulating film and a second gate material over the entire surface of the SOI substrate and etching the second gate insulating film to form a second gate; And an eighth step of etching the first gate and the second gate to expose the active region and ion implantation to form a source / drain region, wherein the second gate insulating film in the seventh step includes a charge storage Layer structure including two or more material layers.

The first step may include forming a first gate contact groove on one side of the first gate groove, and the second step may include depositing the first gate material to a predetermined thickness, and then planarizing In the seventh step, the second gate material is deposited to a predetermined thickness and then etched by a planarization process so that the second gate insulating film is exposed.

The sidewall of the insulating film in the fourth step is etched after depositing an oxide film by LPCVD. In the sixth step, the sidewall of the insulating film is used as an etch mask for forming a fin body, and the etch mask in the fifth step is formed only on the source / .

delete

Wherein the hard mask is formed by sequentially laminating an oxide film and a nitride on the SOI substrate, wherein the first gate material and the second gate material are polysilicon or amorphous silicon, and the second gate insulating film is an oxide film / / Oxide film can be formed.

In the present invention, two gates are formed to have an asymmetric structure by a separate separate process, so that different electrical characteristics can be obtained according to gates in a single device, whereby a memory device having both a volatile / non- , A TFET (Tunneling Field Effect Transistor) capable of easily adjusting a threshold voltage through any one of the gates, and a synapse mimic element capable of short-term memory switching.

1 to 9 are process drawings (plan views, sectional views) showing a method of manufacturing a semiconductor device having an asymmetric dual gate structure according to an embodiment of the present invention. Particularly, Figures 1 (b), 2 (b), 3 (b), 4 (b), 6 (b) and 7 FIG. 3A is an enlarged cross-sectional view taken along line AA in FIG. 3A, FIG. 4A, FIG. 6A and FIG.
FIG. 10 is a graph showing the relationship between the drain voltage Vd of the first gate 52 and the drain voltage Vd of the first gate 52 in a state where a constant voltage is applied to the second gate 92 in the semiconductor device having the asymmetric dual gate structure according to the embodiment of the present invention This is an electrical characteristic diagram showing current characteristics.
FIG. 11 is a graph showing the relationship between the drain voltage Vd of the second gate 92 and the gate voltage Vd of the second gate 92 in a state where a constant voltage is applied to the first gate 52 in the semiconductor device having an asymmetric dual gate structure according to an embodiment of the present invention This is an electrical characteristic diagram showing current characteristics.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

A semiconductor device having an asymmetric dual gate structure according to an embodiment of the present invention includes a source region (not shown) spaced a certain distance from the semiconductor substrate 20, as shown in the process drawings exemplarily shown in FIGS. 1 to 9 24 and a drain region 26; A fin body (22) connecting the source region and the drain region; A first gate (52) formed on one side of the pin body with a first gate insulating film (40) interposed therebetween; An insulation film sidewall 60 formed on the fin body and on one side of the first gate; And a second gate (92) formed on the sidewall of the insulating film and on the opposite side of the pin body with a second gate insulating film (80) interposed therebetween.

The semiconductor substrate may be a bulk substrate electrically isolated from the periphery by one or more impurity doping layers. However, as shown in FIG. 1, an SOI (Si-Si) layer having a silicon layer 20 on an embedded insulating film (buried oxide film: BOX) On-Insulator) substrate is preferable.

The first gate insulating film 40 and the second gate insulating film 80 may have the same material and / or the same stacking pattern, but as will be described later, proceeding to a separate process, (For example, a silicon oxide film), and the other is formed of a stack structure including a charge storage layer (for example, a stacked structure of two or more material layers including a charge storage layer capable of storing charges).

8, the first gate insulating layer 40 may be a silicon oxide layer, and the second gate insulating layer 80 may be formed of an oxide layer, a nitride layer, and an oxide layer. Referring to FIG.

As described above, since the first and second gates 52 and 92 are asymmetric with respect to each other and the first and second gate insulating films 40 and 80 are formed with different materials and / or structures, as shown in FIGS. 10 and 11, It is possible to obtain different electrical characteristics depending on the gate in one device.

FIG. 10 shows a state in which a constant voltage is applied to the second gate 92 in a semiconductor device having an asymmetric dual gate structure (FIG. 8) according to an embodiment of the present invention, FIG. 11 is an electrical characteristic diagram showing a drain current characteristic with respect to a voltage change of the first gate 52 in the first gate 52. Conversely, FIG. FIG. 5 is an electrical characteristic diagram showing drain current characteristics with respect to a voltage change of the second gate 92 in an applied state.

Therefore, according to the semiconductor device having the asymmetric dual gate structure of the present invention as shown in FIG. 8, a memory device having both volatile / nonvolatile characteristics as a single device, a TFET (tunneling field effect transistor) capable of easily adjusting a threshold voltage, And a synaptic mimic element capable of short-term memory switching.

Here, when implemented with a TFET (tunneling field effect transistor) device, the source region 24 and the drain region 26 have opposite conductivity types.

When the semiconductor substrate is formed as an SOI substrate, the first gate 52 and the second gate insulating film 80 may be formed on the buried insulating film 10, as shown in FIG.

Hereinafter, a method of manufacturing a semiconductor device having an asymmetric dual gate structure according to an embodiment of the present invention will be described with reference to FIGS. 1 to 9. FIG.

First, as shown in FIG. 1, a hard mask 30 is formed on the SOI substrate 20, and the silicon layer 20 of the SOI substrate is etched to form the first gate groove 12 ).

At this time, the hard mask 30 is filled with a gate material for the first gate 12 and can serve as an etch mask when etched. Therefore, any material having a gate material and an etch selectivity ratio can be used An oxide layer 32 and a nitride layer 34 are sequentially formed on the SOI substrate 20 as shown in FIG. In the latter case, the uppermost nitride 34 functions as an etching stopper when the CMP process is performed in the subsequent planarization process.

1, a hard mask 30 is formed so that a first gate contact groove 14 is formed at one side of the first gate groove 12, and a silicon layer 20 of the SOI substrate is formed, Is preferably etched.

1, the hard mask 30 having the uppermost layer as the nitride layer 34 is formed, and then the silicon layer 20 of the SOI substrate is etched to form the grooves 12 for the first gate and the 1 is a plan view of the gate contact groove 14, and FIG. 1 (b) is an enlarged cross-sectional view taken along the line AA of FIG. 1 (a).

2, the silicon layer 20 exposed at the side of the first gate groove 12 is oxidized to form a first gate oxide film 40, The first gate 52 is formed by filling the groove for one gate 12 (second step).

2 (b), the first gate oxide film 40 is formed on the oxide film 40 of the hard mask 30 as well as the silicon layer 20 exposed on the side of the first gate groove 12 in FIG. The silicon layer 20 in contact with the silicon oxide film 32 may be formed of a silicon oxide film.

When the first gate contact groove 14 is also formed in the first step, the first gate material is filled in the first gate contact groove 14 to form the first gate contact 14, A pad 54 is also formed.

In this case, the first gate material may be polysilicon or amorphous silicon. After the first gate material is deposited to a predetermined thickness, a planarization process is performed to expose the hard mask 30 as shown in FIG. 2 (b) . The planarization process preferably proceeds to a known CMP process, wherein the uppermost nitride 34 of the hard mask 30 functions as an etch stopper, as described above.

Thereafter, as shown in FIG. 3, the hard mask 30 is removed (step 3). The nitride layer 34 of the hard mask 30 may be removed by dry et and the oxide layer 32 of the hard mask 30 may be removed by wet etch by hydrofluoric acid.

4, an insulating film is deposited on the entire surface of the substrate where the first gate 52 and the first gate contact pad 54 protrude by removing the hard mask 30 and is anisotropically etched to form a first gate 52 and the first gate contact pad 54 (step 4).

At this time, the insulating film sidewall 60 is preferably etched by depositing an oxide film by LPCVD to form sidewalls having a thickness of about 40 nm. This is because a fin body having a thin thickness can be formed using the insulating film side wall 60 as an etching mask in a subsequent process.

5, an etching mask 70 for defining an active region is formed on the silicon layer 20 facing the one side of the first gate 52 (step 5).

5, the etch mask 70 may be formed so as to cover both the source / drain regions 24 and 26 and the portion where the fin body 22 is to be formed, but the fin body 22 May be formed to cover only the source / drain regions 24 and 26, using the insulating film side wall 60 as an etching mask.

6, the silicon layer 20 is etched with the etch mask 70 to form active regions 24 and 26 connected to the fin body 22 (step 6).

6, the fin body 22 is formed by using the insulating film sidewall 60 as an etching mask as described above, and the fin body 22 is formed using the insulating film side wall 60 as an etching mask as described above. .

Next, as shown in FIG. 7, a second gate insulating layer 80 and a second gate material 90 are deposited on the entire surface of the substrate and etched to form a second gate 92 (Step 7).

At this time, the second gate insulating layer 80 may be formed of a single layer such as a silicon oxide layer as in the first gate oxide layer 40, but may have a stacked structure of two or more material layers including a charge storage layer, / Nitride / oxide film to have a different material from that of the first gate oxide film 40 and a laminated structure are preferable from the viewpoint of utilization of the device as described above. According to the present embodiment, the second gate insulating layer 80 is deposited on the entire surface of the substrate, which has been advanced, so that even if two or more material layers are sequentially stacked, it is easy to form a stacked structure.

The second gate material 90 may be polysilicon or amorphous silicon as well as the first gate material. The second gate material 90 may be deposited on the entire surface of the substrate to a predetermined thickness, The second gate 92 can be formed by a planarization process such as a CMP process.

9, the first gate 52 and the second gate 92 are etched to expose the active regions 24 and 26, and ion implantation is performed to expose the source region 24 and the drain region 26 (Step 8).

At this time, if the device to be manufactured is a general MOSFET structure, the active regions 24 and 26 are exposed and at the same time, the implant process is performed. In the case of a TFET, another type of dopant is implanted one by one, (24) and a drain region (26).

The other process steps and the like described above can be performed according to the manufacturing process of a general MOSFET or TFET, so that further explanation is omitted.

10: buried insulating film 12: groove for first gate
14: groove for first gate contact 20: SOI substrate (silicon layer)
22: pin body 24: source region
26: drain region 30: hard mask
32: oxide film 34: nitride
40: first gate insulating film 52: first gate
54: first gate contact pad 60: insulating film side wall
70: etching mask 80: second gate insulating film
92: second gate 94: second gate contact pad

Claims (9)

A source region and a drain region spaced apart from the semiconductor substrate by a predetermined distance;
A fin body connecting the source region and the drain region;
A first gate formed on one side of the pin body with a first gate insulating film interposed therebetween;
An insulating film side wall formed on the pin body and on one side of the first gate; And
And a second gate formed on the sidewall of the insulating film and on the opposite side of the pin body with a second gate insulating film interposed therebetween,
Wherein one of the first gate insulating film and the second gate insulating film is formed of a single material layer and the other is formed of a stacked structure of two or more material layers including a charge storage layer Semiconductor device.
The method according to claim 1,
Wherein the first gate insulating film is a silicon oxide film,
Wherein the second gate insulating layer is formed of a stacked structure of an oxide layer, a nitride layer, and an oxide layer.
The method according to claim 1,
Wherein the source region and the drain region have opposite conductivity types.
4. The method according to any one of claims 1 to 3,
Wherein the semiconductor substrate is an SOI substrate,
Wherein the first gate and the second gate insulating film are formed on the buried insulating film.
A first step of forming a hard mask on an SOI substrate and etching a silicon layer of the SOI substrate to form a groove for a first gate;
A second step of oxidizing the silicon layer exposed at the side of the first gate groove to form a first gate oxide film and filling the first gate material with the first gate material to form a first gate;
A third step of removing the hard mask;
A fourth step of depositing an insulation film on the entire surface of the SOI substrate and etching the insulation film to form a side wall of the insulation film on the side of the first gate;
A fifth step of forming an etch mask for defining an active region in the silicon layer facing one side of the first gate;
A sixth step of etching the silicon layer with the etching mask to form an active region connected to a fin body;
Depositing a second gate insulating film and a second gate material over the entire surface of the SOI substrate and etching the second gate insulating film to form a second gate; And
And etching the first gate and the second gate to expose the active region and implant ions to form a source / drain region,
Wherein the second gate insulating film in the seventh step is formed in a stacked structure of two or more material layers including a charge storage layer.
6. The method of claim 5,
The first step may include forming a first gate contact groove on one side of the first gate groove,
The second step may include depositing the first gate material to a predetermined thickness, etching the second gate material by a planarization process so that the hard mask is exposed,
Wherein the second gate material is deposited to a predetermined thickness and then etched by a planarization process to expose the second gate insulation layer.
The method according to claim 6,
The sidewall of the insulating film in the fourth step is etched after the oxide film is deposited by LPCVD. In the sixth step, the sidewall is used as an etch mask for forming a fin body,
Wherein the etching mask in the fifth step is formed only on the source / drain regions.
delete 8. The method according to any one of claims 5 to 7,
The hard mask is formed by sequentially stacking an oxide film and a nitride on the SOI substrate,
Wherein the first gate material and the second gate material are polysilicon or amorphous silicon,
Wherein the second gate insulating film is formed of a laminated structure of an oxide film, a nitride film, and an oxide film.

Images