KR101066495B1 - LCD and Inspection Method - Google Patents

Abstract

The present invention relates to a liquid crystal display device which can reduce the cost by reducing the number of switching elements of the data line inspection unit and can determine the quantity / defect of the demultiplexer, and is defined by gate lines and data lines crossing each other. A display unit having pixels in a matrix form; A data line inspecting unit supplying a test data voltage to be supplied to the data lines through fewer output lines than the data lines; And a plurality of switching elements in which a plurality of control signals input with a time difference from the outside are individually applied to the gate electrode, a source terminal is commonly connected to the output line, and a drain terminal is individually connected to each data line. It is characterized by including a plurality of demultiplexer having.

LCD, Demultiplexer, Gate Line Inspector, Data Line Inspector

Description

A liquid crystal display device and a method for testing the same}

1 is a block diagram of a conventional liquid crystal display device

FIG. 2 is a detailed circuit diagram of the demultiplexer unit shown in FIG.

3 is a drive waveform diagram of the first demultiplexer shown in FIG. 2 in any horizontal synchronization period;

4 is a configuration diagram of a liquid crystal display device having a gate line inspector and a data line inspector according to the related art.

5 is a configuration diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

6 is a detailed configuration diagram of FIG.

* Explanation of symbols on the main parts of the drawings

501: Gate Driver 502: Data Driver

503: gate line inspection unit 504: data line inspection unit

505: demultiplexer 506: timing controller

GL1 to GLm: gate lines DL1 to DLn: data lines

OL1 to OLk: output line 555: display unit

500: liquid crystal panel

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and a driving method thereof, and more particularly, to a liquid crystal display device and an inspection method thereof capable of determining a quantity / defect of a demultiplexer unit.

Conventional liquid crystal displays display an image corresponding to a video signal (hereinafter, data voltage) by using a display unit having a plurality of pixels defined by gate lines and data lines that cross each other. Each pixel of the display unit includes a liquid crystal cell that adjusts light transmittance according to a corresponding data voltage, and a thin film transistor that switches a data voltage to be supplied from the data line to the liquid crystal cell. In addition, the liquid crystal display includes a gate and a data driver for driving a gate line and a data line. These gate and data drivers are embedded in the liquid crystal panel when the thin film transistor uses polysilicon having high charge mobility. In this case, a demultiplexer portion is connected between the data driver and the display portion. The demultiplexer unit reduces a requirement of a drive IC (Integrated Circuit) constituting the data driver by connecting a plurality of data lines to any one output line of the data driver.

Hereinafter, a conventional liquid crystal display device having a demultiplexer unit will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a conventional liquid crystal display device.

In the conventional liquid crystal display, as shown in FIG. 1, m × n pixels are arranged in a matrix type, m gate lines GL through GLn and n data lines DL1 through DLn are vertically crossed. A display unit 111 having a thin film transistor TFT formed at an intersection thereof, a gate driver 101 for supplying a scan pulse voltage SP to the gate lines GL1 to GLm, and the display unit 111. A data driver 102 for supplying the data voltages VD1 to VDk to the data lines DL to DLn, a demultiplexer unit 105 connected between the display unit 111 and the data driver 102, And a timing controller 106 for controlling the gate driver 101, the data driver 102, and the demultiplexer unit 105.

The timing controller 106 generates and supplies a plurality of control signals for controlling the driving timing of the gate driver 101 and the data driver 102, and aligns and supplies the pixel data to the data driver 102. In addition, the timing controller 106 generates and supplies a plurality of control signals for controlling the demultiplexer 105.

The output lines OL1 to OLk connecting the data driver 102 and the demultiplexer unit 105 have a smaller number than the number of the data lines DL to DLn. Here, the output lines OL1 to OLk are connected to output pins (not shown) of the data driver 102, and the number of output lines OL1 to OLk and output pins is equal to k.

Here, the demultiplexer 105 will be described in more detail as follows.

FIG. 2 is a detailed circuit diagram of the demultiplexer portion shown in FIG. 1, and FIG. 3 is a drive waveform diagram of the first demultiplexer shown in FIG. 2 in any horizontal synchronizing period.

As shown in FIG. 2, the demultiplexer 105 may include k demultiplexers DEMUX1 to DEMUXk connected between the data driver 102 and the n data lines DL to DLn of the display 111. Equipped. Each of the demultiplexers DEMUX1 to DEMUXk includes first to third switching devices SW1 to SW3 connected in parallel to one output line and connected to each of three data lines of the data lines DL to DLn. Equipped. The first to third switching devices SW1 to SW3 are turned on at different times in one horizontal period by the first to third control signals C1 to C3 supplied from the timing controller 106.

The gate driver 101 sequentially supplies the scan pulse voltage SP to the m gate lines GL1 to GLm during one frame. As shown in FIG. 3, the gate high voltage VGH, which is the high logic voltage of the scan pulse voltage SP, is maintained for a horizontal synchronizing period as long as the corresponding gate line is driven.

Here, the gate high voltage VGH is a high logic voltage of the scan pulse voltage SP that is set to be equal to or greater than the threshold voltage of the thin film transistor TFT, and the gate low voltage VGL is a scan set to an off voltage of the thin film transistor TFT. It is the low logic voltage of the pulse voltage SP.

That is, during the horizontal synchronizing period Hi, in which any gate line is driven, the data driver 102 receives the first through the k output lines OL1 through OLk connected to each of the k demultiplexers DEMUX1 through DEMUXk. K data voltages VD1 to VDk are sequentially supplied so as to synchronize with each of the third control signals C1 to C3. Then, each of the demultiplexers DEMUX1 to DEMUXk receives three data voltages VD1 to VDk sequentially supplied through corresponding output lines OL1 to OLk from the first to third control signals from the timing controller 106. In response to C1 to C3), three data lines are supplied.

For example, the gate electrode of the first switching device SW1 formed in each of the k demultiplexers DEMUX1 to DEMUXk may be formed of the signal input line IL of the first control signal C1 and the second switching device SW2. The gate electrode is connected to the signal input line IL of the second control signal C2 and the gate electrode of the third switching device SW3 is connected to the signal input line IL of the third control signal C3, respectively. Accordingly, when the first to third control signals C1 to C3 are supplied with the high state sequentially shifted in one horizontal synchronizing period Hi, as shown in FIG. 3, the demultiplexers DEMUX1 to DEMUXk. Each of the first to third switching devices SW1 to SW3 is driven in the order of the first switching device SW1, the second switching device SW2, and the third switching device SW3. The data driver 102 sequentially supplies the corresponding data voltages VD1 to VDk in correspondence with the driving order of the first to third switching devices SW1 to SW3. As a result, as shown in FIG. 3, the first demultiplexer DEMUX1 supplies the data voltage for R (Red) to the first data line DL1 through the first switching device SW1 and the second switching device. The data voltage for G (Green) is sequentially applied to the second data line DL2 through SW2, and the data voltage for B (Blue) is sequentially transmitted to the third data line DL3 through the third switching device SW3. To supply.

Here, the display unit 111, the gate driver 101 for driving the display unit 111, the data driver 102, and each of the multiplexers DEMUX1 to DEMUXk are embedded in the liquid crystal panel 100. The data driver 102 is mounted on the liquid crystal panel 100 in a chip form (COG method: Chip On Glass). The timing controller 106 is provided outside the liquid crystal panel 100.

On the other hand, in order to check whether the image according to the data voltage (VD1 to VDk) is properly represented in each pixel, the conventional liquid crystal display device has a gate line inspection unit and data for checking whether the gate line (GL1 to GLm) abnormality It may include a data line inspecting unit for checking whether the lines DL1 to DLn are abnormal.

Hereinafter, a liquid crystal display having a conventional gate line inspector and a data line inspector will be described in detail.

4 is a configuration diagram of a liquid crystal display device having a gate line inspector and a data line inspector according to the related art.

In the conventional LCD, as shown in FIG. 4, m × n pixels are arranged in a matrix type, and m gate lines GL1 to GLm and n data lines DL1 to DLn cross each other vertically. A display unit 111 having a thin film transistor TFT formed at an intersection thereof, a gate driver 101 for supplying a scan pulse voltage SP to the gate lines GL1 to GLm, and a data line of the display unit 111; A data driver (102 in FIG. 3) for supplying the data voltages VD1 to VDk to the DL1 to DLn, and a plurality of demultiplexers DEMUX1 to DEMUXk connected between the display unit 111 and the data driver 102. ), The timing driver 106 for controlling the gate driver 101, the data driver 102, and each of the demultiplexers DEMUX1 to DEMUXk, and the gate lines GL1 to GLm of the display unit 111 for testing. Supply scan pulse voltage (VT1) The gate line inspection unit 403 to check whether the gate lines GL1 to GLm are abnormal, and a test data voltage VT2 is supplied to the data lines DL to DLn of the display unit 111 to supply the test data voltage VT2. And a data line checking unit 404 for checking whether or not the DL to DLn is abnormal.

Here, each of the demultiplexers DEMUX1 to DEMUXk has the same configuration as that of FIG. 2.

The gate line inspecting unit 403 is connected to one end of the gate lines GL1 to GLm, and the gate driver 101 is connected to the other end of the gate lines GL1 to GLm. Here, the gate line inspecting unit 403 applies a test scan pulse voltage VT1 to the gate lines GL1 to GLm to test drive the gate lines GL1 to GLm, and the gate driver 101 The scan pulse voltage SP is sequentially supplied to the gate lines GL1 to GLm to sequentially drive the gate lines GL1 to GLm.

The data line inspecting unit 404 is connected to one end of the data lines DL1 to DLn, and the data driver 102 is connected to the data lines DL1 to DLn through the respective demultiplexers DEMUX1 to DEMUXk. It is connected to the other end of.

Here, the gate line inspecting unit 403 and the data line inspecting unit 404 will be described in more detail as follows.

First, the gate line inspecting unit 403 supplies m test lines for supplying a test scan pulse voltage SP to the m gate lines GL1 to GLm in response to a fourth control signal C4 from the outside. It consists of 4 switching elements SW4. That is, one fourth switching device SW4 is connected to one gate line. Specifically, each gate terminal of the fourth switching device SW4 is connected in parallel to each other to receive the fourth control signal C4 in common, and each drain terminal is individually provided to each gate line GL1 to GLm. Each source terminal is connected in parallel to each other, and the test scan pulse voltage VT1 is commonly applied.

In addition, the data line inspecting unit 404 outputs the n scan switching voltages VT2 to the data lines DL1 to DLn in response to the fifth control signal C5 from the outside. SW5). Specifically, each gate terminal of each of the fifth switching elements SW5 is connected in parallel to each other to receive the fifth control signal C5 in common, and each source terminal is individually provided to each of the data lines DL1 to DLn. The drain terminals are connected in parallel to each other and receive the test data voltage VT2 in common.

Meanwhile, as described above, the gate line inspecting unit 403 and the data line inspecting unit 404 are used to inspect whether the gate lines GL1 to GLm and the data lines DL to DLn are abnormal. When the inspector 403 and the data line inspector 404 operate, the gate driver 101 and the data driver 102 do not operate. That is, the gate line inspecting unit 403 and the data line inspecting unit 404 operate the gate driver 101 and the data driver 102 before actually operating the liquid crystal display device. ) And a test unit for experimentally operating the data lines DL to DLn. Therefore, the gate driver 101 and the data driver 102 do not operate while the gate line inspector 403 and the data line inspector 404 are in operation.

Of course, the gate line inspecting unit 403 and the data line inspecting unit 404 stop operation while the gate driver 101, the data driver 102, and the timing controller 106 operate.

Meanwhile, the display unit 111, the gate driver 101 for driving the display unit 111, the data driver 102, the gate line inspecting unit 403, the data line inspecting unit 404, and the demultiplexer unit 105. Is embedded in the liquid crystal panel 100. In particular, the data driver 102 is mounted on the liquid crystal panel 100 in the form of a chip. The timing controller 106 is provided outside the liquid crystal panel 100.

Here, the inspection process of the gate lines GL1 to GLm and the data lines DL to DLn is performed before the data driver 102 and the timing controller 106 are mounted. Therefore, the gate driver 101 and the data driver 102 cannot operate during the inspection process.

In the conventional liquid crystal display configured as described above, the test scan pulse voltage VT1 is simultaneously applied to all the gate lines GL1 to GLm, and the test data voltage is simultaneously applied to all the data lines DL to DLn. Since the VT2 is applied, the thin film transistors TFTs of all the pixels of the display unit 111 are turned on at the same time, thereby displaying all the pixels according to the test data voltage VT2. . In this case, the test data voltages VT2 having the same magnitude are supplied to each of the pixels, and thus the same image is displayed on all the pixels. Therefore, the display section 111 displays an image showing one gray scale.

In this case, the screen line of the display unit 111 may be inspected to determine whether the gate line, the data line, and the pixel are abnormal.

That is, if an image is not displayed in pixels arranged horizontally along a portion of an arbitrary gate line, it may be determined that the arbitrary gate line is disconnected, and pixels arranged along a portion of an arbitrary data line vertically. If no image is displayed on the screen, it can be determined that the arbitrary data line is disconnected.

In addition, if a specific pixel does not display an image, it may be determined that the thin film transistor provided in the specific pixel has malfunctioned.

However, the conventional liquid crystal display has the following problems.

That is, conventionally, the gate line inspecting unit 403 and the data line inspecting unit 404 use the gate lines GL1 through GLm and the data lines DL through DLn or thin film transistors provided in the pixels. Although it was possible to confirm the abnormality of the TFT, there was no method for confirming whether the first to third switching elements SW1 to SW3 included in each of the demultiplexers DEMUX1 to DEMUXk were abnormal.

Accordingly, the gate lines GL1 through GLm, the data lines DL through DLn, and the thin film transistor TFT are all normally operated by the gate line inspector 403 and the data line inspector 404. Even if it is determined, the data voltages VD1 to VDk from the data driver 102 during the actual driving are caused by the operation of the first to third switching devices SW1 to SW3 provided in each of the demultiplexers DEMUX1 to DEMUXk. The first to third switching devices SW1 to SW3, which are provided in each of the demultiplexers DEMUX1 to DEMUXk, are applied to each of the data lines DL to DLn. In many cases, images could not be represented properly due to abnormalities.

The present invention has been made to solve the above problems, the liquid crystal display that can determine whether the data line and the switching device provided in the demultiplexer unit as well as the data line inspection unit between the data driver and the demultiplexer unit. It is an object of the present invention to provide an apparatus and a method of inspecting the same.

According to an aspect of the present invention, there is provided a liquid crystal display device including: a display unit having pixels in matrix form defined by gate lines and data lines that cross each other; A data line inspecting unit supplying a test data voltage to be supplied to the data lines through fewer output lines than the data lines; And a plurality of switching elements in which a plurality of control signals input with a time difference from the outside are individually applied to the gate electrode, a source terminal is commonly connected to the output line, and a drain terminal is individually connected to each data line. It is characterized by including a plurality of demultiplexer having.

According to an exemplary embodiment of the present invention, an inspection method of a liquid crystal display device includes: a display unit having pixels in matrix form defined by gate lines and data lines crossing each other, and to be supplied to the data lines; A data line inspection unit for supplying a test data voltage through fewer output lines than the data lines, and a plurality of control signals input at a time difference from the outside are individually applied to the gate electrode, and are commonly applied to the output lines. A method of inspecting a liquid crystal display including a plurality of demultiplexers having a plurality of switching elements having a source terminal connected thereto and a drain terminal individually connected to each data line, wherein the data voltage for the test from the data line inspecting unit is determined. Through the switching element provided in the demultiplexer And that to be supplied to the emitter line with its features.

Hereinafter, a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

5 is a configuration diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

In the liquid crystal display according to the exemplary embodiment of the present invention, as shown in FIG. 5, m × n pixels are arranged in a matrix type, m gate lines GL1 to GLm, and n data lines DL1 to DLn. ) Is vertically crossed and a display unit 555 having a thin film transistor TFT formed at an intersection thereof, a gate driver 501 for supplying a scan pulse voltage SP to the gate lines GL1 to GLm, and the display unit. The data driver 502 for supplying the data voltages VD1 to VDk to the data lines DL1 to DLn of 555, and the test scan pulse voltage VT1 to the gate lines GL1 to GLm. A gate line inspector 503, a data line inspector 504 for supplying a test data voltage VT2 to the data lines DL1 through DLn, the data line inspector 504, and the display unit Demultiplexer portion 505 connected between 555 And a timing controller 506 for controlling the gate driver 501, the data driver 502, and the demultiplexer unit 505.

Here, the timing controller 506 generates and supplies a plurality of control signals for controlling driving timings of the gate driver 501 and the data driver 502, and aligns and supplies pixel data to the data driver 502. . The timing controller 506 generates and supplies a plurality of control signals for controlling the demultiplexer unit 505.

The gate line inspector 503 is connected to one end of the gate lines GL1 to GLm, and the gate driver 501 is connected to the other end of the gate lines GL1 to GLm. Here, the gate line inspector 503 applies the test scan pulse voltage VT1 to the gate lines GL1 to GLm to drive the gate lines GL1 to GLm, and the gate driver 501 The scan pulse voltage SP is sequentially supplied to the gate lines GL1 to GLm to sequentially drive the gate lines GL1 to GLm.

The output lines OL1 to OLk connecting the data line inspecting unit 504 and the demultiplexer unit 505 have a smaller number than the number of the data lines DL1 to DLn. Here, the output lines OL1 to OLk are connected to output pins (not shown) of the data driver 502, and the number of output lines OL1 to OLk and output pins is equal to k.

Here, the demultiplexer 505, the gate line inspector 503, and the data line inspector 504 will be described in more detail as follows.

FIG. 6 is a detailed configuration diagram of FIG. 5.

First, as shown in FIG. 6, the demultiplexer unit 505 is connected between the data line inspecting unit 504 and the n data lines DL1 to DLn of the display unit 555. Two demultiplexers (DEMUX1 to DEMUXk). Each of the demultiplexers DEMUX1 to DEMUXk connects first to third switching devices SW1 to SW3 connected in parallel to one output line and connected to each of three data lines of the data lines DL1 to DLn. Equipped. The first to third switching devices SW1 to SW3 are turned on at different times in one horizontal period by the first to third control signals C1 to C3 supplied from the timing controller 506.

The gate driver 501 sequentially supplies the scan pulse voltage SP to the m gate lines GL1 to GLm during one frame. As shown in FIG. 3, the gate high voltage VGH, which is the high logic voltage of the scan pulse voltage SP, is maintained for a horizontal synchronizing period as long as the corresponding gate line is driven.

Here, the gate high voltage VGH is a high logic voltage of the scan pulse voltage SP that is set to be equal to or greater than the threshold voltage of the thin film transistor TFT, and the gate low voltage VGL is a scan set to an off voltage of the thin film transistor TFT. It is the low logic voltage of the pulse voltage SP.

That is, during the horizontal synchronizing period Hi, in which any gate line is driven, the data driver 502 receives the first through the first through k output lines OL1 through OLk connected to each of the k demultiplexers DEMUX1 through DEMUXk. The k data voltages VD1 to VDk are sequentially outputted so as to synchronize with each of the three control signals C1 to C3. Then, each of the demultiplexers DEMUX1 to DEMUXk receives three data voltages VD1 to VDk sequentially supplied through corresponding output lines OL1 to OLk from the first to third control signals from the timing controller 506. In response to (C1 to C3), it supplies to each of the three data lines DL1 to DLn.

For example, the gate electrode of the first switching device SW1 configured in each of the demultiplexers DEMUX1 to DEMUXk includes the signal input line IL of the first control signal C1 and the gate of the second switching device SW2. The electrode is connected to the signal input line IL of the second control signal C2 and the gate electrode of the third switching element SW3 is connected to the signal input line IL of the third control signal C3, respectively. Accordingly, when the first to third control signals C1 to C3 are supplied with the high state sequentially shifted within one horizontal synchronizing period, as shown in FIG. 3, each of the demultiplexers DEMUX1 to DEMUXk is formed. The first to third switching devices SW1 to SW3 are driven in the order of the first switching device SW1, the second switching device SW2, and the third switching device SW3. The data driver 502 sequentially outputs the data voltages VD1 to VDk corresponding to the driving order of the first to third switching devices SW1 to SW3. As a result, each of the demultiplexers DEMUX1 to DEMUXk receives the data voltage for R (Red) from the first data line DL1 to the first data line DL1 through the first switching device SW1 and the second through the second switching device SW2. The data voltage for G (Green) is supplied to the data line DL2, and the data voltage for B (Blue) is sequentially supplied to the third data line DL3 through the third switching device SW3.

The gate line inspecting unit 503 supplies the m scan lines for supplying the test scan pulse voltage VT1 to the m gate lines GL1 to GLm in response to a fourth control signal C4 from the outside. It consists of 4 switching elements SW4. That is, one fourth switching device SW4 is connected to one gate line. Specifically, each gate terminal of the fourth switching device SW4 is connected in parallel to each other to receive the fourth control signal C4 in common, and each drain terminal is individually provided to each gate line GL1 to GLm. Each source terminal is connected in parallel to each other, and the test scan pulse voltage VT1 is commonly applied.

The data line inspecting unit 504 outputs the test data voltage VT2 to the output lines OL1 to OLk in response to the fifth control signal C5 from the outside. It consists of). Specifically, each gate terminal of the fifth switching device SW5 is connected in parallel to each other to receive the fifth control signal C5 in common, and each drain terminal is connected to each of the output lines OL1 to OLk. The drain terminals are connected individually and connected in parallel to each other so that the test data voltage VT2 is commonly applied.

The gate line inspecting unit 503 and the data line inspecting unit 504 are used to inspect abnormalities of the gate lines GL1 to GLm and the data lines DL1 to DLn of the liquid crystal display. When the 503 and the data line inspector 504 operate, the gate driver 501 and the data driver 502 do not operate. That is, the gate line inspecting unit 503 and the data line inspecting unit 504 operate the gate driver 501 and the data driver 502 before actually operating the liquid crystal display device. ) And the data lines DL1 to DLn for a test operation. Therefore, the gate driver 501 and the data driver 502 do not operate while the gate line inspector 503 and the data line inspector 504 operate.

Of course, during the real driving, the gate line inspecting unit 503 and the data line inspecting unit 504 stop operation, and the gate driver 501, the data driver 502, and the timing controller 506 operate.

Meanwhile, the display unit 555, the gate driver 501, the data driver 502, the gate line inspecting unit 503, the data line inspecting unit 504, and the demultiplexer unit 505 for driving the display unit 555. Is embedded in the liquid crystal panel 500. In particular, the data driver 502 is mounted on the liquid crystal panel 500 in the form of a chip (COG actual method; Chip On Glass). The timing controller 506 is provided outside the liquid crystal panel 500.

Here, the inspection process of the gate lines GL1 to GLm and the data lines DL1 to DLn is performed before the data driver 502 and the timing controller 506 are mounted. Therefore, the gate driver 501 and the data driver 502 cannot operate during the inspection process. In addition, since the timing controller 506 is not mounted in the test process, the sixth to eighth control signals C6 to C8 from the outside are input to each signal input line IL. The sixth to eighth control signals C6 to C8 also have the same characteristics as the first to third control signals C1 to C3 output from the timing controller 506.

A method of checking whether the gate lines GL1 to GLm, the data lines DL1 to DLn, and the pixel are abnormal in the liquid crystal display according to the exemplary embodiment of the present invention configured as described above will be described in detail.

First, as described above, the timing controller 506 and the data driver 502 are not yet mounted in the liquid crystal display, and the gate driver 501 is not in operation.

In this state, the fourth control signal C4 is supplied to the gate line inspector 503. Then, the fourth switching device SW4 of the gate line inspecting unit 503 is turned on in response to the fourth control signal C4, and the turned-on fourth switching device SW4 is scanned for test. The pulse voltage VT1 is simultaneously supplied to the gate lines GL1 to GLm. Therefore, the thin film transistors TFTs of all the pixels connected to the gate lines GL1 to GLm are turned on.

Next, the fifth control signal C5 is supplied to the data line inspecting unit 504. Then, each fifth switching device SW5 of the data line inspecting unit 504 outputs the test data voltage VT2 in response to the fifth control signal C5 and supplies the same to the demultiplexers DEMUX1 to DEMUXk. do. That is, k test data voltages VT are supplied to k demultiplexes DEMUX1 to DEMUXk through k output lines OL1 to OLk, respectively. Specifically, the test data voltage VT2 is applied to the first to third switching devices SW1 to SW3 provided in the demultiplexers DEMUX1 to DEMUXk.

In this case, the first to third switching devices SW1 to SW3 provided in each of the demultiplexers DEMUX1 to DEMUXk are different from each other by sixth to eighth control signals C6 to C8 sequentially applied from the outside. The first to third switching devices SW3 which are turned on at the same time are sequentially supplied to the data lines DL1 to DLn for the test data voltage VT2.

Here, the sixth to eighth control signals C6 to C8 may be applied as signals having the same DC value. That is, in the inspection process, all of the first to third switching devices SW1 to SW3 may be turned on at the same time. This is because the test data voltages VT2 supplied to each of the data lines DL1 to DLn have the same size.

The test data voltage VT2 supplied to the data lines DL1 to DLn is supplied to each pixel through the turned-on thin film transistor TFT. Accordingly, the entire display unit 555 displays an image corresponding to the gray value of the test data voltage VT2.

At this time, by checking the image of the display unit 555, it is possible to check whether the gate lines GL1 to GLm and the data lines DL1 to DLn are defective or disconnected.

That is, if an image is not displayed in pixels arranged horizontally along a portion of an arbitrary gate line, it may be determined that the arbitrary gate line is disconnected, and pixels arranged along a portion of an arbitrary data line vertically. If no image is displayed on the screen, it can be determined that the arbitrary data line is disconnected.

In addition, if a particular pixel does not display an image, it may be determined that an abnormality has occurred in the thin film transistor TFT provided in the specific pixel.

In addition, the test data voltage VT2 is applied to the data lines DL1 to DLn via the first to third switching devices SW1 to SW3 provided in each of the demultiplexers DEMUX1 to DEMUXk. The abnormality of the first to third switching devices SW1 to SW3 included in each of the demultiplexers DEMUX1 to DEMUXk may also be checked. That is, when an error occurs in any one of the first to third switching devices SW1 to SW3 and does not operate, the test data voltage VT2 is applied to a data line connected to the switching device in which the error occurs. The image according to the test data voltage VT2 is not displayed on all the pixels arranged vertically along the data line.

Therefore, when an image is not displayed in any one of the vertical pixel groups among the vertical pixel groups vertically arranged along the data lines DL1 through DLn, the data line DL1 arranged along the pixel groups in which the abnormality occurs. The abnormality of the switching elements SW1 to SW3 of the demultiplexers DEMUX1 to DEMUXk connected to DLn may be suspected. As a result, the liquid crystal display according to the present invention can check whether the abnormality is more specific than before.

In addition, although a large number of switching elements are conventionally required because one switching element of the data line inspecting unit 504 is connected to each data line DL1 through DLn, the switching unit provided in the data line inspecting unit 504 of the present invention is used. Since each of the elements is connected to at least two data lines DL1 to DLn in common, it may be made of fewer switching elements than before, thereby reducing costs.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

The liquid crystal display according to the present invention as described above has the following effects.

First, the data line inspecting unit outputs a test data voltage and applies it to a data line through a demultiplexer. Therefore, it is possible to check whether the switching device provided in the demultiplexer is abnormal.

Second, since the data line inspecting unit according to the present invention is connected between the data driver and the demultiplexer, each switching element included in the data line inspecting unit needs only the number of output lines connected to the output pin of the data driver. Therefore, the number of switching elements can be reduced as compared with a data line inspection unit having switching elements corresponding to the number of data lines in the related art.

Claims (7)

A display unit having pixels in matrix form defined by gate lines and data lines crossing each other; A data line inspecting unit supplying a test data voltage to be supplied to the data lines through fewer output lines than the data lines; And, A plurality of control signals inputted with a time difference from the outside are individually applied to the gate electrode, a source terminal is commonly connected to the output line, and a plurality of switching elements each having a drain terminal individually connected to each data line. And a plurality of demultiplexers. The method of claim 1, And the data line inspecting unit includes a plurality of switching elements configured to supply the test data voltage to each of the multiplexers through the output line in response to a control signal from an external device. The method of claim 1, And a gate line inspecting unit configured to generate a test scan pulse voltage for test driving the gate line, and supply the test pulse voltage to one side of the gate lines. The method of claim 3, wherein And the gate line inspecting unit includes a plurality of switching elements configured to supply the test scan pulse voltage to the gate lines in response to a control signal from an external source. The method of claim 1, And a gate driver for generating a scan pulse voltage for driving the gate line and sequentially supplying the scan pulse voltage to the other sides of the gate lines. The method of claim 1, And a data driver for outputting a data voltage for displaying an image and supplying the data voltage to the output line. A display unit having pixels in matrix form defined by gate lines and data lines crossing each other, and data for supplying test data voltages to be supplied to the data lines through fewer output lines than the data lines. A plurality of switching lines in which a line inspection unit and a plurality of control signals inputted from the outside with time difference are individually applied to the gate electrode, a source terminal is commonly connected to the output line, and a drain terminal is individually connected to each data line. In the inspection method of a liquid crystal display device comprising a plurality of demultiplexers having elements, And a data voltage for the test from the data line inspecting unit is supplied to the data line through a switching element provided in the demultiplexer.

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