KR101036692B1 - Fabrication method of multi quantum dot nanodevices and multi-quantum dot nano device accordingly - Google Patents

Abstract

The present invention relates to a method for manufacturing a multi-quantum dot nano device, and more particularly, to a method for manufacturing a multi-quantum dot using an electron beam photosensitive film, in particular, a negative electron beam photosensitive film (Negative Electron-beam Resist (NER)), and thus The present invention relates to a manufactured multi-quantum dot nanodevice. A method of fabricating a multi-quantum dot nano device according to the present invention includes forming a conductive channel on an upper silicon layer of an SOI substrate in which a silicon oxide film and an upper silicon layer are sequentially stacked on a lower silicon substrate; Doping impurities in regions other than the conductive channels to form source and drain regions; Depositing a silicon oxide film over the SOI substrate to form a lower gate oxide film; Forming at least one micropattern to be orthogonal to the conducting channel; Stacking a polysilicon layer on an upper surface of the SOI substrate; Forming a lower gate of a polysilicon line on the side of the fine pattern; Forming an upper gate oxide film on an upper surface of the SOI substrate; And forming an upper gate by depositing a metal on the upper gate oxide layer.

QD, electron beam photosensitive film

Description

Fabrication method of multi-quantum dot nanodevices and multi-quantum dot nanodevices according thereto

1 is a perspective view showing a multi-quantum dot nano device according to the present invention,

2 is a perspective view showing a state in which a conductive channel of a nanometer scale is formed in an upper silicon layer during a manufacturing process of a multi-quantum dot nano device according to the present invention;

3 is a cross-sectional view taken along the line A-A of FIG.

4 is a perspective view showing a state in which a lower gate oxide film is formed during a manufacturing process of a multi-quantum dot nano device according to the present invention;

5 is a cross-sectional view taken along line B-B of FIG. 4;

6 is a perspective view showing a state in which a fine pattern is formed during the manufacturing process of the multi-quantum dot nano device according to the present invention;

7 is a cross-sectional view taken along the line C-C of FIG.

8 is a perspective view showing a state in which a polysilicon layer is laminated during the manufacturing process of the multi-quantum dot nano device according to the present invention;

9 is a cross-sectional view taken along the line D-D of FIG. 8;

10 is a perspective view showing a state in which a polysilicon line is formed during a manufacturing process of a multi-quantum dot nano device according to the present invention;

11 is a cross-sectional view taken along the line E-E of FIG.

12 is a perspective view showing a state in which an upper gate oxide film is formed during a manufacturing process of a multi-quantum dot nano device according to the present invention;

13 is a cross-sectional view taken along the line F-F of FIG.

14 is a perspective view showing a state in which an upper gate is formed during a manufacturing process of a multi-quantum dot nano device according to the present invention;

15 is a cross-sectional view taken along the line G-G of FIG. 14;

FIG. 16 is a schematic conceptual view of double quantum dots formed in a conduction channel of a multi-quantum dot nano device according to the present invention.

<Explanation of symbols for the main parts of the drawings>

1: Underlayer Silicon Substrate

2: silicon oxide film

3: upper silicon layer

4: lower gate oxide film

5: first fine pattern

6: second fine pattern

7: third fine pattern

8: polysilicon layer

8a: first polysilicon line (lower layer gate)

8b: second polysilicon line (lower layer gate)

8c: third polysilicon line (lower layer gate)

8d: fourth polysilicon line (lower layer gate)

8e: fifth polysilicon line (lower layer gate)

8f: 6th polysilicon line (lower layer gate)

15: upper gate oxide film

16: upper gate
20: source
30: drain
40a: first quantum dot
40b: second quantum dot

The present invention relates to a method for manufacturing a multi-quantum dot nano device, and more particularly, to a method for manufacturing a multi-quantum dot using an electron beam photosensitive film, in particular, a negative electron beam photosensitive film (Negative Electron-beam Resist (NER)), and thus The present invention relates to a manufactured multi-quantum dot nanodevice.
As a representative method for forming a quantum dot on a commonly used silicon substrate, there has been a technique of manufacturing a quantum dot with a nanometer-scale fine pattern by applying an electron beam lithography technique. However, this method is suitable for forming a single quantum dot using a single fine pattern, but causes a problem in manufacturing a multi-quantum dot using multiple fine patterns.
That is, when forming the multiple fine patterns, the closer the pattern interval is, the more proximity effect due to the interference and diffraction of electrons is generated, making it difficult to form a uniform pattern. As a technique to solve this problem somewhat, the side wall technique for forming an ultra fine pattern by applying the VLSI technology has no proximity effect, and there is an advantage that the current semiconductor technology can be used as it is. In order to form a multi-lamination process and an etching process according to it has to be carried out repeatedly has the disadvantage of increasing the number of processes.

The present invention relates to a method for fabricating a multi-quantum dot nanodevice, and an object of the present invention is to fuse a electron beam lithography technique and a VLSI technique to form a multi-micron pattern using an electron beam photosensitive film. To provide a device manufacturing method and a multi-quantum dot nano device manufactured thereby.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention. Prior to describing the present invention, if it is determined that a detailed description of related known functions and configurations may unnecessarily obscure the subject matter of the present invention, the description thereof will be omitted.
<Manufacturing method of multi quantum dot nano device>
1 is a perspective view of a multi-quantum dot nano device according to the present invention, Figures 2 to 15 shows a state according to the manufacturing process of the multi-quantum dot nano device according to the present invention.
First, as shown in FIGS. 2 and 3 by etching the upper silicon layer 3, which is the uppermost layer of the SOI substrate, on which the silicon oxide film 2 and the upper silicon layer 3 are formed on the lower silicon substrate 1 in order. Form conduction channels. The conduction channel can be formed by electron beam lithography or photolithography, and the conduction channel formed by this method has a scale of nanometer.
Next, the source and drain regions are formed. The source and drain regions are formed by doping impurities in the remaining regions except for the conductive channel portion of the upper silicon layer 3, which is the uppermost layer of the SOI substrate on which the conductive channel is formed.
Thereafter, the lower gate oxide film 4 may be formed to the same thickness, as shown in FIG. Therefore, the portion where the conductive channel is formed has a protruding shape. The dopant doped in the source and drain regions may be activated by a thermal oxidation process.
Next, fine patterns 5, 6, and 7 are formed. The micropatterns 5, 6, 7 may be formed in at least one, single or multiple, preferably multiple. In the present specification, for the convenience of description, a case in which three fine patterns, that is, the first fine pattern 5, the second fine pattern 6, and the third fine pattern 7 are formed will be described. As shown in FIGS. 6 and 7, the fine patterns 5, 6, and 7 are preferably formed in a shape orthogonal to the conduction channel. As a method of forming the fine patterns 5, 6, and 7, an electron beam lithography method using an electron beam photosensitive film can be used.
Thereafter, the polysilicon layer 8 is laminated. As shown in FIGS. 8 and 9, the polysilicon layer 8 may be formed by chemical vapor deposition (CVD) on the entire upper surface of the SOI substrate on which the fine patterns 5, 6 and 7 are formed. .
Next, a lower gate is formed. 10 and 11, polysilicon lines are formed on both sides of each of the fine patterns 5, 6, and 7 formed with at least one. In the present invention, a description will be given when three fine patterns 5, 6, and 7 are formed. The polysilicon lines 8a, 8b, 8c, 8d, 8e, and 8f are formed for each fine pattern 5, 6, and 7, respectively. Since two are provided each, a total of six are formed. These polysilicon lines 8a, 8b, 8c, 8d, 8e, and 8f serve as lower gates. The lower gates of the polysilicon lines 8a, 8b, 8c, 8d, 8e, and 8f are formed by etching the polysilicon layer 8 stacked in the previous step, and anisotropic etching can be used as an etching method.
Thereafter, the upper gate oxide film 15 is formed. As shown in FIGS. 12 and 13, the upper gate oxide layer 15 is formed on the entire upper surface of the SOI substrate on which the lower gate is formed. In this case, the upper gate oxide layer 15 may be formed of a silicon oxide layer.
Finally, the upper gate 16 is formed. As illustrated in FIGS. 14 and 15, the upper gate 16 is formed by depositing a metal on the upper gate oxide layer 15.
In addition, a metal layer (not shown) may be deposited under the SOI substrate formed up to the upper gate 16. That is, the metal layer is further added to the lower part of the lower silicon substrate 1 in the SOI substrate.

The step of forming the polysilicon layer 8 and the step of forming the fine patterns 5, 6 and 7 may be reversed. The steps of forming the conduction channel, forming the source and drain regions, and forming the lower gate oxide layer are the same as described above. In this embodiment, the polysilicon layer 8 is first formed on the top surface of the SOI substrate prior to forming the fine patterns 5, 6, and 7 orthogonal to the conduction channel on the lower gate oxide film 4.
Thereafter, at least one fine pattern 5, 6, 7 is formed. At this time, the method of forming the fine patterns (5, 6, 7) may be by a lithography method using an electron beam photosensitive film as mentioned above.
Subsequently, the lower gate, which is a polysilicon line, is formed by etching the polysilicon layer 8 previously formed using the fine patterns 5, 6, and 7 as a mask. As described above, the method of etching the polysilicon layer 8 may be by anisotropic etching.
Thereafter, the forming of the upper gate oxide film 15 and the forming of the upper gate 16 are as described above.

< Multi quantum dot nano device>
The multi-quantum dot nano device manufactured by the above manufacturing method has the following characteristics. The upper gate serves as a control gate. When a positive voltage is applied to the upper gate, a two-dimensional electron gas layer (2DEG) is formed at the interface of the conductive channel, and the second and fourth poly of the plurality of polysilicon lines serving as the lower gate are formed. When a negative voltage is applied to the silicon lines 8b and 8d, a tunneling barrier is formed by depleting the electrons of the two-dimensional electron gas layer formed at the interface of the conducting channel, thereby forming a single quantum dot.
When a negative voltage is applied to the first, third, and fifth polysilicon lines 8a, 8c, and 8e of the plurality of polysilicon lines that are the lower gates, as illustrated in FIG. 16, the double quantum dots 40a and 40b are formed. Is formed. At this time, the coupling between the quantum dots can be controlled according to the magnitude of the negative voltage applied to the third polysilicon line 8c, and the second and fourth polysilicon lines 8b and 8d are used as control gates of the quantum dots, respectively. It is possible.
When a positive voltage is applied to the drain, electrons move from the source 20 to the first quantum point 40a and the second quantum point 40b, causing single electron tunneling and coulomb blockage, and moving to the drain 30.

Although the present invention has been described in connection with the above-mentioned preferred embodiments, it is possible to make various modifications or variations without departing from the spirit and scope of the invention. Accordingly, the appended claims will cover such modifications and variations as long as they fall within the spirit of the invention.

Therefore, according to the method of manufacturing the multi-quantum dot nano device and the multi-quantum dot nano device of the present invention as described above, the lower gate of the second and fourth polysilicon lines serves as a control gate of the quantum dot, and thus can be utilized as a single-electron multi-function logic gate. It can be used in various ways as a quantum logic gate.

Claims (8)

Forming a conductive channel in the upper silicon layer of the SOI substrate in which a silicon oxide film and an upper silicon layer are sequentially stacked on a lower silicon substrate; Doping impurities in regions other than the conductive channel to form source and drain regions; Depositing a silicon oxide film on the SOI substrate to form a lower gate oxide film; Forming at least one fine pattern to be orthogonal to the conductive channel; Stacking a polysilicon layer on an upper surface of the SOI substrate; Forming a lower gate of a polysilicon line on a side of the fine pattern; Forming an upper gate oxide film on an upper surface of the SOI substrate; And Depositing a metal on the upper gate oxide layer to form an upper gate; The lower gate oxide film forming step is performed by a thermal oxidation process, The conducting channel forming step applies an electron beam lithography or photolithography method, The fine pattern is by an electron beam lithography method using an electron beam photosensitive film, In the lower gate forming step, the polysilicon line is formed on the side surface of the fine pattern by anisotropic etching, And depositing a metal layer under the lower silicon substrate. Forming a conductive channel in the upper silicon layer of the SOI substrate in which a silicon oxide film and an upper silicon layer are sequentially stacked on a lower silicon substrate; Doping impurities in regions other than the conductive channel to form source and drain regions; Depositing a silicon oxide film on the SOI substrate to form a lower gate oxide film; Depositing a polysilicon layer on an upper surface of the SOI substrate; Forming at least one fine pattern to be orthogonal to the conductive channel; Forming a lower gate of a polysilicon line under the fine pattern by etching the polysilicon layer using the fine pattern as a mask; Forming an upper gate oxide film on an upper surface of the SOI substrate; And Depositing a metal on the upper gate oxide layer to form an upper gate; The lower gate oxide film forming step is performed by a thermal oxidation process, The conducting channel forming step applies an electron beam lithography or photolithography method, The fine pattern is by an electron beam lithography method using an electron beam photosensitive film, And depositing a metal layer under the lower silicon substrate. delete delete delete delete delete The multi-quantum dot nano device, characterized in that produced by the manufacturing method of claim 1 or 2.

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