KR100906500B1 - Method of manufacturing gate of semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a gate of a semiconductor device. In particular, an oxide film and a nitride film are sequentially deposited, an etching process is performed to form a gate spacer, a gate electrode is formed, and only N + / P + ions are implanted into a silicon substrate. After forming the source / drain, the inclination toward the gate spacer is again given to the counter doping implant to form an LDD region to form a shallow junction, thereby securing a margin of the shallow junction. Accordingly, the present invention relates to a method of manufacturing a gate of a semiconductor device, which prevents channel punch through from occurring and thereby suppresses an increase in junction leakage current.

Slow Junction, Gate, Direct

Description

Method for manufacturing gate of semiconductor device             

1A to 1D are cross-sectional views sequentially illustrating a method of manufacturing a transistor gate according to the prior art.

2A to 2G are cross-sectional views sequentially illustrating a method of manufacturing a gate of a semiconductor device according to an embodiment of the present invention.

 -Explanation of symbols for the main parts of the drawing-

100: silicon substrate 110: device isolation film

120: well 130: buffer oxide film

140: nitride film 145: gate spacer

160: dielectric film 175: gate electrode

190: source / drain region 195: LDD region

200: nickel-salicide

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a gate of a semiconductor device, and more particularly, an oxide film and a nitride film are sequentially deposited, an etching process is performed to form a gate spacer, a gate electrode is formed, and a N + / P + is formed in a silicon substrate. After implanting only the ions to form the source / drain, the slope is further inclined toward the gate spacer, and a shallow junction is formed by performing a counter-doped implant, thereby securing a margin of the shallow junction. The present invention relates to a method of manufacturing a gate that can prevent a punch-through phenomenon from occurring and thereby suppress an increase in junction leakage current.

In general, a MOS field effect transistor is formed by forming a field oxide film on a silicon substrate, and then forming a gate oxide film and a polysilicon layer on the front surface thereof in an active region, and forming a gate electrode that acts as an electrode of the transistor by masking etching. Since the source / drain regions are formed by implanting ions into the silicon substrate on the side portion of the substrate, it can be used as a transistor.

Recently, as semiconductor devices are highly integrated, the line widths and spaces of various patterns constituting the device, that is, word lines and bit lines, are significantly reduced. In particular, design rules of transistor gates are gradually integrated to increase gate lengths. The gate length is getting shorter. By the way, in the case of the transistor gate manufactured according to the manufacturing method according to the prior art, after forming a field oxide film on a silicon substrate, a gate oxide film and a polysilicon layer formed on the entire surface of the transistor gate in the active region and serves as an electrode by masking etching After the electrode is formed, the source / drain regions are formed by implanting ions into the silicon substrate on the side of the gate electrode, and then forming gate spacers on the sidewalls of the gate electrodes. In turn, thermal budgets are applied, which causes a problem that the implanted ions are diffused to form the LDD region, thereby decreasing the cell junction margin.

In particular, in the transistor gate, the ion implanted to form the LDD region is diffused by the thermal birdjet, so that the gate length is reduced, thereby causing a channel punch through phenomenon. (junction leakage) increases the problem that can occur.

Hereinafter, with reference to the accompanying drawings, it will be described in more detail the problems appearing in the method of manufacturing a semiconductor device according to the prior art as described above.

1A to 1D are cross-sectional views sequentially illustrating a method of manufacturing a transistor gate according to the prior art.

According to the conventional method of manufacturing a transistor gate, first, as shown in FIG. 1A, a device isolation film 20 is formed by a shallow trench isolation (STI) process, and then a well for forming a transistor ( Wells 30 will be formed. Subsequently, the gate oxide layer 40 is grown by a wet oxidization process or an annealing process using wet and NO gas on the silicon substrate 10 on which the device isolation layer 20 and the well 30 are formed. An undoped poly 50, which is a gate electrode forming material, is deposited on the gate oxide layer 40. At this time, as the degree of integration of semiconductors increases recently, the circuit line width becomes smaller, and at the time of forming the gate oxide film 40 by the wet oxidization process, the thickness of the gate oxide film 40 becomes thin, that is, about 30 GPa or less. As a result, the thin film is formed thinner and thus, direct tunneling occurs, and also dopants of P + or N + doped into the silicon substrate 10 doped into the undoped-poly 50 to form the gate electrode. The characteristics of the device may be degraded due to the phenomenon caused by the phenomenon and the change in the threshold voltage due to the dopant distribution variation.

Then, as shown in FIG. 1B, the photoresist pattern (not shown) is formed to define the transistor gate electrode region by performing an exposure and development process using a photosensitive material on the resultant in which the undoped poly 50 is deposited. ) Is formed and then the etching process is performed using this as an etching mask to form the transistor gate electrode 60. Subsequently, the LDD region 70 is formed by implanting P- or N- ions into the silicon substrate 10 between the device isolation layer 20 and the transistor gate electrode 60 using the transistor gate electrode 60 as a mask. .

After the process of forming the LDD region 70 is performed, as shown in FIG. 1C, a spacer 80 is formed on the sidewall of the transistor gate electrode 60 by using an insulating layer to form the gate electrode 60. After protecting, the source / drain regions 90 are formed by implanting P + or N + ions into the LDD region 70 using the gate electrode 60 and the spacer 80 as an ion implantation mask to form a shallow junction ( 70, 90).                         

That is, in the above process, after the LDD region 70 is formed by implanting P- or N- ions, an insulating film is deposited to form the spacer 80 on the sidewall of the gate electrode 60, and isotropically etched. In this case, two thermal processes are performed, whereby two thermal birdjets are applied to the pre-formed LDD region 70, whereby P- or N- ions of the LDD region 70 are gated. (60) the gate length is shortened due to diffusion to the lower portion, and the concentration of the LDD region 70 is lowered due to the diffusion of P- or N- ions, thereby securing a shallow junction margin. There is a limit.

On the other hand, after forming the cell junction, as shown in Figure 1d, by performing a high temperature thermal process on the resultant to activate the ions injected into the cell junction, and then to the entire surface portion of the activated result Cobalt (not shown) is deposited. The cobalt (not shown) is for forming cobalt silicide in a later process. Subsequently, the high-temperature thermal process is performed on the cobalt-deposited product once again, so that the cobalt silicide 95 is disposed on the gate electrode 60 and the source / drain region 90 except the spacer 80 region formed of an insulating layer. To increase the junction resistance.

That is, according to the transistor gate manufacturing method according to the related art, as the degree of integration of semiconductors increases, the circuit line width decreases, and the thickness of the gate oxide film formed by the wet oxidization process becomes thinner and thinner to about 30 GPa or less. There was a problem in that tunneling (direct tunneling) occurs, and also, as shown in Figure 1c, by forming an LDD region, and then forming a spacer to which two thermal birdjets are applied, P- or N- ions are diffused under the gate electrode to shorten the gate length, making it difficult to secure a shallow junction margin, and channel punch through occurs, resulting in an increase in junction leakage. There was a problem.

In order to solve the above problems, as the integration degree of the semiconductor is recently increased and the circuit line width is reduced, the direct tunneling caused by the thinning of the gate oxide film is prevented, and the LDD due to the thermal birdjet applied when the spacer is formed By preventing the diffusion of ions in the region, it is possible not only to secure a margin of the shallow junction, but also to prevent the occurrence of channel punch through, thereby suppressing an increase in junction leakage current. It is an object to provide a gate manufacturing method.

In order to achieve the above object, the present invention includes forming a buffer oxide film and a nitride film on a semiconductor substrate, defining a gate electrode region by patterning the buffer oxide film and a nitride film, and performing a wet etching process on the nitride film and the buffer oxide film. Forming a gate spacer comprising a buffer oxide film and a nitride film on both sides of the gate electrode region, forming a dielectric film on the exposed semiconductor substrate of the gate electrode region, and forming a gate electrode by depositing polysilicon on the dielectric film Forming a source / drain region by implanting N + / P + ions with a gate spacer as a mask, and implanting the implant by giving an inclination toward the gate spacer to form an LDD region, and forming a gate electrode and a source / drain region Forming a nickel-salicide on top of the region; It provides gate process for manufacturing a semiconductor device, characterized in that eojin.

According to the method of manufacturing a gate of a semiconductor device according to the present invention, a dielectric film made of an oxide film and a nitride film is formed by a remote plasma nitrification step, so that the thickness of the gate oxide film thinned as the semiconductor device becomes highly integrated is compensated. Thus, direct tunneling can be prevented, and gate junctions are formed, and then, a shallow junction is formed, and when forming the gate spacers, the diffusion junctions are prevented from being diffused by the thermal birdjet applied. It is possible to secure a margin of, thereby preventing the channel punch through phenomenon from occurring and thereby suppressing an increase in junction leakage current.

In the method of manufacturing a gate of a semiconductor device according to the present invention, a bulk wet etching process is performed on the buffer oxide film and the nitride film on both sides of the gate electrode region, and in the step of forming the gate spacer, the buffer oxide film is formed using a solution of H ₃ PO ₄ . By etching this 100 μs, the implantation range of the N + / P + ion implant for forming a source / drain is later reduced by the buffer oxide film.

In addition, in the gate manufacturing method of the semiconductor device according to the present invention, the remote plasma nitrification step is performed at a temperature of 550 ~ 650 ℃ to form a dielectric film in which the nitride film and the oxide film are sequentially stacked. Accordingly, as the semiconductor device is highly integrated, the thickness of the gate oxide film, which is thinned, is compensated to prevent direct tunneling, and subsequently, P + or N + dopants doped with polysilicon to form the gate electrode are semiconductors. It is possible to prevent the penetration into the substrate.

In the method of manufacturing a gate of a semiconductor device according to the present invention, a counter-doping implant is performed by giving a tilt of 7 ° in the gate space direction to form an LDD region only in a lower portion of the gate spacer, thereby reducing the gate length. The channel punch through phenomenon can be prevented, and the junction leakage current can be reduced to realize a highly integrated device.

In the method of manufacturing a gate of a semiconductor device according to the present invention, the rapid heat treatment annealing process is carried out using N ₂ gas and O ₂ gas at a temperature of 900 ~ 1000 ℃, thereby activating the implanted N + / P + ions. Will be.

Hereinafter, an embodiment of a method for manufacturing a gate of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. However, the scope of the present invention is not limited thereto, but is presented as an example.

2A to 2G are cross-sectional views sequentially illustrating a method of manufacturing a gate of a semiconductor device according to the present invention.

According to the manufacturing method according to the present invention, in the same manner as in the prior art, by the STI (Shallow Trench Isolation) process, a well (120) for forming the isolation layer 110 and the transistor sequentially formed Next, as shown in FIG. 2A, an HLD oxide layer is deposited on the upper surface of the silicon substrate 100 on which the device isolation layer 110 and the well 120 are formed, as the buffer oxide layer 130, and then the nitride layer 140 is formed. Is deposited to a thickness of about 700Å by the LP-CVD method. In this case, the buffer oxide layer 130 is formed to a thickness of about 300 GPa so that the buffer oxide layer 130 of about 100 GPa remains after the over-etching process during the etching process for forming the gate spacer.

Subsequently, as illustrated in FIG. 2B, a photoresist film is coated on the nitride layer 140, and then an exposure and development process, that is, a photolithography process is performed to form a photoresist pattern 150 to define a gate electrode region. Subsequently, the gate electrode region 155 is defined by sequentially etching the insulating layer 140 and the buffer oxide layer 130 of the gate electrode region using the photoresist pattern 150 as an etch mask.

After the process of defining the gate electrode region 155 is performed, H ₃ PO is applied to the buffer oxide layer 130 and the nitride layer 140 remaining on both sides of the gate electrode region 155, as shown in FIG. 2C. _The bulk wet etch process is performed with the solution of ₄ to overetch the nitride layer 140, and the gate oxide layer 145 is formed by etching the buffer oxide layer 130 to remain at about 100 μs. Accordingly, the buffer oxide film 130 having a thickness of about 100 μs may reduce the implanted range when the N + / P + ion implant is formed to form a source / drain later.

After the process of forming the gate spacer 145, as shown in FIG. 2D, the remote plasma nitrate is formed on the exposed silicon substrate 100 of the gate electrode region 155 at a temperature of about 550 to 650 ° C. By applying a remote plasma nitration (RPN) process, the dielectric film 160 in which the nitride film 161 and the oxide film 162 are sequentially stacked is formed. In this case, the formed dielectric film 160 is formed to have a thickness of about 10 GPa, and as the semiconductor device is highly integrated by the dielectric film 160, the thickness of the gate oxide film, which is thinned, is compensated to prevent direct tunneling. In addition, it is possible to prevent the dopants of P + or N + doped into the polysilicon to form a subsequent gate electrode to penetrate the semiconductor substrate.

Thereafter, polysilicon 170 is deposited to form a gate electrode on the entire product on which the dielectric film 160 is formed, and is deposited to a thickness of about 1000 μs thick enough to cover the gate spacer 145.

As shown in FIG. 2E, the polysilicon 170 is masked to pattern the polysilicon 170 to form the gate electrode 175 inside the gate spacer 145, and then the gate spacer ( The source / drain region 190 is formed by implanting only N + / P + ions without implanting N− / P− ions using the mask 145 and the gate electrode 175 as a mask. In this case, when only the N + / P + ions are implanted, the implant implantation range can be reduced by the buffer oxide layer 130 of about 100 kV remaining by the bulk wet etching process for forming the gate spacer 145, and the gate Since the source / drain regions 190 formed by the N + / P + ions are formed after the spacer 145 is formed, it is possible to prevent ion diffusion due to the thermal birdjet applied when the gate spacer 145 is formed. will be.

After the process of forming the source / drain region 190 is performed, as shown in FIG. 2F, an inclination of about 7 ° toward the gate space 145 is provided to counter-dope the ions for forming the LDD region. By implanting (counter doping implant), the LDD region 195 is formed only on the lower portion of the gate spacer 145, thereby preventing the channel punch through phenomenon due to the reduction of the gate length, and also prevents junction leakage current It will be possible to implement a highly integrated device by reducing. In addition, a rapid heat treatment annealing process is performed on the resultant source / drain region 190 formed using N ₂ gas and O ₂ gas at a temperature of about 900 to 1000 ° C. to activate the implanted N + / P + ions. The shallow junctions 190 and 195 are formed.

Next, as shown in FIG. 2G, by forming a nickel-salicide 200 on the gate electrode 175 and the source / drain region 190, the contact resistance is reduced.

Therefore, as described above, when the gate manufacturing method of the semiconductor device according to the present invention is used, as the integration degree of the semiconductor becomes smaller and the circuit line width becomes smaller, the direct tunneling caused by the thinning of the gate oxide film can be prevented, In addition, by forming the spacer before forming the LDD region, it is possible to prevent the diffusion of ions in the LDD region by the thermal birdjet applied during the formation of the spacer, thereby securing a margin of the shallow junction. In addition, there is an effect to suppress the increase in the junction leakage current by preventing the channel punch through phenomenon occurs.

Claims (5)

Forming a buffer oxide film and a nitride film on the semiconductor substrate; Patterning the buffer oxide film and the nitride film to define a gate electrode region; Performing a wet etching process on the nitride film and the buffer oxide film to form gate spacers including the buffer oxide film and the nitride film on both sides of the gate electrode region; Forming a dielectric film on the exposed semiconductor substrate of the gate electrode region; Depositing polysilicon on the dielectric layer to form a gate electrode; Implanting N + / P + ions with the gate spacer as a mask to form a source / drain region; Implanting by giving an inclination toward the gate spacer to form an LDD region; And And forming nickel-salicide on the gate electrode and the source / drain regions. The method of claim 1, In the forming of the gate spacer, And etching the buffer oxide layer so as to remain at a thickness of about 100 GPa. The method of claim 1, wherein the forming of the dielectric film comprises: A method of manufacturing a gate of a semiconductor device, characterized in that to form a dielectric film in which a nitride film and an oxide film are sequentially stacked by performing a remote plasma nitriding process at a temperature of 550 to 650 ° C. The method of claim 1, wherein the forming of the LDD region comprises: And proceeding with an inclination of 7 ° such that an LDD region is formed only below the gate spacer. The method of claim 1, wherein in the forming of the source / drain regions, A method for manufacturing a gate of a semiconductor device, characterized in that the annealing process is performed using N2 gas and O2 gas at a temperature of 900 ~ 1000 ℃ after ion implantation.

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