KR100858082B1 - Etching Method of Nickel Oxide Layer - Google Patents

Abstract

An etching method of a nickel oxide layer and a method of manufacturing a storage node of a resistive memory device including the nickel oxide layer are disclosed. The etching method of the disclosed nickel oxide layer comprises the steps of: preparing a substrate having a nickel oxide layer formed thereon; Forming a mask pattern on a predetermined region of the nickel oxide layer; Removing the nickel oxide layer around the mask pattern by using a plasma generated from an etching gas in which a main gas and an additive gas are mixed at a predetermined mixing ratio; And removing the mask pattern.

Description

Method of etching nickel oxide layer

1 is a cross-sectional view showing a general configuration of a resistive memory device.

2 and 3 are cross-sectional views illustrating a method of forming a storage node of the memory device illustrated in FIG. 1.

4 to 6 are cross-sectional views illustrating a method of etching a nickel oxide layer according to an embodiment of the present invention.

7 is a cross-sectional view showing the configuration of the inductively coupled plasma etching apparatus used in the embodiment of the present invention.

8 is a scanning electron micrograph showing the result of the etching result of the etching method of the nickel oxide layer of the present invention.

9 is a scanning electron micrograph showing a nickel oxide layer etched by a conventional ion milling method.

10 to 12 are cross-sectional views illustrating a method of manufacturing a storage node of a resistive memory device according to another exemplary embodiment of the present invention.

The present invention relates to an etching method of nickel oxide used as a variable resistance layer of a resistive memory device.

The nickel oxide layer (NiO) may be used as a data storage layer of a resistive memory device which is a nonvolatile memory device as one of transition metal oxide (TMO).

Nonvolatile memory devices are typically flash memory in which stored data can be preserved even after the power is turned off. Unlike volatile memory, flash memory has nonvolatile characteristics, but has a low density and a slow operation speed compared to DRAM.

Currently, many researches are being conducted on nonvolatile memory devices including magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase-change random access memory (PRAM), and resistance random access memory (RRAM). .

1 is a cross-sectional view of a resistive memory device having a variable resistance layer.

Referring to FIG. 1, a gate oxide layer 13 and a gate electrode layer 14 are formed on a substrate 11 including a first impurity region 12a and a second impurity region 12b. One of the first impurity region 12a and the second impurity region 12b is a source and the other is a drain. The gate electrode layer 14, the first impurity region 12a and the second impurity region 12b constitute a transistor. An interlayer insulating layer 16 is formed on the substrate 11 to cover the transistor. A contact hole 20 through which the second impurity region 12b is exposed is formed in the interlayer insulating layer 16, and the contact hole 20 is filled with the conductive plug 22. The storage node S is formed on the interlayer insulating layer 16 to cover the exposed portion of the conductive plug 22.

The storage node S includes a lower electrode 30, a variable resistance layer 32, and an upper electrode 34 sequentially formed. 1 is a cross-sectional view illustrating a 1T (transistor)-1R (resistor) structure in which a resistive memory device using an amorphous variable resistance layer 32 as a data storage layer is connected to a transistor serving as a switch.

Here, instead of the transistor structure, it is connected to a diode structure including a p-type semiconductor layer and an n-type semiconductor layer to form a 1D (diode)-1R (resistor) structure, which is optional.

A single layer of NiO layer may be used as the variable resistance layer, and may also be formed in a multilayer structure including other protective layers.

The storage node S shown in FIG. 1 may be formed as shown in FIGS. 2 and 3.

As shown in FIG. 2, the lower electrode layer 41, the NiO layer 42, and the upper electrode layer 43 are sequentially formed on a predetermined region on the substrate 40, and then the storage node is formed on the upper electrode layer 43. A mask pattern M defining a region to be formed is formed. Thereafter, as illustrated in FIG. 3, the storage nodes S are completed by sequentially etching the stacked layers in the reverse order using the mask pattern M as an etch mask and removing the mask pattern M after etching.

On the other hand, when the ion milling method using the argon gas (Ar) used in the conventional semiconductor process to etch the NiO layer 42, the etched material on the side of the storage node (S) Redeposit may leave an ear byproduct (45 in FIG. 3), which may cause a problem of electrically shorting the material layers constituting the storage node (S).

In addition, when the NiO layer 42 is etched by the reactive ion etching method, it is difficult to produce a volatile etching product, and thus etching is performed at a high temperature of 300 ° C. or higher. This results in thermal damage to the fabricated device.

On the other hand, when the storage node S is formed by a lift-off method, productivity is reduced.

SUMMARY OF THE INVENTION An object of the present invention is to improve the above-mentioned problems of the prior art, and to minimize the thermal damage while preventing the redeposition of the etching by-products on the side of the etched result, the micro-sub having a good profile. It is to provide an etching method of the nickel oxide layer having a size of.

Another object of the present invention is to provide a method of manufacturing a storage node in a resistive memory device using a nickel oxide layer as a variable resistive layer.

In order to achieve the above object, the etching method of the nickel oxide layer according to an embodiment of the present invention:

Preparing a substrate having a nickel oxide layer formed thereon;

Forming a mask pattern on a predetermined region of the nickel oxide layer;

A third step of removing the nickel oxide layer around the mask pattern by using a plasma generated from an etching gas in which a main gas and an additive gas are mixed at a predetermined mixing ratio; And

And a fourth step of removing the mask pattern.

According to the invention, the third step is:

Loading the resultant product on which the mask pattern is formed into an inductively coupled plasma etching apparatus; And

Generating the plasma in an upper space in which the resultant is loaded by applying a predetermined source power and a bias voltage while uniformly supplying the etching gas to the etching apparatus.

According to the present invention, the mixing ratio of the main gas is preferably 40% to 70%.

In addition, the main gas is preferably at least one gas selected from the group consisting of Cl ₂ , BCl ₃ , BBr ₃ , HBr, CF ₄ , C ₂ F ₆ , C ₄ F ₈ , CHF ₃ , CO.

According to the present invention, source power of 500W to 800W is applied to the etching apparatus in the third step.

In addition, a bias voltage of about 100V to 150V is applied to the etching apparatus.

On the other hand, the third step may be carried out at room temperature of about 25 ℃.

A method of manufacturing a storage node of a resistive memory device including a nickel oxide layer according to another embodiment of the present invention is:

A first step of sequentially forming a lower electrode layer, a nickel oxide layer and an upper electrode layer on the substrate;

Forming a mask pattern on a predetermined area on the upper electrode layer;

A storage node of the resistive memory device is formed by sequentially removing the upper electrode layer, the nickel oxide layer, and the lower electrode layer around the mask pattern using a plasma generated from an etching gas in which a main gas and an additive gas are mixed at a predetermined mixing ratio. Performing a third step; And

And a fourth step of removing the mask pattern.

Hereinafter, an etching method of the nickel oxide layer according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings. In this process, the thicknesses of layers or regions illustrated in the drawings are exaggerated for clarity.

An etching method of the nickel oxide layer of the present invention will be described with reference to FIGS. 4 to 6.

Referring to FIG. 4, first, the insulating layer 62 and the nickel oxide layer 64 are sequentially formed on the substrate 60. Here, the substrate 60 uses a silicon substrate, but this is for illustrative purposes and is not necessarily limited thereto. In addition, the insulating layer 62 is silicon oxide, but is not necessarily limited thereto.

Referring to FIG. 5, a mask pattern 65 covering only a predetermined region of the nickel oxide layer 64 is formed using a photolithography process in which a predetermined exposure apparatus, for example, a KrF stepper, is used. At this time, the mask pattern 65 has a size of micro or less as a photosensitive film pattern. The mask pattern 65 having this size is transferred as it is to the material film formed below in the subsequent etching process. Therefore, the width and length of the finally formed nickel oxide layer 64 are also less than a micrometer.

Referring to FIG. 6, the nickel oxide layer 64 is dry-etched using the mask pattern 65 as an etching mask in the resultant shown in FIG. 5. The mask pattern 65 is then removed to obtain an etched nickel oxide layer 64 '.

At this time, the nickel oxide layer 64 is sequentially etched using a predetermined plasma etching process. In this process, it is important to independently control the mixing ratio of the mixed gas used as the etching gas and the bias power applied to the substrate.

FIG. 7 shows a schematic configuration of an inductively coupled plasma etching apparatus 100 used to etch a nickel oxide layer. Where reference numeral 102 denotes a stage on which the substrate is placed, 104 denotes a chuck supporting the stage 102, and 106 denotes a chuck 104 which is connected to a substrate loaded on the stage 102. A first RF matching unit for independently adjusting a predetermined bias power is shown. Reference numeral 108 denotes a chamber in which the plasma etching process is performed, 110 denotes a coil embedded in the upper wall of the chamber 108 so as to surround a space above the stage 102 inside the chamber 108, and 112 denotes a chamber 108. Optical emission spectroscopy to check the progress of etching inside. Light emitted by the light emission analyzer 112 through the light emitting window (not shown) provided in the chamber 108 is analyzed. Through the light emission analyzer 112, it is possible to know how far the etching proceeds in the chamber 112, what by-products are generated in the etching process, and the like. Reference numeral 114 denotes a second high frequency matching unit for independently adjusting the power applied to the coil 110. Although not shown in the figure, helium gas may flow inside the stage 102 to efficiently transfer the temperature of the chuck 104 to the substrate loaded on the stage 102.

When etching the nickel oxide layer in the inductively coupled plasma etching apparatus 100, the first high frequency matching unit 106 is 300 V or less, preferably 100 V to 150 V, to the substrate loaded on the stage 102. Apply a bias voltage of degree. The second high frequency matching unit 114 applies source power to the coil 110 at 1.5 kW or less, preferably 500W to 800W. Ions to be used for etching from the mixed etching gas uniformly introduced into the chamber 108 by the bias voltage applied by the first high frequency matching unit 106 and the source power applied by the second high frequency matching unit 114; Plasma containing radicals and electrons is generated in the space P above the stage 102.

The etching of the nickel oxide layer 64 is performed by loading the resultant (hereinafter, referred to as the resultant of FIG. 5) on the stage 102 with the mask pattern 65 formed on the nickel oxide layer 64 as shown in FIG. 5. It starts by For convenience, the parts indicated by reference numeral 116 in FIG. 7 are regarded as the result of FIG. 5 loaded on the stage 102. The resultant 116 of FIG. 5 loaded on the stage 102 is fixed until the etching is completed by the fixing members provided on the stage 102. As such, after the resultant 116 of FIG. 5 is fixed on the stage 102, the etching gas mixed in the space above the resultant 116 of FIG. 5 is formed through a nozzle (not shown) provided in the ceiling of the chamber 108. It is sprayed uniformly. As the mixed etching gas, chlorine gas (Cl ₂ ) as a main gas and an additive gas such as argon (Ar) gas may be used.

The etching characteristics of the nickel oxide layer may include a mixing ratio of the mixed etching gas, a main power applied to the inductively coupled plasma etching apparatus 100 to discharge the mixed etching gases, and a substrate loaded on the stage 102. It can be optimized by changing the bias power, substrate temperature, process pressure, gas flow rate, etc.

For example, it can be seen through experiments that the chlorine gas is most effectively etched against the nickel oxide layer when used in a mixture of 40% to 70%.

In addition to the chlorine gas, the main gas may be BCl ₃ , BBr ₃ , HBr, CF ₄ , C ₂ F ₆ , C ₄ F ₈ , CHF ₃ , CO gas.

Subsequently, the mixed etching gas is uniformly injected into the space above the resultant 116 of FIG. 5 by the nozzle provided in the chamber 108, and a predetermined source power, for example, is applied to the inductively coupled plasma etching apparatus 100. Apply 500W. As a result, radicals and ions, that is, plasma, used for etching are generated from the mixed etching gas. The nickel oxide layer 64 around the mask pattern 65 is etched in the resultant 116 of FIG. 5 by the generated plasma.

After the nickel oxide layer around the mask pattern 65 is etched, the mask pattern 65 is removed.

When the inductively coupled plasma etching apparatus 100 is used to etch the nickel oxide layer and an etching gas having the above-described mixing ratio is used, the plasma density, that is, radicals and ions, participating in the etching reaction increases. . Therefore, the plasma is further activated, so that even by-products generated in the etching process performed at a low temperature, for example, 100 ° C. or less, preferably 25 ° C., are volatile.

As described above, the etching process for forming the nickel oxide layer is not a high temperature process performed at several hundred degrees (° C.) but a low temperature process performed at room temperature of about 25 ° C., so that the nickel oxide layer is thermally etched during the etching process. Damage is prevented. In addition, since the etching by-products generated in the low temperature process as described above is volatile, the etching by-products are prevented from being re-deposited on the etched nickel oxide layer, so that the profile of the nickel oxide layer is much better than before.

FIG. 8 is a scanning electron micrograph showing a result of etching the nickel oxide layer according to the present invention, and FIG. 9 is a scanning electron micrograph showing a nickel oxide layer etched by a conventional ion milling method. 8 and 9 show a result of forming a silicon oxide layer and a nickel oxide layer stacked on a silicon substrate, and then etching the nickel oxide layer.

First, referring to FIG. 9, it can be seen that an etch byproduct is formed on the side of the nickel oxide in an ear shape during the ion milling process. These etching byproducts have made it difficult to use the nickel oxide layer in a memory device including a variable resistance layer.

Referring to FIG. 8, it can be seen that the pattern of the nickel oxide layer has a clean etching cross section, and thus this etching method enables the nickel oxide layer to be used as a variable resistance layer of the resistive memory device.

A method of manufacturing a storage node of the resistive memory device of the present invention will be described with reference to FIGS. 10 to 12.

Referring to FIG. 10, first, the lower electrode layer 82, the nickel oxide layer 84, and the upper electrode layer 86, which are constituents of the storage node of the resistive memory device, are sequentially formed on the substrate 80. Herein, the substrate 80 refers to material layers except for the storage node in FIG. 1.

Referring to FIG. 11, a mask pattern 87 covering only a predetermined region of the upper electrode layer 86 is formed by using a photolithography process using a predetermined exposure apparatus, for example, a KrF stepper. At this time, the mask pattern 87 has a size of micro or less as a photosensitive film pattern. The mask pattern 87 having this size is transferred as it is to the material film formed below in the subsequent etching process. Therefore, the width and length of the finally formed nickel oxide layer 84 are also less than a micrometer.

Referring to FIG. 12, the upper electrode layer 86, the nickel oxide layer 84, and the lower electrode layer 82 are sequentially etched using the mask pattern 87 as an etching mask in the resultant shown in FIG. 11. Subsequently, the mask pattern 87 is removed. In this way, the lower electrode layer pattern 82 ', the nickel oxide layer pattern 84', and the upper electrode layer pattern 86 'are sequentially stacked. Node S is completed.

In this case, the upper electrode layer 86, the nickel oxide layer 84, and the lower electrode layer 82 are sequentially etched using the inductively coupled plasma apparatus plasma etching apparatus 100 of FIG. 7. In this process, the etching conditions are different depending on the material layer to be etched.

The etching characteristics of the three material layers 86, 84, and 82 may include a mixing ratio of the mixed etching gases, a main power and a stage applied to the inductively coupled plasma etching apparatus 100 to discharge the mixed etching gases. The bias power, the substrate temperature, the process pressure, the gas flow rate, and the like applied to the substrate loaded on the substrate 102 may be changed and optimized.

As the mixed etching gas, chlorine gas (Cl 2) and an additional gas such as argon (Ar) gas may be used as the main gas. The chlorine gas was found to be the most effective etching for the nickel oxide layer when used in a mixture of 40% to 70% through experiments.

In addition to the chlorine gas, the main gas may be BCl ₃ , BBr ₃ , HBr, CF ₄ , C ₂ F ₆ , C ₄ F ₈ , CHF ₃ , CO gas.

As such, after the material layers 82, 84, and 86 around the mask pattern 87 are etched, the mask pattern 87 is removed.

As described above, the etching process for forming the nickel oxide layer is not a high temperature process performed at several hundred degrees (° C.) but a low temperature process performed at room temperature of about 25 ° C., so that the nickel oxide layer is thermally etched during the etching process. Damage is prevented. In addition, as described above, since the etch byproducts generated in the low temperature process are volatile, the etch byproducts are prevented from being redeposited on the etched nickel oxide layer, so that the profile of the nickel oxide layer is much better than before.

As described above, the etching method of the nickel oxide layer according to the present invention is performed in an inductively coupled plasma etching apparatus. As the etching process starts, Cl ₂ and Ar are mixed at an optimal ratio and uniformly supplied to the etching apparatus to generate an etching plasma. Accordingly, the density of plasma generated in the inductively coupled plasma etching apparatus, that is, the density of ions and radicals participating in the etching reaction may be increased to perform the etching process at a room temperature lower than 100 ° C., for example, about 25 ° C. In this way, the MTJ layer can be prevented from being thermally damaged in the etching process. And since the plasma is activated compared to the prior art, by-products generated in the etching process is volatile. Due to this property of the by-products, since the by-products are not redeposited on the storage node, the side of the storage node is not only clean but also has a vertical inclination, which makes the profile of the storage node much better than before.

Although the present invention has been described with reference to the embodiments with reference to the drawings, this is merely exemplary, it will be understood by those skilled in the art that various modifications and equivalent embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined only by the appended claims.

Claims (14)

Preparing a substrate having a nickel oxide layer formed thereon; Forming a mask pattern on a predetermined region of the nickel oxide layer; A third step of removing the nickel oxide layer around the mask pattern by using a plasma generated from an etching gas in which a main gas and an additive gas are mixed at a predetermined mixing ratio; And And etching the mask pattern to remove the mask pattern. The method of claim 1, wherein the third step, Loading the resultant product on which the mask pattern is formed into an inductively coupled plasma etching apparatus; And And applying the predetermined source power and bias voltage while uniformly supplying the etching gas to the etching apparatus to generate the plasma in an upper space in which the resultant is loaded. . The method of etching a nickel oxide layer according to claim 1 or 2, wherein the mixing ratio of the main gas is 40% to 70%. The method of claim 1, The main gas is an etched nickel oxide layer, characterized in that at least one gas selected from the group consisting of Cl ₂ , BCl ₃ , BBr ₃ , HBr, CF ₄ , C ₂ F ₆ , C ₄ F ₈ , CHF ₃ , CO Way. The method of claim 2, wherein a source power of 500W to 800W is applied to the etching apparatus. The etching method of claim 2, wherein a bias voltage of 100 V to 150 V is applied to the etching apparatus. The method according to claim 1 or 2, The third step is an etching method of the nickel oxide layer, characterized in that carried out at room temperature of 25 ℃. A first step of sequentially forming a lower electrode layer, a nickel oxide layer and an upper electrode layer on the substrate; Forming a mask pattern on a predetermined area on the upper electrode layer; A storage node of the resistive memory device is formed by sequentially removing the upper electrode layer, the nickel oxide layer, and the lower electrode layer around the mask pattern using a plasma generated from an etching gas in which a main gas and an additive gas are mixed at a predetermined mixing ratio. Performing a third step; And And a fourth step of removing the mask pattern. The method of claim 8, wherein the third step, Loading the resultant product on which the mask pattern is formed into an inductively coupled plasma etching apparatus; And And applying the predetermined source power and bias voltage while uniformly supplying the etching gas to the etching apparatus to generate the plasma in an upper space in which the resultant is loaded. The method according to claim 8 or 9, The mixing ratio of the main gas is 40% to 70% manufacturing method of the storage node. The method of claim 8, The main gas is manufactured of a storage node, characterized in that at least one gas selected from the group consisting of Cl ₂ , BCl ₃ , BBr ₃ , HBr, CF ₄ , C ₂ F ₆ , C ₄ F ₈ , CHF ₃ , CO Way. The method of claim 9, wherein a source power of 500 W to 800 W is applied to the etching apparatus. The method of claim 9, wherein a bias voltage of 100 V to 150 V is applied to the etching apparatus. The method according to claim 8 or 9, The third step is a manufacturing method of the storage node, characterized in that performed at room temperature of 25 ℃.

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