KR100843014B1 - Manufacturing Method of Semiconductor Device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, wherein the area of an active region is increased by isotropic etching the semiconductor substrate of the active region, and a tunnel insulating film is formed thereon to form a length of a channel. The present invention relates to a method of fabricating a semiconductor device capable of reducing short channel effects by increasing the short channel effect and reducing leakage current due to punchthrough between the source and the drain.

Description

Method of manufacturing a semiconductor device

1A to 1H are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.

2A through 2E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100 semiconductor substrate 102 buffer oxide film

104: nitride film 106: trench

108: insulating film 108a: device isolation film

110 tunnel insulating film 112 floating gate

114: dielectric film 116: control gate

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of reducing the leakage current caused by source / drain punchthrough by increasing the length of a channel.

As semiconductor devices become increasingly integrated, a self-aligned shallow trench isolation (SA-STI) method is used as an isolation forming process for separating active regions of a device. In the SA-STI method, a tunnel insulating film, a conductive film and a hard mask film are stacked on a semiconductor substrate, and then the hard mask film is etched using the photoresist pattern as an etch mask, and then the conductive film, the tunnel insulating film and the patterned hard mask film are used. The trench is formed by etching a predetermined region of the semiconductor substrate.

In this way, the critical dimension (CD) of the active region is determined when the trench is formed by the SA-STI method. As the device is highly integrated, the CD length of the active region is reduced as well as the CD of the isolation region. This shortens the leakage current due to source / drain punchthrough. In this case, the cell current (cell current) is not secured in the device of 40nm or less, it is impossible to manufacture the device.

The present invention provides a method of manufacturing a semiconductor device capable of reducing the leakage current caused by punch-through between the source and the drain by increasing the channel length to improve the short channel effect.

A method of manufacturing a semiconductor device according to a first embodiment of the present invention includes providing a semiconductor substrate having an etch mask formed in an active region and an isolation layer formed in an isolation region, and exposing the semiconductor substrate exposed by etching the isolation layer. Performing an etching process of the device isolation film and the semiconductor substrate so that the sidewalls are isotropically etched together, removing the etching mask, and forming an insulating film on the surface of the semiconductor substrate.

In the above, the device isolation layer is formed of an HDP (High Density Plasma) oxide film. Isotropic etching is performed by a wet etching method, and the etching selectivity of the semiconductor substrate and the device isolation layer is set to 0.2: 1 to 1: 1. The etching process is performed using a mixed solution of HF / NH ₄ F / Etylene Glycol or a mixed solution of HF / NH ₄ F / IPA.

The target etching thickness of the device isolation layer is 10 kPa to 1000 kPa. After forming the insulating film, the method further includes forming a floating storage charge storage film, a dielectric film, and a conductive gate control film.

In addition, in the method of manufacturing a semiconductor device according to the second embodiment of the present invention, there is provided a semiconductor substrate having an etching mask formed in an active region and an isolation layer formed in an isolation region, and an upper portion of the isolation layer being etched to provide a semiconductor. Performing a first etching process to expose the sidewalls of the substrate, performing a second etching process to etch the exposed sidewalls of the semiconductor substrate, removing the etching mask, and insulating films on the surface of the semiconductor substrate. Forming a step.

In the above, the device isolation layer is formed of an HDP oxide film. The first etching process is performed by a wet etching process using an etching recipe having an etching selectivity ratio of 20: 1 to 100: 1 between the semiconductor substrate and the device isolation layer, and is performed using BOE or HF.

In the second etching process, Cl ₂ , SF ₆ , HBr, O _2, or a combination thereof is used as a reaction gas, and a bias power larger than 0 W and smaller than 100 W is applied. The target etching thickness of the device isolation layer is 10 kPa to 1000 kPa.

After forming the insulating film, the method further includes forming a floating storage charge storage film, a dielectric film, and a conductive gate control film.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings. However, the embodiments of the present invention can be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below, and those skilled in the art It is preferred that the present invention be interpreted as being provided to more fully explain the present invention.

1A to 1H are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.

Referring to FIG. 1A, a buffer oxide film 102 and a nitride film 104 are sequentially formed on a semiconductor substrate 100 having an active region a and an isolation region b. The buffer oxide film 102 and the nitride film 104 serve as etching masks in a subsequent etching process. Here, the semiconductor substrate 100 is formed of silicon (Si). The buffer oxide film 102 may be formed of a silicon oxide film SiO ₂ . Thereafter, a photoresist (not shown) is formed on the nitride film 104 to expose the nitride film 104 of the device isolation region b by applying a photoresist (not shown) and performing an exposure and development process.

Referring to FIG. 1B, the device isolation region b of the nitride film 104 and the buffer oxide film 102 is etched by an etching process using a photoresist pattern, and the nitride film 104 and the buffer oxide film patterned with the photoresist pattern are subsequently etched. The semiconductor substrate 100 is etched by a predetermined region using an etching process using the 102. As a result, the trench 106 is formed in the device isolation region b of the semiconductor substrate 100. Thereafter, the photoresist pattern is removed.

Referring to FIG. 1C, an insulating material is deposited on the entire structure including the trench 106 so that the trench 106 is filled to form an insulating film 108. The insulating film 108 may be formed of an oxide film, and preferably, may be formed of an HDP oxide film by using a high density plasma (High Density Plasma) method.

Referring to FIG. 1D, the planarization process is performed until the surface of the nitride film 104 is exposed. As a result, the insulating film 108 remains only in the device isolation region b, and the entire surface of the semiconductor substrate 100 is planarized. In addition, an element isolation layer 108a formed of an insulating layer 108 is formed in the element isolation region b. In this case, the active region a and the device isolation region b are defined by the device isolation layer 108a.

Referring to FIG. 1E, an etching process may be performed such that sidewalls of the semiconductor region 100 of the active region a, which are exposed while the device isolation layer 108a of the device isolation region b is etched, are etched together.

Specifically, the etching process is performed by wet etching, using an etching recipe having a higher etching selectivity to the device isolation layer 108a than the semiconductor substrate 100. Preferably, the etching process is performed by setting the etching selectivity of the semiconductor substrate 100 and the device isolation layer 108a to 0.2: 1 to 1: 1. Here, the etching process is performed using a mixed solution of HF / NH ₄ F / Etylene Glycol or a mixed solution of HF / NH ₄ F / IPA. In this case, in order for the semiconductor substrate 100 to have a low selectivity with respect to the device isolation layer 108a, the concentration of NH ₄ F must be increased to increase the concentration of HF ^2- in the chemical solution.

In the first embodiment of the present invention, since the semiconductor substrate 100 is formed of silicon (Si) and the device isolation layer 108a is formed of an HDP oxide film, the first etching process is preferably an etching of silicon (Si) and the HDP oxide film. The selectivity may be set to 0.2: 1 to 1: 1.

In this case, the device isolation layer 108a of the device isolation region b having a high etching rate is etched first to expose sidewalls of the upper portion of the semiconductor substrate 100 of the active region a, and subsequently to expose the semiconductor substrate 100. Sidewalls are isotropically etched. At this time, the target etching thickness of the device isolation film 108a is set to 10 kPa to 1000 kPa.

As a result, the semiconductor substrate 100 on the active region a is isotropically etched by the etchant to have a three-dimensional structure, and thus the area of the active region a is increased compared to the conventional two-dimensional structure. . Accordingly, the short channel effect may be improved as the channel length is increased by increasing the length of the tunnel insulating layer (not shown) to be formed in a subsequent process. Therefore, the leakage current due to the source / drain punchthrough can be reduced, so that a device of 40 nm or less can be manufactured, and the yield can be improved and the reliability of the operation of the device can be improved.

Meanwhile, the buffer oxide layer 102 may also be etched by a predetermined thickness when etching the semiconductor substrate 100 of the active region a and the device isolation layer 108a of the device isolation region b.

Referring to FIG. 1F, the nitride film 104 and the buffer oxide film 102 are removed. In this case, the nitride film 104 may be removed using a phosphoric acid (H ₃ PO ₄ ) solution, and the buffer oxide film 102 may also be removed in the etching process of the nitride film 104.

Referring to FIG. 1G, the tunnel insulating layer 110 is formed along the surface of the semiconductor substrate 100 isotropically etched in the active region a. The tunnel insulating film 110 is formed of a silicon oxide film (SiO ₂ ), and in this case, is performed by an oxidation process. As such, when the tunnel insulating film 110 is formed along the surface of the semiconductor substrate 100 of the active region a having the three-dimensional structure by isotropic etching, the tunnel insulating film is compared with the semiconductor substrate of the active region having the conventional two-dimensional structure. The length of 110 is to be increased.

Referring to FIG. 1H, a floating storage charge storage layer (not shown) is formed on the tunnel insulating layer 110 and first patterned by an etching process using a mask (not shown), and the dielectric layer 114 is formed thereon. And a control film conductive film (not shown).

The charge storage film for the floating gate may be formed of a polysilicon film, a metal film, a laminated film of a polysilicon film and a metal film, or a nitride film. Charge storage film for floating gate A general non-volatile memory device is formed of a polysilicon film, and in the case of a Sonos (Silicon-Oxide-Nitride-Oxide-Silicon; SONOS) memory device, a nitride film is formed. The dielectric film 114 may be formed in a stacked structure of oxide-nitride-oxide (ONO). The conductive film for the control gate can be formed of a polysilicon film, a metal film, or a laminated film thereof, preferably a polysilicon film.

Thereafter, the control film conductive film, the dielectric film 114 and the floating storage charge storage film are sequentially patterned by a conventional etching process. As a result, the floating gate 112 and the control gate 116 are formed, and the gate including the tunnel insulating film 110, the floating gate 112, the dielectric film 114, and the control gate 116 is formed on the semiconductor substrate 100. Is formed.

2A through 2E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.

Referring to FIG. 2A, a first etching process for etching the device isolation layer 108a of the device isolation region b where the planarization process of FIG. 1D is completed is performed.

In detail, the first etching process is performed by a wet etching process, and an etching recipe having a higher etching selectivity with respect to the device isolation layer 108a in the device isolation region b is higher than the semiconductor substrate 100 in the active region a. It is carried out using. Preferably, the first etching process is performed by setting the etching selectivity of the device isolation layer 108a and the semiconductor substrate 100 to 20: 1 to 100: 1. At this time, the etchant may use BOE (Buffered Oxide Etchant) or HF. In addition, the target etching thickness of the device isolation film 108a is set to 10 kPa to 1000 kPa.

In the second embodiment of the present invention, since the semiconductor substrate 100 is formed of silicon (Si) and the device isolation layer 108a is formed of an HDP oxide film, the first etching process is preferably performed by etching the HDP oxide film and silicon (Si). It can be carried out using an etching recipe having a selectivity of 20: 1 to 100: 1.

As a result, only the device isolation layer 108a of the device isolation region b is selectively etched, and sidewalls of the upper portion of the semiconductor substrate 100 of the active region a are exposed.

Referring to FIG. 2B, a second etching process may be performed to etch exposed sidewalls of the semiconductor substrate 100 in the active region a. Specifically, the second etching process isotropically etched by using a dry etching method, and in order to prevent the recessed device isolation layer 108a from being etched, the second etching process may be performed more than the device isolation layer 108a of the device isolation region b. An etching recipe having a high etching selectivity with respect to the semiconductor substrate 100 in the active region a is used. Preferably, the second etching process is performed using Cl ₂ , SF ₆ , HBr, O _2, or a combination thereof as a reaction gas, with a bias power greater than 0 W and less than 100 W.

As a result, the exposed sidewalls of the semiconductor substrate 100 of the active region a are isotropically etched to have a three-dimensional structure, thereby increasing the area of the active region a as compared with a conventional two-dimensional structure. Thus, the short channel effect can be improved as the channel length is increased by increasing the length of the tunnel insulating film (not shown) to be formed in a subsequent process. Therefore, since the leakage current due to the source / drain punchthrough can be reduced, a device of 40 nm or less can be manufactured, and the yield can be improved and the reliability of the operation of the device can be improved.

Meanwhile, when the semiconductor substrate 100 is etched in the active region a, the buffer oxide layer 102 may also be etched by a predetermined thickness.

Referring to FIG. 2C, the nitride film 104 and the buffer oxide film 102 are removed. The nitride layer 104 may be removed using a phosphoric acid (H ₃ PO ₄ ) solution, and the buffer oxide layer 102 may also be removed during the etching process of the nitride layer 104.

Referring to FIG. 2D, a tunnel insulating layer 110 is formed along the surface of the isotropically etched semiconductor substrate 100 in the active region a. The tunnel insulating film 110 is formed of a silicon oxide film (SiO ₂ ), and in this case, is performed by an oxidation process. As such, when the tunnel insulating film 110 is formed along the surface of the semiconductor substrate 100 of the active region a having isotropic etching and is three-dimensional, the tunnel insulating film ( 110) is to be increased in length.

Referring to FIG. 2E, after forming a floating gate charge storage layer (not shown) on the tunnel insulating layer 110, first patterning is performed by an etching process using a mask (not shown), and the dielectric layer 114 is formed thereon. And a control film conductive film (not shown).

The charge storage film for the floating gate may be formed of a polysilicon film, a metal film, a laminated film of a polysilicon film and a metal film, or a nitride film. Charge storage film for floating gate A general non-volatile memory device is formed of a polysilicon film, and in the case of a Sonos (Silicon-Oxide-Nitride-Oxide-Silicon; SONOS) memory device, a nitride film is formed. The dielectric film 114 may be formed in a stacked structure of oxide-nitride-oxide (ONO). The conductive film for the control gate can be formed of a polysilicon film, a metal film, or a laminated film thereof, preferably a polysilicon film.

Subsequently, the control film conductive film, the dielectric film 114 and the floating gate charge storage film are sequentially patterned in a conventional process. As a result, the floating gate 112 and the control gate 116 are formed, and the gate including the tunnel insulating film 110, the floating gate 112, the dielectric film 114, and the control gate 116 is formed on the semiconductor substrate 100. Is formed.

The present invention is not limited to the above-described embodiments, but can be implemented in various forms, and the above embodiments make the disclosure of the present invention complete and complete the scope of the invention to those skilled in the art. It is provided to inform you. Therefore, the scope of the present invention should be understood by the claims of the present application.

The present invention is to isotropically etch the semiconductor substrate over the active region to increase the area of the active region to increase the length of the channel, thereby improving the short channel effect due to the high integration of the cells, thereby reducing the source / drain. Leakage current due to liver punchthrough can be reduced.

In addition, the present invention can reduce the leakage current caused by the punch-through between the source and drain, it is possible to manufacture a device of 40nm or less, and there is an effect that can improve the process yield and the reliability of device operation.

Claims (14)

Providing a semiconductor substrate having an etch mask formed in the active region and a device isolation layer formed in the device isolation region; Performing an etching process of the device isolation layer and the semiconductor substrate so that sidewalls of the semiconductor substrate exposed while the device isolation layer is etched are isotropically etched together; Removing the etch mask; And And forming an insulating film on the surface of the semiconductor substrate. The method of claim 1, The device isolation film is a method of manufacturing a semiconductor device formed of an HDP oxide film. The method of claim 1, The isotropic etching is a method of manufacturing a semiconductor device performed by a wet etching method. The method of claim 3, wherein The etching process is performed by setting the etching selectivity of the semiconductor substrate and the device isolation layer from 0.2: 1 to 1: 1. The method of claim 4, wherein The etching process is a semiconductor device manufacturing method using a mixture solution of HF / NH ₄ F / Etylene Glycol or a mixture solution of HF / NH ₄ F / IPA. The method of claim 1, The target etching thickness of the device isolation layer is a semiconductor device manufacturing method of 10 ~ 1000Å. The method of claim 1, And forming a floating gate charge storage film, a dielectric film, and a control gate conductive film after forming the insulating film. Providing a semiconductor substrate having an etch mask in the active region and a device isolation layer in the device isolation region; Performing a first etching process to etch an upper portion of the device isolation layer to expose sidewalls of the semiconductor substrate; Performing a second etching process to etch exposed sidewalls of the semiconductor substrate; Removing the etch mask; And And forming an insulating film on the surface of the semiconductor substrate. The method of claim 8, The device isolation layer is a semiconductor device manufacturing method of forming an HDP oxide film. The method of claim 8, The method of claim 1, wherein the first etching process is performed by a wet etching process using an etching recipe having an etching selectivity of 20: 1 to 100: 1 between the semiconductor substrate and the device isolation layer. The method of claim 10, The first etching process is a semiconductor device manufacturing method performed using BOE or HF. The method of claim 8, Cl ₂ , SF ₆ , HBr, O ₂ or a combination thereof in the second etching process using a reaction gas, and applying a bias power greater than 0W, less than 100W. The method of claim 8, The target etching thickness of the device isolation layer is a semiconductor device manufacturing method of 10 ~ 1000Å. The method of claim 8, And forming a floating gate charge storage film, a dielectric film, and a control gate conductive film after forming the insulating film.

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