KR100803725B1 - Common voltage generator - Google Patents

Abstract

The present invention relates to a common voltage generator having a common voltage level which can shorten production time and finely adjust.

The common voltage generator according to the present invention includes a first resistor connected to a first voltage source, a plurality of voltage adjusting resistors connected to a second voltage source, a voltage adjusting resistor of any one of the plurality of voltage adjusting resistors, and A switching element for connecting a first resistor, and a buffer for buffering the voltage divided by the first resistor and any one of the voltage adjusting resistors connected through the switching element to supply to the output terminal.

Description

Common Voltage Generator {COMMON VOLTAGE GENERATOR}             

1 is a block diagram showing a conventional liquid crystal display device.

FIG. 2 is a circuit diagram illustrating an equivalent circuit of the liquid crystal panel shown in FIG. 1.

3 is a circuit diagram illustrating a common voltage generator shown in FIG. 1.

4 is a block diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 5 is a diagram illustrating a control unit implemented with the ASIC shown in FIG. 4. FIG.

FIG. 6 is a circuit diagram illustrating a common voltage generator implemented with an EEPROM shown in FIG. 5.

7 is a flowchart illustrating a process of adjusting flicker using a program.

<Description of Symbols for Main Parts of Drawings>

1,31: Digital video card 2,32: control unit

3,33: data driver 4,34: liquid crystal panel

5,35: Gate driver 6,36: Common voltage generator

40: resistance unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving device for a liquid crystal display device, and more particularly, to a common voltage generating device having a common voltage level capable of shortening production time and making fine adjustments.

In general, a liquid crystal display (“LCD”) displays an image by adjusting light transmittance of liquid crystal cells according to a video signal. Among the liquid crystal display devices, an active matrix type in which switching elements are provided for each liquid crystal cell is suitable for displaying a moving image. In an active matrix type LCD, a thin film transistor (hereinafter, referred to as TFT) is mainly used as a switching element.

As shown in FIG. 1, a driving device of a liquid crystal display device includes a digital video card 1 for converting analog data into digital video data and a data driver for supplying video data to data lines DL of the liquid crystal panel 4. (3), a gate driver 5 for sequentially driving the gate lines GL of the liquid crystal panel 4, a control unit 2 for controlling the data driver 3 and the gate driver 5; And a common voltage generator 6 for supplying the common voltage Vcom to the data driver 3.

The digital video card 1 converts an analog input video signal into digital video data and detects a synchronization signal included in the video signal.

The common voltage generator 6 supplies a common voltage Vcom for driving the liquid crystal panel 4 to the data driver 3 using the supply voltage Vdd generated by the DC / DC converter unit (not shown). Will be supplied.

The control unit 2 supplies the digital video data of red (R), green (G) and blue (B) from the digital video card 1 to the data driver 3. In addition, the controller 2 generates the dot clock Dclk and the gate start pulse GSP using the horizontal / vertical synchronization signals H and V input from the digital video card 1 to generate the data driver 3 and the data driver 3. The timing of the gate driver 5 is controlled. The dot clock Dclk is supplied to the data driver 3, and the gate start pulse GSP is supplied to the gate driver 5.

The gate driver 5 includes a shift register (not shown) that sequentially generates scan pulses in response to the gate start pulse GSP input from the controller 2, and a level suitable for driving the voltage of the scan pulses to drive the liquid crystal cell. And a level shifter (not shown) for shifting to a low speed. In response to the scan pulse input from the gate driver 5, video data on the data line DL is supplied to the pixel electrode of the liquid crystal cell Clc by the TFT.

A dot clock Dclk is input to the data driver 3 together with video data of red (R), green (G), and blue (B) from the control unit 2. The data driver 3 latches the red (R), green (G), and blue (B) digital video data in synchronization with the dot clock Dclk, and then corrects the latched data according to the gamma voltage Vγ. Done. The data driver 3 converts the data corrected by the gamma voltage Vγ into analog data and supplies the data lines DL by one line.

In the liquid crystal panel 4, liquid crystal is injected between two glass substrates, and the gate lines GL and the data lines DL are formed to be perpendicular to each other on the lower glass substrate. TFTs for selectively supplying images input from the data lines DL to the liquid crystal cell Clc are formed at the intersections of the gate lines GL and the data lines DL, as shown in FIG. 2. . For this purpose, the gate terminal of the TFT is connected to the gate line GL, and the source terminal of the TFT is connected to the data line DL. The drain terminal of the TFT is connected to the pixel electrode of the liquid crystal cell Clc and the storage capacitor Cst. Parasitic capacitance Cgs (not shown) exists between the source terminal and the gate terminal of the TFT, and parasitic capacitance Cds (not shown) exists between the source terminal and the drain terminal of the TFT, and between the gate terminal and the drain terminal of the TFT. There is a parasitic dose Cgd.

Looking at the operation of the liquid crystal panel as follows.

When a high signal is applied to the gate line GL, all the TFTs connected to the gate line GL are turned on and at this time, the data signal is Cst along the data line DL connected to the source terminal of the TFT. And Clc to display an image.

When a low signal is applied to the gate line GL, all the TFTs connected to the gate line GL are turned off and at this time, an image is displayed by data stored in Cst.

However, as the voltage of the gate changes from Vgh to Vgl, the TFT is turned off, and at that moment, the voltage applied to the pixel electrode is reduced by ΔVp due to parasitic capacitance Cgd.

This voltage difference causes brightness difference and flickering of the screen occurs. To eliminate this flicker phenomenon, that is, to reduce the voltage difference applied to the liquid crystal layer during the (+) frame and the (-) frame, the common voltage Vcom is lowered than the center of the signal voltage. When the common voltage Vcom is lowered by ΔVp, the magnitude of the absolute voltage applied to the liquid crystal layer between the two frames is equal to remove flicker.

As shown in FIG. 3, the common voltage generator 6 generating the common voltage Vcom includes first to third resistors R1 to R3 formed between the supply voltage Vdd and the ground voltage GND. And a first capacitor C1 connected between the non-inverting terminal + of the operational amplifier OP and the ground voltage GND, and a fourth resistor R4 connected to the output terminal of the operational amplifier OP. And a second capacitor C2 connected between the fourth resistor R4 and the ground voltage GND.

The first resistor R1 is formed of a variable resistor whose resistance is adjusted by a user so as to adjust the common voltage Vcom applied to the common electrode according to the liquid crystal display. The second and third resistors R2 and R3 divide the supply voltage, and the first and second capacitors C1 and C2 serve to stabilize the power supply.

The voltage divided by the second and third resistors R2 and R3 and the first capacitor is input to the non-inverting (+) terminal of the operational amplifier OP, and the previous common voltage is fed back to the inverting (-) terminal. Is input. The operational amplifier OP is a buffer, which suppresses the loss of the divided voltage and supplies it to the output terminal.

However, the common voltage Vcom is designed to adjust flicker by varying the value of the first resistor R1 with a variable resistor, and it is difficult to finely adjust the first resistor R1 because the designer manually adjusts the first resistor R1. have. In addition, since the first resistor R1 is manually adjusted, it takes a long time to generate a desired common voltage.

Accordingly, an object of the present invention is to provide a common voltage generator having a common voltage level capable of fine adjustment and shortening production time.

In order to achieve the above object, the common voltage generator according to the present invention is any one of the first resistor connected to the first voltage source, a plurality of voltage adjusting resistors connected to the second voltage source, the plurality of voltage adjusting resistors A switching element for connecting one voltage regulating resistor and the first resistor, and a buffer for buffering the voltage divided by the first resistor connected through the switching element and one of the voltage regulating resistors and supplying the voltage to the output terminal. It is characterized by including.

The common voltage generator further includes a first capacitor connected between the switching element and the second voltage source, a second resistor connected between the buffer and the output terminal, and a second capacitor connected between the second resistor and the second voltage source. It is characterized by comprising as.                     

The plurality of voltage regulating resistors are connected in parallel and have different resistance values.

The common voltage generator is characterized in that it is implemented in EEPROM.

Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 4 to 7.

Referring to FIG. 4, the liquid crystal display according to the first exemplary embodiment of the present invention may include a digital video card 31 for converting analog data into digital video data, and data lines DL of the liquid crystal panel 34. The data driver 33 for supplying video data, the gate driver 35 for sequentially driving the gate lines GL of the liquid crystal panel 34, the data driver 33 and the gate driver 35 A control unit 32 for controlling and a common voltage generating unit 36 built in the control unit 32 are provided.

The digital video card 31 converts an analog input video signal into digital video data and detects a synchronization signal included in the video signal.

The control unit 32 supplies the red (R), green (G) and blue (B) digital video data from the digital video card 31 to the data driver 33. In addition, the controller 32 generates the dot clock Dclk and the gate start pulse Gsp using the horizontal / vertical synchronization signals H and V input from the digital video card 31 to generate the data driver 33 and the data driver 33. The timing of the gate driver 35 is controlled. The dot clock Dclk is supplied to the data driver 33, and the gate start pulse Gsp is supplied to the gate driver 35.

In addition, as shown in FIG. 5, the common voltage generator 36 is integrated in the controller 32. The common voltage generation unit 36 integrated in the control unit 32 uses the common voltage Vcom for driving the liquid crystal panel 34 using the supply voltage Vdd branched from the DC / DC converter unit (not shown). Create The common voltage Vcom generated by the common voltage generator 36 is supplied to the data driver 33.

The gate driver 35 may include a shift register (not shown) that sequentially generates scan pulses in response to a gate start pulse GSP input from the controller 32, and a voltage of the scan pulses at a level suitable for driving the liquid crystal cell. And a level shifter (not shown) for shifting. In response to the scan pulse input from the gate driver 35, video data on the data line DL is supplied to the pixel electrode of the liquid crystal cell Clc by the TFT.

The data driver 33 receives a dot clock Dclk together with video data of red (R), green (G), and blue (B) from the control unit 32. The data driver 33 latches the red (R), green (G) and blue (B) digital video data in synchronization with the dot clock Dclk, and then corrects the latched data in accordance with the gamma voltage Vγ. Done. The data driver 33 converts data corrected by the gamma voltage Vγ into analog data and supplies the data lines DL by one line.

Liquid crystal is injected between the two glass substrates, and the liquid crystal panel 34 is formed such that the gate lines GL and the data lines DL are orthogonal to each other on the lower glass substrate. A TFT for selectively supplying an image input from the data lines DL to the liquid crystal cell Clc is formed at the intersection of the gate lines GL and the data lines DL. For this purpose, the gate terminal of the TFT is connected to the gate line GL, and the source terminal of the TFT is connected to the data line DL. The drain terminal of the TFT is connected to the pixel electrode of the liquid crystal cell Clc and the storage capacitor Cst.

Referring to FIG. 5, the control unit 32 is formed of an application specific semiconductor, and is mainly implemented as an application specific integrated circuit (hereinafter, referred to as “ASIC”). The control unit 32 formed of an ASIC includes a common voltage generator 36 implemented as an electrically erasable and programmable ROM (hereinafter, referred to as “EEPROM”). When the supply voltage Vdd, the common voltage clock Vcom Clk, and the common voltage data Vcom DATA are input to the input terminal of the common voltage generator 36 implemented as an EEPROM, the data driver 33 and the gate driver are output to the output terminal. The common voltage Vcom input to 35 is generated. As shown in FIG. 6, the common voltage generator 36 includes a first resistor R1 to which a supply voltage Vdd is applied, a resistor unit 40 formed of a plurality of voltage adjusting resistors, and a first resistor. The switch SW connected between the resistor R1 and the resistor portion 40, the operational amplifier OP connected between the switch SW and the output terminal, and the non-inverting terminal (+) of the operational amplifier OP. And the first capacitor C1 connected between the base voltage source GND, the second resistor R2 connected to the output terminal of the operational amplifier OP, and between the second resistor R2 and the base voltage GND. And a second capacitor C2 connected to it.

The first and second capacitors C1 and C2 serve to stabilize the power supply. The resistor unit 40 includes a plurality of voltage adjusting resistors connected in parallel, and the plurality of voltage adjusting resistors have different resistance values.
The reference terminal of the switch SW is connected to the first resistor R1 connected to the voltage divider node, and the selection terminal is connected to any one of a plurality of voltage adjusting resistors. The switch SW selects at least one of a plurality of voltage adjusting resistors by a program and connects it to the first resistor R1. Accordingly, the supply voltage Vdd is divided by the resistance value of the at least one of the plurality of voltage regulating resistors and the first resistor R1 and input to the non-inverting terminal of the operational amplifier OP. The common voltage Vcom is fed back to the inverting terminal. The operational amplifier OP is a buffer, which suppresses the loss of the divided voltage and supplies it to the output terminal.

A process of selecting at least one of the plurality of voltage adjusting resistors formed in the resistor unit 40 of the common voltage generator 36 is illustrated in FIG. 7.

The set maker sets the temporary common voltage PVcom (S1). After inputting the temporary common voltage (PVcom) and test data into the program, the set maker visually checks the flicker displayed on the screen. One of the voltage adjusting resistors is selected by using a keyboard or a mouse according to whether or not flicker is generated to determine an optimum image state while adjusting the common voltage of the liquid crystal cell (S2). After checking the image state, it is determined whether the common voltage Vcom is redesigned (S3). If the flicker-free image is satisfied, the common voltage is finally determined (S4). When flicker remains in the image or when the gamma voltage or gate high voltage that affects the flicker is changed, it is fed back to reset the common voltage.

Here, the program for the common voltage level set by the set maker can be changed by changing the software in accordance with the setting range of the common voltage level and writing the common voltage level back to the EEPROM.
On the other hand, the common voltage generating device according to the present invention may be formed integrated in the control unit.

As described above, according to the present invention, by adjusting the common voltage level programmatically, fine adjustment of the voltage level is possible, thereby generating an accurate common voltage, and also reducing the time for setting the common voltage, thereby shortening the production time.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (4)

A first resistor connected to the first voltage source, A plurality of voltage regulating resistors connected to the second voltage source, A switching element connecting the voltage regulating resistor of the plurality of voltage regulating resistors to the first resistor; And a buffer for buffering the voltage divided by the first resistor and the voltage regulating resistor connected through the switching element and supplying the voltage to an output terminal. The method of claim 1, A first capacitor connected between the switching element and the second voltage source; A second resistor connected between the buffer and the output terminal; And a second capacitor connected between the second resistor and the second voltage source. The method of claim 1, The plurality of voltage adjusting resistors are connected in parallel and have a different resistance value, the common voltage generator of the liquid crystal display device. The method of claim 1, The common voltage generator is a common voltage generator, characterized in that implemented in the EEPROM (EEPROM).

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