KR100753795B1 - Semiconductor package and manufacturing method thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package and a method of manufacturing the same. The technical problem to be solved is a semiconductor package having a simple manufacturing process, a low manufacturing cost, a fast electrical signal processing speed, and excellent heat dissipation characteristics. To provide.

To this end, the gist of the solution according to the present invention is a semiconductor die in which a plurality of bond pads are formed, a plurality of leads positioned to face each bond pad of the semiconductor die, one end is bonded to the bond pad of the semiconductor die, and the other end is a lead. Disclosed is a semiconductor package including a plurality of wire terminals connected via solder paste.

In this case, a dimple having a predetermined depth may be further formed in the lead for easy connection with the wire terminal.

Description

Semiconductor package and manufacturing method the same

FIG. 1A is a cross-sectional view illustrating a semiconductor package according to an exemplary embodiment of the present invention, and FIG. 1B is an enlarged view illustrating region 1b of FIG. 1A.

2A is a cross-sectional view illustrating a semiconductor package in accordance with another embodiment of the present invention, and FIG. 2B is an enlarged view illustrating region 2b of FIG. 2A.

3 is a cross-sectional view illustrating a semiconductor package in accordance with another embodiment of the present invention.

4 is a cross-sectional view illustrating a semiconductor package in accordance with another embodiment of the present invention.

5 is a flowchart illustrating a method of manufacturing a semiconductor package according to the present invention.

6A to 6J are diagrams sequentially illustrating a method of manufacturing a chip package according to the present invention.

<Description of Symbols for Main Parts of Drawings>

100,200,300,400; Semiconductor package according to the present invention

110; Semiconductor die 111; Top

112; 113; side

114; Bond pads 120; Spacer

121; Adhesive 130; lead

131; Top 132; if

133; Side 134; Middle plane

135; Dimple 136; Groove

137; Solder paste 140; Die paddle

141; Top 142; if

143; Side 145; Dimple

147; Solder paste 150; Wire terminals

151; First terminal 152; Terminal 2

153; Third terminal 160; Encapsulation

161; Top 162; if

163; Flank 170; Solder ball

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package and a method for manufacturing the same, and more particularly, to a semiconductor package having a simple manufacturing process, a low manufacturing cost, a fast electrical signal processing speed, and excellent heat dissipation characteristics.

In general, the semiconductor package is designed to minimize the length of various wiring patterns formed on the connection member and the substrate interconnecting the semiconductor die and the substrate in order to improve the electrical signal processing speed of the semiconductor die. In response to this demand, flip chip packages are known as semiconductor packages having relatively short lengths of electrical connection members.

The flip chip package forms solder bumps, gold bumps, or kappa core solder bumps on the bond pads or the redistribution patterns of the semiconductor dies, and flips them to form a substrate. The electrical connection to the wiring pattern is carried out.

However, in the conventional flip chip package, the above-described solder bump, gold bump, or kappa core solder bump is additionally formed on the bond pad or the redistribution pattern of the semiconductor die, which increases the manufacturing process and increases the manufacturing cost. Accordingly, there is a problem of low production yield.

Moreover, such a conventional flip chip package has a pitch of the bond pads formed in the semiconductor die so small that it is difficult to actually form bumps directly on the bond pads. Therefore, a re-distributed layer (RDL) is usually performed. The RDL process, as is well known, forms a new redistribution pattern on the surface of the semiconductor die, thereby extending the pitch of the areas where the bumps are to be formed. It plays a role.

However, in order to form such RDL, many processes such as a coating process, a photo process, an etching process, a deposition process, and a plating process must be additionally performed, thereby making the manufacturing process of the semiconductor package more complicated and the manufacturing cost much more expensive. In addition, there is a problem that the production yield is also lowered. Of course, due to the newly formed redistribution pattern, the length of the signal line is increased accordingly, and thus there is a problem that it is difficult to apply to a semiconductor die requiring signal processing of several GHz to several tens of GHz.

Meanwhile, in addition to such a chip scale package, a semiconductor package is known in which a semiconductor die is electrically connected to a substrate such as a lead frame or a laminate circuit board using a conventional wire bonding process. However, the semiconductor package using such a wire bonding process has a problem that it is difficult to apply to a semiconductor die requiring signal processing of several GHz to several tens of GHz because the length of the wire is relatively long.

SUMMARY OF THE INVENTION The present invention has been made to overcome the above-mentioned problems, and an object of the present invention is to provide a semiconductor package having a simple manufacturing process, low manufacturing cost, high electrical signal processing speed, and excellent heat dissipation characteristics, and a method of manufacturing the same. It is.

In order to achieve the above object, a semiconductor package according to the present invention includes a semiconductor die having a plurality of bond pads formed thereon, a plurality of leads positioned to face each bond pad of the semiconductor die, and one end bonded to the bond pad of the semiconductor die. And the other end includes a plurality of wire terminals connected to the lead via solder paste.

Here, a dimple having a predetermined depth may be formed in the lead, and the wire terminal may be coupled to the dimple by solder paste.

In addition, a groove having a predetermined depth may be formed on an opposite surface of the lead to which the wire of the lead is connected, a plating layer having a predetermined thickness may be formed on the groove, and a solder ball may be welded to the plating layer.

In addition, a plurality of spacers may be bonded to the semiconductor die, and the die paddle may be bonded to the spacer in the same plane as the lead.

In addition, the spacer may be formed of any one material selected from epoxy, silicon, elastomer, or polyimide.

In addition, a dimple having a predetermined depth may be formed in the die paddle, and the wire terminal may be connected to the dimple through solder paste.

In addition, the wire terminal may be bent in the "S" shape.

The wire terminal may include a first terminal portion bonded to a bond pad of the semiconductor die, a second terminal portion bent by a predetermined angle from the first terminal portion and extended by a predetermined length, and a predetermined angle bent from the second terminal portion. The lead may include a third terminal portion connected through a solder paste.

The wire terminal may have a bending angle of 5 ° to 85 ° between the first terminal part and the second terminal part.

The semiconductor die, the lead, and the wire terminal may be encapsulated with an encapsulant, and an opposite surface of the lead to which the wire terminal is connected may be exposed to the outside of the encapsulant.

In addition, the semiconductor die, the lead, the wire terminal, the spacer and the die paddle are encapsulated with an encapsulant, but the opposite side of the lead to which the wire terminal is connected and the opposing side of the die paddle to which the spacer is bonded are exposed to the outside of the encapsulant. Can be.

In addition, an opposite surface of the semiconductor die on which the bond pad is formed may be exposed to the outside of the encapsulant.

In addition, in order to achieve the above object, the semiconductor package manufacturing method according to the present invention includes a spacer forming step of forming a spacer having a predetermined thickness in a wafer state on a semiconductor die having a plurality of bond pads, and a single semiconductor die from the wafer. A semiconductor die sawing step of sawing, a wire terminal forming step of forming a wire terminal of a predetermined length on a bond pad of the sawed semiconductor die, an adhesive forming step of adhering an adhesive to the spacer, and a pick-and-place of the semiconductor die. A pick-and-place step of seating on the lead on which the solder paste is formed, a wire terminal connecting step of reflowing the solder paste so that the wire terminal is electrically connected to the lead, and encapsulating the semiconductor die, the spacer, and the lead with an encapsulant. Of the lead to which the wire is connected Face comprises a sealing step to be exposed to the outside.

Here, a dimple having a predetermined depth may be formed in a portion where the wire terminal is to be positioned in the lead used in the pick and place step, and the solder paste may be printed on the dimple.

In addition, a recess having a predetermined depth may be formed on a lead opposite to a surface to which the wire terminal is connected to the lead used in the pick and place step, and a plating layer may be formed on the recess.

In addition, after the encapsulation step, a solder ball welding process for welding the solder ball to the plating layer of the lead may be further performed.

As described above, the semiconductor package and the method of manufacturing the same according to the present invention can omit all of the various complicated bump forming processes, the rewiring processes, and the like, so that the manufacturing process is simplified and the manufacturing cost is also low.

In addition, the semiconductor package and the method of manufacturing the same according to the present invention require signal processing of several GHz to several tens of GHz because electric signals flow not through the bumps and the rewiring patterns, but through the very short wire terminals. It is easy to apply to a semiconductor die.

In addition, in the present invention, heat generated from the semiconductor die is discharged to the outside through the lead and the die paddle mainly made of copper, thereby improving heat dissipation characteristics of the semiconductor package.

In addition, in the present invention, a dimple having a predetermined depth is formed in the lead in advance, and the wire terminal is connected to the dimple by solder paste, so that the electrical connection force between the wire terminal and the lead is excellent.

In addition, in the present invention, grooves are formed in the lead in advance, a plating layer having a predetermined thickness is formed thereon, and solder balls are welded to the plating layer, whereby the electrical connection force between the solder balls and the leads is excellent.

In addition, in the present invention, the predetermined surface of the semiconductor die is exposed to the outside of the encapsulation portion, whereby the heat dissipation characteristics of the semiconductor die may be further improved.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings such that those skilled in the art may easily implement the present invention.

FIG. 1A is a cross-sectional view illustrating a semiconductor package 100 according to an exemplary embodiment of the present invention, and FIG. 1B is an enlarged view illustrating an area 1b of FIG. 1A.

First, as shown in FIG. 1A, the semiconductor package 100 according to the present invention includes a semiconductor die 110 having a plurality of bond pads 114 and a semiconductor die 110 having the same surface as the surface on which the bond pads 114 are formed. A plurality of spacers 120 formed on the plurality of spacers 120, a plurality of leads 130 positioned to face each of the bond pads 114 of the semiconductor die 110, and a plurality of leads 130 positioned to face the spacers 120 and adhered thereto. One end is bonded to the die paddle 140 and the bond pad 114 of the semiconductor die 110, and the other end thereof is provided with a plurality of wire terminals 150 connected to the lead 130 through solder paste 137. And encapsulating the semiconductor die 110, the spacer 120, the lead 130, the die paddle 140, and the wire terminal 150 with an encapsulant, and the lead 130 and the die paddle 140 The predetermined surface includes an encapsulation portion 160 to be exposed to the outside.

The semiconductor die 110 has an approximately flat upper surface 111 and an approximately flat lower surface 112 as an opposite surface thereof, and a plurality of bond pads 114 are formed around the lower surface 112. Of course, a side surface 113 is formed between the upper surface 111 and the lower surface 112 substantially perpendicular to them. In addition, integrated circuits (not shown) are mainly formed on the bottom surface 112 of the semiconductor die 110. In addition, the bond pad 114 may be formed of ordinary aluminum or an equivalent thereof.

The spacer 120 is mainly attached to the lower surface 112 of the semiconductor die 110, and is formed to have a predetermined thickness toward the die paddle 140. That is, the spacer 120 is finally bonded to the die paddle 140 through the adhesive 121. In addition, the wire terminal 150 is not damaged by the weight of the semiconductor die 110 during the manufacturing process by the spacer 120. In other words, the spacer 120 prevents the wire terminal 150 from collapsing due to the weight of the semiconductor die 110 until the sealing process is completed. The spacer 120 is preferably an insulator to prevent electrical short, and is a highly elastic material to prevent separation between the semiconductor die 110 and the die paddle 140 during thermal expansion or thermal contraction of the package. It may be formed of epoxy, silicone, elastomer, polyimide or the like having low moisture absorption so as to be minimized. However, the present invention is not limited to the material of the spacer 120, it is obvious that various materials can be used in addition. In addition, although three spacers 120 are illustrated in the drawing, respectively, spaced apart from each other by a predetermined distance, they may be formed between the semiconductor die 110 and the substrate in an integral form. In addition, the thickness of the spacer 120 may be formed to be slightly smaller than the height of the wire terminal 150, so that the wire terminal 150 is surely in contact with the lead 130.

The plurality of leads 130 are positioned to face each bond pad 114 of the semiconductor die 110. The lead 130 may be formed of any one selected from ordinary copper, copper alloy, nickel / iron alloy, stainless steel, or an equivalent thereof, but is not limited thereto. The lead 130 is an intermediate surface formed by a partial etching technique between an approximately flat upper surface 131, an approximately flat lower surface 132 as an opposite surface of the upper surface 131, and the upper surface 131 and the lower surface 132. And a side surface 134 and a side surface 133 formed at right angles between the top surface 131 and the bottom surface 132. Here, a dimple 135 having a predetermined depth is formed on the upper surface 131 of the lead 130 by a partial etching technique or a stamping technique, as shown in FIG. 1B. Of course, a predetermined amount of solder paste 137 is applied to the dimple 135. In fact, the wire terminal 150 is difficult to be connected to the top surface 131 of the lead 130 by a conventional bonding technique and difficult to be aligned at a predetermined position, and thus, the top surface 131 of the lead 130 as described above. ), A dimple 135 having a predetermined depth is formed in advance, and a predetermined amount of solder paste 137 is applied to the surface thereof. In addition, the intermediate surface 134 formed on the lead 130 improves the mutual coupling force between the lead 130 and the encapsulation portion 160, so that the lead 130 is not easily separated from the encapsulation portion 160. It plays a role.

The die paddle 140 is positioned to face the spacer 120 bonded to the semiconductor die 110. The die paddle 140 may also be formed of any one selected from copper, a copper alloy, a nickel / iron alloy, or an equivalent thereof as the material of the lead 130, but the material is not limited thereto. The die paddle 140 also has an approximately flat upper surface 141 and an approximately flat lower surface 142 as an opposite surface of the upper surface 141, and a direction perpendicular to them between the upper surface 141 and the lower surface 142. The side surface 143 is formed. The side surface 143 is in a state spaced apart from the lead 130 by a predetermined distance. Of course, the spacer 120 is adhered to the upper surface 141 of the die paddle 140 by an adhesive 121. In addition, an intermediate surface may be formed on the die paddle 140 by a partial etching technique or a stamping technique to improve the bonding force with the encapsulation portion 160, but is not illustrated in the drawings.

As illustrated in FIG. 1B, one end of the plurality of wire terminals 150 is bonded to the bond pad 114 of the semiconductor die 110, and the other end is a dimple formed on the upper surface 131 of the lead 130. It is connected to the 135 through the solder paste 137. Here, the wire terminal 150 may be formed in an approximately "S" shape to electrically connect the bond pad 114 and the lead 130 to elasticity, but the present invention is not limited thereto. . For example, the wire terminal 150 may be bent at a predetermined angle from the first terminal 151 bonded to the bond pad 114 of the semiconductor die 110 in a direction substantially perpendicular to the first terminal 151 and may be predetermined. The second terminal 152 is extended in length, and the angle is bent from the second terminal 152 at the same time, or printed on the dimple 135 and the dimple 135 formed on the upper surface 131 of the lead 130 or The third terminal 153 is connected to the doped solder paste 137 in a substantially vertical direction, but the present invention is not necessarily limited thereto. Here, the bending angle (or shoulder angle) between the first terminal 151 and the second terminal 152 is a semiconductor die even in a high temperature environment generated during the package manufacturing process or the operation of the semiconductor die 110. It may be formed to approximately 5 ~ 85 ° so that the connection reliability between the 110 and the lead 130 is not degraded. That is, when the bending angle is 5 ° or less, there is a disadvantage in that the elastic force of the wire terminal 150 is reduced, and when the bending angle is 85 ° or more, between the first terminal 151 and the second terminal 152. The disadvantage is that the mechanical stress is too large. In addition, the wire terminal 150 has a fan-in type or an outside of the semiconductor die 110 in which the second terminal 152 and the third terminal 153 are formed to face inwardly of the semiconductor die 110. The fan-out type may be formed toward the direction, but the type is not limited thereto. That is, the fan-in type or the fan-out type may be appropriately selected and formed according to the number of bond pads 114 formed on the semiconductor die 110 and the design of the lead 130. In addition, the wire terminal 150 may be formed of an Au wire, an aluminum wire, an Al wire, a Cu wire, or an equivalent thereof, but the material of the wire terminals 150 and 130 may be used. It is not intended to limit. Meanwhile, the third terminal 153 of the wire terminal 150 may be electrically and mechanically connected to the dimple 135 formed on the upper surface 131 of the lead 130 through the solder paste 137. That is, in the wire terminal 150 according to the present invention, the first terminal 151 is ball-bonded to the bond pad 114 of the semiconductor die 110 by capillary among the wire bonding equipment. Although it may be ball bonding, the third terminal 153 is a structure that is difficult to stitch bonding or ball bonding to the upper surface 131 of the lead 130. Therefore, a predetermined size dimple 135 is formed in advance on the upper surface 131 of the lead 130 by a partial etching technique or a stamping technique during the manufacturing process, and a predetermined amount of solder paste 137 is applied to the dimple 135. In addition, in a state in which the third terminal 153 of the wire terminal 150 is aligned, a reflow process is performed, so that the third terminal 153 of the wire terminal 150 is connected to the lead ( It is electrically and mechanically connected to the dimple 135 and the solder paste 137 formed on the upper surface 131 of the 130. This manufacturing method will be described in more detail below. Of course, the solder paste 137 may be a lead-free solder in response to recent environmental pollution regulations, and various conductors may be used.

The encapsulation unit 160 basically encapsulates the semiconductor die 110, the spacer 120, the lead 130, the die paddle 140, and the wire terminal 150 with an encapsulant, thereby protecting them from the external environment. Of course, let the package form a certain form. Here, the lower surface 112 and the side surface 113 of the lid 130 and the lower surface 142 of the die paddle 140 are exposed to the outside of the encapsulation unit 160. Accordingly, heat generated from the semiconductor die 110 is quickly dissipated to the outside through the wire terminal 150 and the lead 130, and is also quickly dissipated to the outside through the spacer 120 and the die paddle 140. . In addition, the encapsulation portion 160 also has an upper surface 161, a lower surface 162, and a side surface 163. The lower surface 162 of the encapsulation portion 160 has a lower surface 132 of the lead 130. And coplanar with the bottom surface 142 of the die paddle 140. In addition, the side surface 163 of the encapsulation portion 160 is coplanar with the side surface 133 of the lid 130. The encapsulation unit 160 may be formed using any one selected from a conventional epoxy molding compound, an underfill, or an equivalent thereof, and the material is not limited thereto.

In this way, the semiconductor package 100 according to the present invention does not require various complicated bumps and rewiring as in the prior art. In addition, since the electrical signal between the semiconductor die 110 and the lead 130 is made through a very short wire terminal 150, it is applied to the semiconductor die 110 that requires signal processing of several GHz to several tens of GHz. easy. In addition, the heat generated from the semiconductor die 110 is discharged to the outside through the lead 130 and the die paddle 140 mainly made of copper, thereby improving heat dissipation characteristics.

In addition, as described above, a dimple 135 having a predetermined depth is formed in the lead 130, and the wire terminal 150 is connected to the dimple 135 through the solder paste 137. And the electrical connection between the lid 130 are easy and more secure.

2A is a cross-sectional view illustrating a semiconductor package 200 according to another exemplary embodiment of the present invention, and FIG. 2B is an enlarged view illustrating the region 2b of FIG. 2A.

As shown, the semiconductor package 200 according to another embodiment of the present invention is substantially the same as the semiconductor package 100 shown in FIGS. 1A and 1B. Therefore, mainly the differences will be described.

As illustrated in FIGS. 2A and 2B, in the semiconductor package 200 according to another exemplary embodiment, recesses 136 having a predetermined depth are further formed on the bottom surface 132 of the lead 130. The recess 136 may be formed through a conventional partial etching technique or a stamping technique. In addition, the groove 136 is further formed with a plating layer 138 having a predetermined thickness. The plating layer 138 is formed of a metal well connected to the solder ball 170 to be described later. More specifically, the plating layer 138 may be made of nickel / gold, but the present invention is not limited thereto.

The solder ball 170 is welded to the recess 136, the plating layer 138, and the periphery of the lead 130. This solder ball 170 may be a conventional tin / lead alloy or a recent Pb free solder. By the solder ball 170, the semiconductor package 200 according to the present invention can be mounted by immediately performing a reflow process to the external device without a separate solder printing process.

3 is a cross-sectional view illustrating a semiconductor package 300 according to another exemplary embodiment of the present invention.

As shown, the semiconductor package 300 according to another embodiment of the present invention is almost the same as the semiconductor package 100 shown in FIGS. 1A and 1B. Therefore, mainly the differences will be described.

As shown in FIG. 3, in the semiconductor package 300 according to another exemplary embodiment, the upper surface 111 of the semiconductor die 110 is coplanar with the upper surface 161 of the encapsulation portion 160. That is, the upper surface 111 of the semiconductor die 110 is exposed outside the encapsulation portion 160. Of course, the upper surface 111 of the semiconductor die 110 may be lower or higher than the upper surface 161 of the encapsulation portion 160.

In this manner, in the present invention, heat of the semiconductor die 110 is directly discharged to the outside through its exposed top surface 111 or to the outside through the spacer 120 and the die paddle 140. Of course, it is also discharged to the outside through the wire terminal 150, the lead 130 and the encapsulation portion 160. Therefore, the heat dissipation characteristics of the semiconductor package 300 according to the present invention are remarkably improved compared with the related art.

4 is a cross-sectional view illustrating a semiconductor package 400 according to another exemplary embodiment of the present invention.

As shown, the semiconductor package 400 according to another embodiment of the present invention is substantially the same as the semiconductor package 100 shown in FIGS. 1A and 1B. Therefore, mainly the differences will be described.

As shown in FIG. 4, the wire terminal 150 having one end bonded to the semiconductor die 110 may be connected to the die paddle 140 at the other end thereof. Of course, dimples 145 having a predetermined depth are formed in the die paddle 140, and the wire terminals 150 are coupled to the dimples 145 and fixed with the solder paste 147.

In this manner, in the present invention, all the ground signals of the semiconductor die 110 may be drawn out toward the die paddle 140. As such, the number of signal leads 130 can be increased, and thus a large amount of input / output signals can be easily handled. Of course, the die paddle 140 is also grounded by being connected to an external motherboard (or main board) through solder or the like.

5 is a flowchart illustrating a method of manufacturing the semiconductor package 100 according to the present invention.

As shown in the drawing, a method of manufacturing a semiconductor package 100 according to the present invention includes forming a spacer in which a spacer 120 having a predetermined thickness is formed in a wafer w on a semiconductor die 110 having a plurality of bond pads 114. Step S1, a semiconductor die sawing step S2 for sawing individual semiconductor dies 110 from the wafer, and a semiconductor die fixing step S3 for fixing the sawed semiconductor die 110 to a predetermined jig; A wire terminal forming step (S4) of forming a wire terminal 150 having a predetermined length on the bond pad 114 of the sawed semiconductor die 110, and an adhesive agent for adhering the adhesive 121 to the spacer 120. A pick-and-place step (S6) of picking and placing the semiconductor die 110 and picking and placing it on the lead 130 on which the solder paste 137 is formed, and the solder paste 137. To reflow the wire terminal (1). A wire terminal connecting step S7 for allowing 50 to be electrically connected to the lead 130, and the semiconductor die 110, the spacer 120, and the lead 130 are encapsulated with an encapsulant, but the wire terminal 150 is sealed. The opposite side of the lead 130 to which the is connected includes an encapsulation step (S8) to be exposed to the outside.

A method of manufacturing the semiconductor package 100 according to the present invention will be described in more detail with reference to FIGS. 6A to 6J.

First, referring to FIG. 6A, a forming step S1 of the spacer 120 is illustrated. As shown, a plurality of semiconductor dies 110 are formed on the wafer w with a substantially scribed line of scribe lines s formed therein, and each of the semiconductor dies 110 has a plurality of bond pads. 114 is formed, and a plurality of insulating spacers 120 having a predetermined thickness are formed in the inner region of the bond pad 114. The spacer 120 may be formed by, for example, any one method selected from a screen printing method, a jet dispensing method, or an equivalent method thereof, but the spacer 120 may be formed. ) Is not limited. In addition, the spacer 120 may be formed of any one insulating material selected from epoxy, silicon, polyimide, elastomer, or equivalent thereof having a predetermined elasticity, but the material is not limited thereto. Of course, such spacers 120 may not be formed on reject dies and edge dies.

Referring to FIG. 6B, a sawing step S2 of the semiconductor die 110 is shown. More precisely, a single semiconductor die 110 is shown, which is sawed and separated from the wafer w. This sawing of the semiconductor die 110 is performed by cutting along a scribe line s formed in the wafer w using a diamond blade (not shown) or the like as is well known. Of course, the sawing of the semiconductor die 110 is performed, for example, in a state in which the adhesive tape is adhered to the circular ring and the wafer is adhered to the surface thereof. In addition, the individual semiconductor die 110 as described above is picked up from the wafer by an adsorption tool.

Referring to FIG. 6C, a fixing step S3 of the semiconductor die 110 is illustrated. More precisely, the step of securing the semiconductor die 110 to a jig z of some form is shown. That is, the groove z1 having a predetermined depth is formed in the jig z having a substantially rectangular hexahedron shape, and a plurality of vacuum suction holes z2 are formed at the bottom surface of the groove z1 to provide a predetermined suction force. . Of course, this recess z1 is almost similar to the width and thickness of the semiconductor die 110. Therefore, after the semiconductor die 110 is seated in the recess z1 of the jig z, the semiconductor die 110 is firmly fixed to the jig z by the strong adsorption force of the vacuum adsorption hole z2. It becomes a state.

Referring to FIG. 6D, the forming step S4 of the wire terminal 150 is illustrated. Here, the jig is omitted in the drawing. Such a wire terminal 150 is performed by a wire bonding equipment used in a general packaging process. That is, as shown, the lower end of the wire w1 is ball bonded to the bond pad 114 of the semiconductor die 110 by the capillary c of the wire bonding equipment, and then the capillary c of the For example, the first terminal 151, the second terminal 152, and the third terminal 153 are continuously defined and formed by the predetermined trajectory. Of course, after the third terminal 153 is formed, the wire w1 is cut from the third terminal 153 by the spark of the discharge tip e. As described above, the wire terminal 150 is formed to be substantially "S" to have a predetermined elastic force. Of course, the wire terminal 150 has a fan-in type, a fan-out type, a type in which the fan-in type and the fan-out type are mixed, and the length of each second terminal 152. May be formed differently from each other according to a preset value. Here, since the vacuum suction force is continuously provided through the suction hole formed in the jig during the formation of the wire terminal 150, the semiconductor die 110 is not shaken during the formation of the wire terminal 150.

Referring to FIG. 6E, the forming step S5 of the adhesive 121 is shown. As shown, the formation of the adhesive 121 is formed by a predetermined adhesive tool (a). To this end, first, the vacuum suction force is removed through the suction hole formed in the groove of the jig. Subsequently, the adhesive tool a adsorbs the semiconductor die 110 coupled to the jig and rises a predetermined height upward. In this case, an adhesive 121 having a predetermined thickness is formed on the bottom surface of the adhesive tool a. The adhesive 121 is buried in a predetermined amount on the spacer 120 formed on the semiconductor die 110, thereby forming the spacer ( At the end of the 120, an amount of the adhesive 121 is naturally formed.

6F and 6G, the pick and place step S6 of the semiconductor die 110 is shown. For pick and place of such a semiconductor die 110, the adhesive tool a first rotates approximately 180 ° as shown in FIG. 6F. Thereafter, the pick-and-place tool p rises by a predetermined height in a state in which the pick-and-place tool p strongly vacuum-adsorbs the opposite surface on which the bond pad 114 is not formed. The semiconductor die 110 is then separated from the adhesive tool a. Of course, at this time, a certain amount of adhesive 121 remains in the spacer 120.

Subsequently, as shown in FIG. 6G, the pick and place tool p places the semiconductor die 110 on the die paddle 140 and the lead 130. Here, the dimple 135 having a predetermined depth may be previously formed in the lead 130, and the solder paste 137 may be previously applied to the dimple 135. Of course, the wire terminal 150 is coupled to the dimple 135 and the solder paste 137. In addition, the spacer 120 is bonded to the upper surface of the die paddle 140 through the adhesive (121). Here, the solder paste 147 may also be formed by any one method selected from a screen printing method, a pin dotting method, or an equivalent method thereof. In addition, although not shown in the drawing, dimples may be formed in the die paddle 140 and the solder paste 147 may be coated. In addition, grooves may be formed on the lower surface of the lead 130, and a plating layer having a predetermined thickness may be formed thereon.

Referring to FIG. 6H, a reflow step S7 is shown. As described above, after temporarily attaching the wire terminal 150 of the semiconductor die 110 to the dimple 135 of the lead 130 using the solder paste 137, the temperature of about 100 to 250 ° is maintained as it is. It is put in a hot furnace provided. Then, all the flux of the solder paste 137 is removed by volatilization and the solder is melted to fix the wire terminal 150 to the lead 130. Of course, after melting the solder paste 137, the semiconductor die 110, the lead 130, the die paddle 140, and the like are integrally taken out from the furnace and cooled to room temperature. By such cooling, the wire terminal 150 is firmly fixed to the lead 130 mechanically and electrically.

Referring to FIG. 6I, the forming step S8 of the encapsulation unit 160 is illustrated. The encapsulation 160 may be formed through a conventional mold or dispenser. In the case of using a mold, the reflow-completed package is placed between the upper mold and the lower mold, and an encapsulant such as an epoxy molding compound or an encapsulant of high temperature and high pressure is injected to form an encapsulant 160 of a predetermined shape. . In addition, in the case of using a dispenser, a dam or the like is formed in advance on the outer circumference of the lid 130, and the encapsulation unit 160 is formed by injecting a certain amount of liquid encapsulant or underfill into the dispenser and curing the encapsulation unit 160. To form. Here, the adhesive tape T may be adhered to the lower surface of the lead 130 and the die paddle 140 during the encapsulation process as described above. The adhesive tape serves to prevent the encapsulant flowing into the lower surface of the lead 130 and the die paddle 140 during the encapsulation process to form a large amount of mold flash.

Of course, the adhesive tape T is removed from the lead 130, the die paddle 140 and the encapsulation part 160 after completion of the formation process of the encapsulation part 160, as shown in FIG. 6J. 130 and a lower surface of the die paddle 140 are exposed to the outside of the encapsulation unit 160.

On the other hand, although not shown in the figure, after completion of the encapsulation process is usually followed by a singulation process. That is, in the semiconductor packaging process as described above, since a plurality of units are formed on one strip, a singulation process of separating the semiconductor package 100 into individual semiconductor packages 100 is performed after the sealing process is completed. In some cases, the solder ball 170 welding process for welding the solder ball 170 to the lower surface of the lead 130 may be further performed. Of course, the usual marking process or pack process is performed last.

As described above, the semiconductor package and the method of manufacturing the same according to the present invention can omit all of the various complicated bump forming processes and the rewiring processes as in the prior art, thereby simplifying the manufacturing process and reducing the manufacturing cost.

In addition, the semiconductor package and the method of manufacturing the same according to the present invention require signal processing of several GHz to several tens of GHz because electric signals flow not through the bumps and the rewiring patterns, but through the very short wire terminals. It is effective to apply to a semiconductor die.

In addition, the present invention has the effect that the heat generated from the semiconductor die to the outside through the lead and the die paddle mainly made of copper, thereby improving the heat dissipation characteristics of the semiconductor package.

Further, in the present invention, a dimple having a predetermined depth is formed in the lead in advance, and the wire terminal is connected to the dimple by solder paste, so that the electrical connection force between the wire terminal and the lead is excellent.

In addition, the present invention has the effect that the groove is formed in advance in the lead, a plating layer having a predetermined thickness is formed thereon, and the solder balls are welded to the plating layer, whereby the electrical connection force between the solder ball and the lead is excellent.

In addition, according to the present invention, the predetermined surface of the semiconductor die is exposed to the outside of the encapsulation portion, whereby the heat dissipation characteristics of the semiconductor die are further improved.

What has been described above is only one embodiment for carrying out the semiconductor package and the manufacturing method according to the present invention, the present invention is not limited to the above embodiment, as claimed in the following claims Without departing from the gist of the present invention, those skilled in the art to which the present invention pertains to the technical spirit of the present invention to the extent that various changes can be made.

Claims (16)

A semiconductor die having a plurality of bond pads formed thereon; A plurality of leads positioned to face each bond pad of the semiconductor die; One end is bonded to the bond pad of the semiconductor die, and the other end comprises a plurality of wire terminals connected to the lead through the solder paste. The semiconductor package of claim 1, wherein a dimple having a predetermined depth is formed in the lead, and the wire terminal is coupled to the dimple by solder paste. The semiconductor package of claim 1, wherein a groove having a predetermined depth is formed on an opposite surface of the lead to which the wire of the lead is connected, a plating layer having a predetermined thickness is formed on the groove, and a solder ball is welded to the plating layer. . The semiconductor package of claim 1, wherein a plurality of spacers are bonded to the semiconductor die, and the die paddle is bonded to the spacer in the same plane as the leads. The semiconductor package of claim 4, wherein the spacer is formed of any one material selected from epoxy, silicon, elastomer, and polyimide. The semiconductor package of claim 4, wherein a dimple having a predetermined depth is formed in the die paddle, and the wire terminal is connected to the dimple through a solder paste. The semiconductor package of claim 1, wherein the wire terminal is bent in an “S” shape. The method of claim 1, wherein the wire terminal is A first terminal portion bonded to the bond pad of the semiconductor die; A second terminal portion bent at a predetermined angle from the first terminal portion and extended by a predetermined length; And a third terminal portion bent at a predetermined angle from the second terminal portion and connected to the lead through solder paste. The semiconductor package of claim 8, wherein the wire terminal has a bending angle of 5 ° to 85 ° between the first terminal part and the second terminal part. The semiconductor package of claim 1, wherein the semiconductor die, the lead, and the wire terminal are encapsulated with an encapsulant, and an opposite surface of the lead to which the wire terminal is connected is exposed to the outside of the encapsulant. The semiconductor die of claim 1, wherein the semiconductor die, the lead, the wire terminal, the spacer, and the die paddle are encapsulated with an encapsulant, wherein an opposing face of the lead to which the wire terminal is connected and an opposing face of the die paddle to which the spacer is bonded are encapsulant. A semiconductor package, characterized in that exposed to the outside. The semiconductor package of claim 10, wherein the opposite surface of the semiconductor die on which the bond pad is formed is exposed outside the encapsulant. A spacer forming step of forming a spacer having a predetermined thickness in a wafer state on a semiconductor die having a plurality of bond pads; A semiconductor die sawing step of sawing individual semiconductor dies from the wafer; Forming a wire terminal having a predetermined length on a bond pad of the sawed semiconductor die; An adhesive forming step of adhering an adhesive to the spacer; A pick-and-place step of pick-and-place the semiconductor die and seating it on a lead on which solder paste is formed; A wire terminal connecting step of reflowing the solder paste so that the wire terminal is electrically connected to a lead; And encapsulating the semiconductor die, the spacer, and the lid with an encapsulant, wherein the opposite side of the lead to which the wire is connected is exposed to the outside. The method of claim 13, wherein a dimple having a predetermined depth is formed in a portion of the lead used in the pick and place step, and a solder paste is printed on the dimple. . The method of claim 13, wherein a recess having a predetermined depth is formed on a lead opposite to a surface to which the wire terminal is connected, and a plating layer is formed on the lead. The method of claim 15, wherein after the encapsulating step, a solder ball welding process of depositing solder balls on the plating layer of the lead is further performed.

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