KR100545193B1 - MOS transistor - Google Patents

Abstract

The present invention relates to a MOS transistor, and an object thereof is to provide a MOS transistor having a new structure that can compensate for the disadvantages of the MOS transistor structure having a conventional three gate electrode. To this end, the present invention is characterized by forming an inversion layer having a high concentration under the sidewall gate by injecting electrons, negative charges, holes or positive charges into the potential well formed in the sidewall gate. That is, the MOS transistor according to the present invention includes a gate insulating film having a predetermined width formed on a semiconductor substrate; A main gate formed on the center portion of the gate insulating film and having a smaller width than the gate insulating film; Sidewall insulating films formed on both sidewalls of the main gate; Sidewall gates formed on the edge portions of the gate insulating film and the sidewall insulating films that are not applied by the main gate and are positioned on both sides of the main gate and have holes or electrons injected therein; And source and drain regions formed in the semiconductor substrate on both sides of the sidewall gate.

Sidewall Gate, Inverting Layer, Hole, Charge

Description

MOS transistor

1 is a cross-sectional view showing a MOS transistor structure having three conventional gate electrodes;

2 is a cross-sectional view illustrating a MOS transistor structure having three gate electrodes according to the present invention.

The present invention relates to a MOS transistor structure, and more particularly to a structure of a MOS transistor having three gate electrodes.

A conventional MOS transistor structure with three gate electrodes has been described in H.Noda, F.Murai, and S.Kimura's paper, published in 1993, "Threshold voltage controlled 0.1 using an inversion layer as an extremely shallow source / drain. Μm MOSFET "(IEDM Tech. Dig., 1993, pp. 123-126).

1 illustrates a conventional MOS transistor structure having three gate electrodes. In the case of NMOS, a gate oxide film 5 and a polysilicon main gate 8 heavily doped with N-type impurities are formed on a P-type silicon substrate 1. There is a polysilicon sidewall gate 7 doped with N-type impurities at both sides of the main gate.

An oxide film 6 exists between the sidewall gate 7 and the main gate 8 for insulation, and a gate oxide film 5 exists between each sidewall gate 7 and the P-type silicon substrate 1. .

The source 2 and the drain 3 are formed in the semiconductor substrate 1 outside the sidewall gate 7.

In the case of PMOS, only the conductivity type of impurities is different, and the rest are all the same.

When a constant voltage is applied to the sidewall gate of this structure, an inversion layer is formed under the sidewall gate, which plays the same role as the source / drain extention area of the MOS transistor. Channels are formed so that current flows between the drain and the source.

By using the sidewall gate to form a virtual source / drain extention area, the source / drain extension region junction depth of about 5 to 10 nm can be formed, so that the drain field of the MOS transistor is a channel. It is possible to effectively improve short channel effects such as a threshold voltage drop phenomenon and a drain induced barrier lowering (DIBL) generated by penetrating to the side.

However, when the source / drain extension region is formed by the conventional ion implantation process, since the implanted impurities are diffused into the channel region by the subsequent thermal process, when the gate length is 0.06 μm or less, the source / drain adheres to each other and the MOS transistor is actually used. Also, even when the gate length is more than 0.06 μm, the source / drain junction depth cannot be formed to be less than 10 nm, which causes a short channel effect.

Therefore, a virtual source / drain extension region structure using sidewall gates has been attracting attention as an alternative to forming source / drain extension regions of nano-transistors of 0.1 μm or less.

However, in the conventional MOS transistor structure having three gate electrodes, in order to apply a constant voltage to the sidewall gate, a contact must be formed on the sidewall gate. This is a difficult problem, and the ion implanted for the purpose of adjusting the sidewall gate threshold voltage is difficult. They may diffuse through subsequent thermal processes and affect the threshold voltage of the main gate region.

In addition, an additional parasitic capacitance is generated between the sidewall gate and the main gate, between the sidewall gate and the body, and between the sidewall gate and the source / drain, which slows down the transfer rate of the sidewall gate bias voltage applied by the parasitic capacitance. This results in relatively poor transistor performance.

In addition, since a constant voltage must be continuously applied to the sidewall gate, additional leakage current may occur to increase power consumption, and deterioration of the insulating layer between the sidewall gate and the main gate may occur.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide a MOS transistor having a new structure that can compensate for the disadvantages of the MOS transistor structure having three gate electrodes.

In order to achieve the above object, the present invention is characterized in that the sidewall gate is formed of a material having a larger energy band gap than the main gate.

That is, the MOS transistor according to the present invention includes a gate insulating film having a predetermined width formed on a semiconductor substrate; A main gate formed on the center portion of the gate insulating film and having a smaller width than the gate insulating film; Sidewall insulating films formed on both sidewalls of the main gate; Sidewall gates formed on the edge portions of the gate insulating film and the sidewall insulating films that are not applied by the main gate and are positioned on both sides of the main gate and have holes or electrons injected therein; And source and drain regions formed in the semiconductor substrate on both sides of the sidewall gate.

Hereinafter, the present invention will be described in detail.

2 is a cross-sectional view illustrating a structure of a MOS transistor according to the present invention. As shown in FIG. 2, a gate insulating film 25 having a predetermined width is formed on a semiconductor substrate 21, and a gate insulating film 25 is formed on a central portion of the gate insulating film 25. The main gate 28 having a width smaller than that of the gate insulating film 25 is formed.

Sidewall insulating films 26 are formed on both sidewalls of the main gate 28, and sidewall gates are formed on the edges of the remaining gate insulating film 25 and the sidewall insulating films 26, which are not applied by the main gate 28. 27) is formed. At this time, holes or electrons are injected into the sidewall gates 27 located on both sides of the main gate 28.

A positive charge may be injected instead of a hole, and a negative charge may be injected instead of an electron.

Source 22 and drain 23 regions are formed in the semiconductor substrate 21 on both sides of the sidewall gate 27.

As described above, the MOS transistor structure according to the present invention is doped with a high concentration n-type (p-type in the case of PMOS) impurities instead of using a conventionally heavily doped polysilicon as a sidewall gate as compared with the conventional device structure. It is characterized by injecting holes or electrons into the polysilicon.

In general, the threshold voltage of the long channel MOS transistor may be represented by Equation 1 below.

Description of each symbol in Equation 1 is as follows.

φ _ms : Work function difference [V], φ _f : Fermi potential [V], Q _d : Depletion region charge amount [C / cm ³ ]

C _ox : gate oxide capacitance, q: charge amount of electron [C],

D _p : p-type dopant threshold voltage adjustment dose amount [cm ^-2 ],

D _n : n type dopant threshold voltage adjustment dose amount [cm ^-2 ]

Q _t : Charge trapped in sidewall gate potential well [C / cm ³ ]

The work function difference is around -1.0 V and the Fermi potential is almost fixed at 0.4-0.45 V when using a general high concentration N + polysilicon gate. Therefore, to adjust the threshold voltage, the amount of depletion region charge is controlled by adjusting the concentration of the silicon substrate. Or a method of injecting N-type impurities or P-type impurities into the silicon substrate surface.

For example, if a high concentration of N + polysilicon gate is used, and the silicon substrate has a concentration of 1.0 × 10 ¹⁷ [ions / cm ³ ] and the gate oxide has a thickness of 50 GPa, N-type or P-type impurities are not implanted in the silicon substrate surface. The threshold voltage of a long channel native NMOS transistor is about 0.1V, and in the short channel case, it will have a lower threshold voltage.

Therefore, a voltage much higher than the threshold voltage, such as 2 to 3 V, should be applied to the sidewall gate so that a sufficient amount of inversion layer may be formed under the sidewall gate to form a desired source / drain extension region.

If the threshold voltage is to be increased under the above conditions, the P-type impurity may be ion-implanted onto the silicon substrate surface. If the threshold voltage is to be reduced, the N-type impurity may be ion implanted to the silicon substrate surface.

However, injecting impurities to adjust the threshold voltage is not preferable because the implanted impurities can be diffused by a subsequent thermal process to change the threshold voltage of the main gate. Since it is difficult to lower the threshold voltage from -1 V to -2 V or less, it can be seen that in the conventional structure, a desired source / drain extension region can be obtained only by applying a voltage to the sidewall gate.

However, when holes (or positive charges) are injected into the high concentration N-type polysilicon forming the sidewall gates as in the present invention, the injected holes (or positive charges) are added to the sidewall gates (polysilicon), the gate insulating film (oxide film), and the sidewalls. The threshold voltage of the sidewall gate can be lowered below the desired voltage by being trapped in the potential well formed between the insulating film (oxide film) and lowering the flat band voltage.

For example, a high concentration of N + polysilicon sidewall gate is used, the silicon substrate has a concentration of 1.0 × 10 ¹⁷ [ions / cm ³ ], the thickness of the gate oxide is 90 GPa, and holes (or positive charges) in the high concentration of N + polysilicon sidewall gate. When 2.0 x 10 ¹⁶ [ions / cm ³ ] is injected, the threshold voltage of a long channel native NMOS transistor that does not inject N-type or P-type impurities into the silicon substrate surface is approximately -5V.

Thus, by injecting holes (or positive charges) into the potential well of the N + polysilicon sidewall gate, a threshold voltage much lower than 0 V can be obtained in the native state, so that an inversion layer is always under the sidewall gate even if the sidewall gate is not biased. This can be formed to make a source / drain extension region.

Here, if the amount of holes (or positive charges) injected into the N + polysilicon sidewall gate potential well is changed, the threshold voltage can be changed as much as desired. Therefore, in order to make a high performance transistor, the injection is a hole (or positive charges). The threshold voltage of the sidewall gate is made very low by increasing the amount of, and thus the amount of inversion layer formed is increased to reduce the source / drain extension region parasitic resistance.

On the contrary, in the case of making a low leakage transistor, the amount of holes (or positive charges) to be injected is reduced to raise the threshold voltage of the sidewall gate somewhat, thus reducing the amount of inversion layer to be formed. It is only necessary to increase the drain extension region parasitic resistance.

In addition, by reducing the thickness of the sidewall gate oxide layer or by using a material having a high dielectric constant, the increase in the threshold voltage due to the depletion region charge amount can be reduced.

In order to further reduce the threshold voltage, an additional count-dopoing may be performed under the sidewall gate. Here, count doping means that N-type impurities are implanted into the channel region surface in the case of NMOS and P-type impurities are implanted into the channel region surface in the case of PMOS, thereby lowering the NMOS and PMOS threshold voltages.

In the case of performing the count doping, since the impurities implanted by the count doping are diffused into the main gate region through the subsequent thermal process, the threshold voltage of the main gate region can be changed, so it is not applicable to the nano transistor. This threshold voltage change can be sufficiently achieved by controlling the amount of holes injected into the sidewall gate potential wells. Thus, virtually no count doping is needed.

In addition, since the voltage applied to the main gate is induced a certain amount of voltage to the sidewall gate by coupling the sidewall gate insulating oxide film 26 and the sidewall gate oxide film 25, the thickness of the sidewall gate insulating oxide film is increased. 0.5 of the voltage applied to the main gate when the coupling ratio is made 0.5 or more by using a dielectric material that is relatively thinner than the thickness of the gate oxide film or when the dielectric constant of the sidewall gate insulating oxide is larger than that of the sidewall gate oxide film. More than twice the voltage is induced in the sidewall gate.

Therefore, the induced voltage in the sidewall gate further increases the inversion layer under the sidewall gate, so that the parasitic resistance value of the source / drain extension region formed is further reduced, so that a large amount of current can flow in the on state. In the (Off) state, since no voltage is induced at the sidewall gate, the parasitic resistance of the source / drain extension region formed by decreasing the inversion layer is relatively increased, so that less current can flow in the off state.

Therefore, the sidewall gate threshold voltage can be lowered to a desired level by injecting holes (or positive charges) into a polysilicon potential well doped with a high concentration N-type impurity used as a conventional sidewall gate for NMOS as in the present invention. Even without biasing the wall gate, an inversion layer can be formed under the sidewall gate to form source / drain extension regions. In addition, the coupling between the sidewall gate insulating oxide film 26 and the sidewall gate oxide film 25 is adjusted so that the voltage applied to the main gate is induced to the sidewall gate by a predetermined amount. To increase the parasitic resistance of the source / drain extension region and to decrease the amount of the inversion layer in the OFF state to increase the parasitic resistance of the source / drain extension region. Can be changed dynamically.

As described above, in the present invention, by injecting holes (or positive charges) into polysilicon doped with a high concentration of N-type impurities used as a sidewall gate for NNOS, and in the case of PMOS, it is used as a sidewall gate for PMOS. By injecting electrons (or negative charges) into polysilicon doped with high concentration P-type impurities, an inversion layer can be formed under the sidewall gate to form source / drain extension regions even without biasing the sidewall gate. There is no need to form contacts for the circuit, which not only simplifies the process but also reduces the area of the transistor.

In addition, since the impurity ion implantation process is not necessary to lower the threshold voltage of the sidewall gate, there is no problem of changing the threshold voltage of the main gate due to impurity implantation, and there is no need to apply a constant bias to the sidewall gate. Parasitic capacitance between the main and main gates, parasitic capacitance between the sidewall gate and the body, and parasitic capacitance between the sidewall gate and the source and drain cause a delay in the sidewall gate bias voltage, thereby reducing the transistor performance. In addition, there is no leakage current due to the sidewall gate bias applied voltage, and the problem of insulation film degradation between the sidewall gate and the main gate does not occur.

In addition, the coupling between the sidewall gate insulating oxide film and the sidewall gate oxide film is adjusted so that the voltage applied to the main gate is induced to the sidewall gate by a predetermined amount. The parasitic resistance of the extended region can be further reduced and the amount of inverted layer can be decreased in the OFF state to increase the parasitic resistance of the source / drain extended region to dynamically change the amount of the inverted layer according to the on or off state. Therefore, the current in the on state can be increased to the maximum to realize a high performance transistor, and in the off state, the low leakage transistor can be simultaneously implemented by minimizing the off-current.

Claims (7)

A gate insulating film having a predetermined width formed on the semiconductor substrate; A main gate formed on a central portion of the gate insulating film and having a width smaller than that of the gate insulating film; Sidewall insulating layers formed on both sidewalls of the main gate; Sidewall gates disposed on both sides of the main gate and formed on an edge portion of the gate insulating layer and the sidewall insulating layer that are not applied by the main gate, and in which holes or electrons are injected; And Source and drain regions formed in the semiconductor substrate on both sides of the sidewall gate Morse transistor comprising a. The method of claim 1, A MOS transistor, in which positive charges are injected instead of the holes, or negative charges are injected instead of the electrons. The method of claim 2, And a MOS transistor doped with impurities in the main gate. The method of claim 2, A MOS transistor doped with impurities in the sidewall gate. The method of claim 1, A MOS transistor doped with impurities in a semiconductor substrate under the sidewall gate. The method according to any one of claims 1 to 5, And the sidewall insulating film has a thickness thinner than an edge portion of the gate insulating film remaining without being applied by the main gate. The method according to any one of claims 1 to 5, And a sidewall insulating film having a higher dielectric constant than an edge portion of the gate insulating film remaining without being applied by the main gate.

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