KR100525114B1 - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
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- KR100525114B1 KR100525114B1 KR1019980055131A KR19980055131A KR100525114B1 KR 100525114 B1 KR100525114 B1 KR 100525114B1 KR 1019980055131 A KR1019980055131 A KR 1019980055131A KR 19980055131 A KR19980055131 A KR 19980055131A KR 100525114 B1 KR100525114 B1 KR 100525114B1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0147—Manufacturing their gate sidewall spacers
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/013—Manufacturing their source or drain regions, e.g. silicided source or drain regions
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0135—Manufacturing their gate conductors
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- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
본 발명은 반도체소자의 제조방법에 관한 것으로, 종래에는 게이트를 형성한 후, 산화막측벽을 형성함에 따라 산화막측벽 만큼의 마진이 고려되어야 하고, 소스/드레인과 접촉되는 콘택 형성시에 오정렬에 대한 마진을 확보하기 어려운 문제점이 있었다. 따라서, 본 발명은 반도체기판의 상부에 버퍼산화막과 질화막을 형성한 후, 사진식각공정을 통해 질화막의 일부를 식각하여 버퍼산화막을 노출시키는 공정과; 상기 버퍼산화막이 노출된 구조물의 상부에 절연막을 증착한 후, 에치-백하여 식각된 질화막의 측면에 절연막측벽을 형성하는 공정과; 상기 노출된 버퍼산화막을 제거하고, 산화공정을 통해 게이트산화막을 형성하는 공정과; 상기 게이트산화막의 상부에 폴리실리콘과 캡산화막을 증착한 후, 에치백하여 캡산화막, 폴리실리콘 및 게이트산화막이 적층되는 게이트를 형성하는 공정과; 상기 질화막을 제거한 후, 게이트 및 절연막측벽을 마스크로 하여 반도체기판 내에 불순물이온을 주입하여 소스/드레인을 형성하는 공정으로 이루어지는 반도체소자의 제조방법을 통해 산화막측벽을 형성한 후, 산화막측벽 사이에 게이트를 형성함에 따라 게이트의 크기를 최소화할 수 있으며, 소스/드레인의 노출되는 면적이 종래에 비해 산화막측벽이 형성되는 영역만큼 넓어지므로, 고집적 메모리셀에서 콘택 형성시에 오정렬에 대한 마진을 확보할 수 있게 되어 메모리셀의 고집적화를 실현할 수 있는 효과가 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In the related art, as the oxide sidewall is formed after the gate is formed, the margin as much as the oxide sidewall must be considered, and margins for misalignment during contact formation in contact with the source / drain. There was a difficult problem to secure. Accordingly, the present invention includes forming a buffer oxide film and a nitride film on the semiconductor substrate, and then etching a part of the nitride film through a photolithography process to expose the buffer oxide film; Depositing an insulating film on the structure where the buffer oxide film is exposed, and then etching-back to form an insulating film side wall on the side of the etched nitride film; Removing the exposed buffer oxide film and forming a gate oxide film through an oxidation process; Depositing a polysilicon and a cap oxide film on the gate oxide film, and then etching back to form a gate in which the cap oxide film, the polysilicon, and the gate oxide film are stacked; After the nitride film is removed, an oxide film side wall is formed through a method of fabricating a semiconductor device, which includes a process of implanting impurity ions into a semiconductor substrate using a gate and an insulating film side wall as a mask to form a source / drain, and then forming a gate between the oxide film side walls. The size of the gate can be minimized by forming a, and since the exposed area of the source / drain becomes wider as the area where the oxide side wall is formed, the margin for misalignment can be secured when forming a contact in a highly integrated memory cell. As a result, high integration of memory cells can be realized.
Description
본 발명은 반도체소자의 제조방법에 관한 것으로, 특히 고집적 메모리셀의 게이트(first gate)를 최소화하여 집적도를 향상시킴과 아울러 콘택(contact)의 공정마진을 확보하기에 적당하도록 한 반도체소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device, which is suitable for minimizing the first gate of a highly integrated memory cell to improve integration and to secure a process margin of contact. It is about.
종래 반도체소자의 제조방법을 도1에 도시한 단면도를 참조하여 상세히 설명하면 다음과 같다.A method of manufacturing a conventional semiconductor device will be described in detail with reference to the cross-sectional view shown in FIG.
먼저, 반도체기판(1) 상에 게이트산화막(2), 폴리실리콘(3) 및 캡산화막(4)을 순차적으로 형성한 후, 사진식각공정을 통해 패터닝하여 캡산화막(4), 폴리실리콘(3) 및 게이트산화막(2)이 적층되는 제1,제2게이트를 서로 이격하여 형성한다.First, the gate oxide film 2, the polysilicon 3, and the cap oxide film 4 are sequentially formed on the semiconductor substrate 1, and then patterned by a photolithography process to form the cap oxide film 4 and the polysilicon 3. ) And the first and second gates on which the gate oxide film 2 is stacked are formed to be spaced apart from each other.
그리고, 상기 제1,제2게이트를 마스크로 하여 반도체기판(1) 내에 불순물이온을 저농도로 주입하여 엘디디영역(5)을 형성한다.The LED region 5 is formed by implanting impurity ions at low concentration into the semiconductor substrate 1 using the first and second gates as masks.
그리고, 상기 엘디디영역(5)이 형성된 구조물의 상부전면에 산화막을 증착한 후, 에치-백(etch-back)하여 상기 제1,제2게이트의 측면에 산화막측벽(6)을 형성한다.In addition, an oxide film is deposited on the top surface of the structure in which the LED region 5 is formed, and then etched back to form an oxide film side wall 6 on the side surfaces of the first and second gates.
그리고, 상기 산화막측벽(6) 및 제1,제2게이트를 마스크로 하여 반도체기판(1) 내에 불순물이온을 고농도로 주입하여 소스/드레인(7)을 형성한다.A source / drain 7 is formed by implanting impurity ions at a high concentration into the semiconductor substrate 1 using the oxide side wall 6 and the first and second gates as masks.
그러나, 상기한 바와같은 종래 반도체소자의 제조방법은 게이트영역을 정의하여 게이트를 형성한 후, 게이트의 측면 및 소스/드레인 상부에 산화막측벽을 형성함에 따라 산화막측벽 만큼의 마진이 고려되어야 함으로써, 셀면적이 증가됨과 아울러 메모리셀이 점점더 고집적화됨에 따라 디자인룰(design rule)이 감소하여 후속 공정중 하나인 소스/드레인과 접촉되는 콘택 형성시에 오정렬(misalign)에 대한 마진을 확보하기 어려운 문제점이 있었다.However, in the conventional method of manufacturing a semiconductor device as described above, after forming a gate by defining a gate region, the margin of the oxide side wall should be considered as the oxide side wall is formed on the side of the gate and the upper portion of the source / drain. As the area is increased and memory cells become more highly integrated, design rules are reduced, making it difficult to secure misalignment margins when forming contacts in contact with the source / drain, one of the subsequent processes. there was.
본 발명은 상기한 바와같은 종래의 문제점을 해결하기 위하여 창안한 것으로, 본 발명의 목적은 고집적 메모리셀의 게이트를 최소화하여 집적도를 향상시킴과 아울러 콘택의 공정마진을 확보할 수 있는 반도체소자의 제조방법을 제공하는데 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the conventional problems as described above, and an object of the present invention is to minimize the gate of a highly integrated memory cell to improve the degree of integration and to manufacture a semiconductor device capable of securing a process margin of a contact. To provide a method.
상기한 바와같은 본 발명의 목적을 달성하기 위한 반도체소자 제조방법의 바람직한 일 실시예는 반도체기판의 상부에 버퍼산화막과 질화막을 형성한 후, 사진식각공정을 통해 질화막의 일부를 식각하여 버퍼산화막을 노출시키는 공정과; 상기 버퍼산화막이 노출된 구조물의 상부에 절연막을 증착한 후, 에치-백하여 식각된 질화막의 측면에 절연막측벽을 형성하는 공정과; 상기 질화막 및 절연막측벽을 마스크로 사용하여 버퍼산화막의 노출된 부분을 제거하여 상기 반도체기판을 노출시키고 산화공정을 통해 게이트산화막을 형성하는 공정과; 상기 게이트산화막의 상부에 폴리실리콘과 캡산화막을 증착한 후, 에치백하여 캡산화막, 폴리실리콘 및 게이트산화막이 적층되는 게이트를 형성하는 공정과; 상기 질화막 및 상기 버퍼산화막의 노출된 부분을 제거한 후, 게이트 및 절연막측벽을 마스크로 하여 상기 반도체기판에 저농도 불순물이온을 경사지게 주입하여 절연막측벽과 중첩되는 엘디디영역을 형성하고 연속해서 고농도 불순물이온을 수직으로 주입하여 소스/드레인을 형성하는 공정을 구비하여 이루어지는 것을 특징으로 한다.According to an embodiment of the present invention, a buffer oxide film and a nitride film are formed on an upper surface of a semiconductor substrate, and then a portion of the nitride film is etched through a photolithography process to form a buffer oxide film. Exposing; Depositing an insulating film on the structure where the buffer oxide film is exposed, and then etching-back to form an insulating film side wall on the side of the etched nitride film; Removing the exposed portion of the buffer oxide film using the nitride film and the insulating film side wall as a mask to expose the semiconductor substrate and form a gate oxide film through an oxidation process; Depositing a polysilicon and a cap oxide film on the gate oxide film, and then etching back to form a gate in which the cap oxide film, the polysilicon, and the gate oxide film are stacked; After the exposed portions of the nitride film and the buffer oxide film are removed, low concentration impurity ions are inclined to the semiconductor substrate using the gate and the insulating film side wall as masks to form an LED region overlapping the insulating film side wall, and subsequently to form a high concentration impurity ion. It is characterized in that it comprises a step of forming a source / drain by vertical injection.
상기한 바와같은 본 발명에 의한 반도체소자 제조방법의 바람직한 일 실시예를 도2a 내지 도2f에 도시한 수순단면도를 참조하여 상세히 설명하면 다음과 같다.A preferred embodiment of the semiconductor device manufacturing method according to the present invention as described above will be described in detail with reference to the procedure cross-sectional view shown in Figs. 2a to 2f.
먼저, 도2a에 도시한 바와같이 반도체기판(11)의 상부에 버퍼산화막(12)과 질화막(13)을 순차적으로 형성한다. 이때, 버퍼산화막(12)은 질화막(13)에 의한 반도체기판(11)의 손상(damage)을 방지하기 위하여 형성한다.First, as shown in FIG. 2A, a buffer oxide film 12 and a nitride film 13 are sequentially formed on the semiconductor substrate 11. At this time, the buffer oxide film 12 is formed to prevent damage of the semiconductor substrate 11 by the nitride film 13.
그리고, 도2b에 도시한 바와같이 사진식각공정을 통해 상기 질화막(13)의 일부를 식각하여 버퍼산화막(12)을 노출시킨다. 이때, 사진식각공정은 질화막(13)의 상부에 감광막을 도포한 후, 노광 및 현상하여 감광막 패턴을 형성하고, 이를 적용하여 노출된 질화막(13)을 식각하는 일련의 공정으로, 필요에 따라 질화막(13)이 식각되는 영역을 다수개로 형성할 수 있다.As shown in FIG. 2B, a portion of the nitride layer 13 is etched through a photolithography process to expose the buffer oxide layer 12. At this time, the photolithography process is a series of processes for applying a photoresist film on top of the nitride film 13, and then exposing and developing to form a photoresist pattern, and etching the exposed nitride film 13 by applying the same. A plurality of regions in which (13) is etched can be formed.
그리고, 도2c에 도시한 바와같이 상기 버퍼산화막(12)이 노출된 구조물의 상부에 절연막으로 산화막을 증착한 후, 에치-백하여 상기 식각된 질화막(13)의 측면에 산화막측벽(14)을 형성한다.As shown in FIG. 2C, an oxide film is deposited as an insulating film on the structure where the buffer oxide film 12 is exposed, and then etched back to form an oxide film side wall 14 on the side surface of the etched nitride film 13. Form.
그리고, 도2d에 도시한 바와같이 상기 노출된 버퍼산화막(12)을 제거하고, 산화공정을 통해 게이트산화막(15)을 형성한다.As shown in FIG. 2D, the exposed buffer oxide film 12 is removed and a gate oxide film 15 is formed through an oxidation process.
그리고, 도2e에 도시한 바와같이 상기 게이트산화막(15)의 상부에 폴리실리콘(16)과 캡산화막(17)을 증착한 후, 에치-백하여 캡산화막(17), 폴리실리콘(16) 및 게이트산화막(15)이 적층되는 제1,제2게이트를 형성한다.As shown in FIG. 2E, the polysilicon 16 and the cap oxide layer 17 are deposited on the gate oxide layer 15, and then etched back to form the cap oxide layer 17, the polysilicon 16, and the like. First and second gates on which the gate oxide layer 15 is stacked are formed.
그리고, 도2f에 도시한 바와같이 상기 질화막(13)을 제거한 후, 제1,제2게이트 및 산화막측벽(14)을 마스크로 하여 반도체기판(11) 내에 불순물이온을 주입하여 소스/드레인(19)을 형성한다. 이때, 제1,제2게이트 및 산화막측벽(14)을 마스크로 하여 반도체기판(11) 내에 불순물이온을 주입하는 공정은 먼저, 저농도 불순물이온을 경사지게 주입하여 산화막측벽(14)의 하부 반도체기판(11) 내에 엘디디영역(18)을 형성한 후, 고농도 불순물이온을 수직으로 주입하여 소스/드레인(19)을 형성하는 것이 바람직하다.As shown in FIG. 2F, after the nitride film 13 is removed, impurity ions are implanted into the semiconductor substrate 11 using the first and second gates and the oxide film side wall 14 as a mask. ). At this time, the process of implanting impurity ions into the semiconductor substrate 11 using the first and second gates and the oxide film side wall 14 as a mask, firstly inclinedly implants the low concentration impurity ions into the lower semiconductor substrate of the oxide film side wall 14 ( 11) After the LED region 18 is formed, it is preferable to form the source / drain 19 by vertically injecting high concentration impurity ions.
상기한 바와같은 본 발명에 의한 반도체소자의 제조방법은 게이트영역을 정의하여 산화막측벽을 형성한 후, 산화막측벽 사이에 게이트를 형성함에 따라 게이트의 크기를 최소화할 수 있으며, 소스/드레인의 노출되는 면적이 종래에 비해 산화막측벽이 형성되는 영역만큼 넓어지므로, 고집적 메모리셀에서 콘택 형성시에 오정렬에 대한 마진을 확보할 수 있게 되어 메모리셀의 고집적화를 실현할 수 있는 효과가 있다.According to the method of manufacturing a semiconductor device according to the present invention as described above, the gate region is defined to form an oxide sidewall, and a gate is formed between the oxide sidewalls, thereby minimizing the size of the gate and exposing the source / drain. Since the area becomes wider than the area where the oxide film side wall is formed compared with the related art, a margin for misalignment can be secured at the time of contact formation in a highly integrated memory cell, thereby achieving high integration of the memory cell.
도1은 종래의 반도체소자를 보인 단면도.1 is a cross-sectional view showing a conventional semiconductor device.
도2는 본 발명의 일 실시예를 보인 수순단면도.Figure 2 is a cross-sectional view showing an embodiment of the present invention.
***도면의 주요 부분에 대한 부호의 설명****** Description of the symbols for the main parts of the drawings ***
11:반도체기판 12:버퍼산화막11: semiconductor substrate 12: buffer oxide film
13:질화막 14:산화막측벽13: nitride film 14: oxide film side wall
15:게이트산화막 16:폴리실리콘15: gate oxide film 16: polysilicon
17:캡산화막 18:엘디디영역17: cap oxide film 18: LED area
19:소스/드레인19: source / drain
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Citations (5)
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|---|---|---|---|---|
| US5552329A (en) * | 1994-01-05 | 1996-09-03 | Lg Semicon Co., Ltd. | Method of making metal oxide semiconductor transistors |
| KR0154303B1 (en) * | 1995-10-31 | 1998-12-01 | 김광호 | Method of fabricating mosfet |
| KR0171068B1 (en) * | 1994-11-18 | 1999-02-01 | 문정환 | Method of fabricating a semiconductor device |
| KR20000024755A (en) * | 1998-10-01 | 2000-05-06 | 윤종용 | Method for forming gate electrode of semiconductor device |
| KR20000031758A (en) * | 1998-11-10 | 2000-06-05 | 김영환 | Method for producing semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5552329A (en) * | 1994-01-05 | 1996-09-03 | Lg Semicon Co., Ltd. | Method of making metal oxide semiconductor transistors |
| KR0171068B1 (en) * | 1994-11-18 | 1999-02-01 | 문정환 | Method of fabricating a semiconductor device |
| KR0154303B1 (en) * | 1995-10-31 | 1998-12-01 | 김광호 | Method of fabricating mosfet |
| KR20000024755A (en) * | 1998-10-01 | 2000-05-06 | 윤종용 | Method for forming gate electrode of semiconductor device |
| KR20000031758A (en) * | 1998-11-10 | 2000-06-05 | 김영환 | Method for producing semiconductor device |
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