KR100459931B1 - Method for manufacturing semiconductor device using damascene method - Google Patents

Abstract

The present invention relates to a method for fabricating a semiconductor device using a damascene method, wherein a first oxide film, a first nitride film, and a sacrificial film are sequentially formed on a semiconductor substrate, and the sacrificial film and the first nitride film are etched to form a residual sacrificial film pattern. Forming a; Performing an ion implantation process using the residual sacrificial layer pattern as a mask to form an LDD ion implantation layer in a semiconductor substrate; Forming spacers on both sides of the residual sacrificial layer pattern; Forming a source / drain ion implantation layer on a lower portion of the LDD ion implantation layer by performing an ion implantation process using the residual sacrificial layer pattern and the spacer as a mask; Forming a source / drain region by thermally forming a second nitride film and a second oxide film over the entire product in turn; After performing the CMP process on the second oxide film and the second nitride film so that the upper surface of the remaining sacrificial film pattern is exposed, the residual sacrificial film pattern is etched and removed, and the lower portion of the remaining sacrificial film pattern is disposed. Etching the first oxide film; Performing an ion implantation process in the semiconductor substrate between the second spacers to form a punch-stop ion implantation layer; And forming a gate insulating film in a portion from which the first oxide film is removed, and forming a gate in a portion from which the residual sacrificial film pattern is removed.

Description

Method for manufacturing semiconductor device using damascene method {Method for manufacturing semiconductor device using damascene method}

The present invention relates to a method of manufacturing a semiconductor device using a damascene method, and more particularly, to a method of manufacturing a semiconductor device for reducing damage to an active region by first forming a source / drain region and then using a damascene method. will be.

In the prior art of fabricating transistors using the damascene process, not only the active region is damaged when the spacer is etched, but the substrate is formed even when the sacrificial film is removed, thereby providing a uniform gate insulating film. Since there is a difficulty in forming the structure, there is a problem of lowering the reliability of the device.

Accordingly, the present invention has been made to solve the above-mentioned problems of the prior art, and by using the nitride film as an etch stop layer in order to reduce the damage of the active region during the process, it is possible to minimize the damage of the active region and to provide excellent reliability of the semiconductor device. The purpose is to provide a manufacturing method.

1A to 1E are cross-sectional views illustrating a method of manufacturing a semiconductor device using the damascene method according to the present invention.

(Code description of main parts of drawing)

5: semiconductor substrate 10, 10a: first oxide film

20, 20a: first nitride film 25, 25a: sacrificial film

30 mask 40 spacer

50: LDD ion implantation layer 55: source / drain region

60 source / drain ion implantation layer 70, 70a: second nitride film

80, 80a: second oxide film 100: punch-stop ion implantation layer

200: gate insulating film 300: gate

According to an aspect of the present invention, there is provided a method including: forming a first sacrificial layer, a first nitride layer, and a sacrificial layer on a semiconductor substrate, and then etching the sacrificial layer and the first nitride layer to form a residual sacrificial layer pattern; Performing an ion implantation process using the residual sacrificial layer pattern as a mask to form an LDD ion implantation layer in a semiconductor substrate; Forming spacers on both sides of the residual sacrificial layer pattern; Forming a source / drain ion implantation layer on a lower portion of the LDD ion implantation layer by performing an ion implantation process using the residual sacrificial layer pattern and the spacer as a mask; Forming a source / drain region by thermally forming a second nitride film and a second oxide film over the entire product in turn; After performing the CMP process on the second oxide film and the second nitride film so that the upper surface of the remaining sacrificial film pattern is exposed, the residual sacrificial film pattern is etched and removed, and the lower portion of the remaining sacrificial film pattern is disposed. Etching the first oxide film; Performing an ion implantation process in the semiconductor substrate between the second spacers to form a punch-stop ion implantation layer; And forming a gate insulating layer in a portion from which the first oxide layer has been removed, and forming a gate in a portion from which the residual sacrificial layer pattern is removed.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, as shown in FIG. 1A, the first oxide film 10, the first nitride film 20, and the polysilicon sacrificial film 25 are sequentially deposited on the semiconductor substrate 5, and then the mask pattern 30 is disposed thereon. To form.

Next, as shown in FIG. 1B, the polysilicon sacrificial layer 25 is dry-etched using the mask pattern 30 to form a residual sacrificial layer 25a, and then an ion implantation process is performed to LDD. An ion implantation layer 50 is formed above the source / drain ion implantation layer to be formed subsequently.

In this case, when the sacrificial layer 25 is etched, the first nitride layer 20 is used as an etch stop layer, and when the first nitride layer 20 is etched, the first oxide layer 10 is used as an etch stop layer. In addition, the first oxide film 10 is used as an ion implantation buffer film during the LDD ion implantation.

Subsequently, after the deposition of a spacer film (not shown), the spacer film is etched entirely to form spacers 40 on both sides of the residual sacrificial film 25a.

Thereafter, an ion implantation process using the residual sacrificial film 25a and the spacer 40 as a mask is performed, so that the source / drain ion implantation layer 60 is formed in the semiconductor substrate 5 below both sides of the first spacer 40. To form. In this case, the source / drain ion implantation layer 60 is formed below the LDD ion implantation layer 50, and uses the first oxide film 10 as an ion implantation buffer layer when the source / drain ion implantation is performed. .

Subsequently, as illustrated in FIG. 1C, a second nitride film 70 and a second oxide film 80 are sequentially deposited on the whole of the resultant product. In this case, the second oxide film 80 may be formed in multiple layers.

Next, a thermal process is performed on the LDD ion implantation layer 50 and the source / drain ion implantation layer 60 to form a source / drain region 55.

Subsequently, as illustrated in FIG. 1D, the CMP process is performed on the second oxide film 80 and the second nitride film 70 to planarize such that the upper surface of the residual sacrificial film 25a is exposed. As a result, the second residual oxide film 80a and the second residual nitride film 70a are formed. At this time, when performing the CMP process, the second nitride film 70 is used as the CMP stop layer.

Next, a wet etching process is performed on the whole of the resultant to completely remove the residual sacrificial layer 25a. In this case, the wet oxide of the residual sacrificial layer 25a is used as the etch stop layer. The first oxide film 10 under the gate forming portion is wet-etched to form a first residual oxide film 10a.

Subsequently, a punch-stop ion implantation layer 100 is formed using an ion implantation method between the source / drain regions 55, which are lower portions of the gate to be subsequently formed. In this case, the punch-stop ion implantation layer 100 may be applied by replacing the threshold voltage (Vth) -controlled ion implantation layer.

Subsequently, as illustrated in FIG. 1E, the gate insulating layer 200 is formed in the portion where the first oxide layer is removed. Then, a polysilicon layer is finally deposited on the upper surface of the entire structure including the gate forming portion and then planarized to form the gate 300 in the gate forming portion.

As described above, the present invention reduces the SCE (Short Channel Effect) of the transistor by reducing the damage of the active region by first forming a source / drain region, and then damaging the active region, and reducing the transistor induced barrier lowering (DIBL) of the transistor. By reducing, a transistor having excellent characteristics can be manufactured.

In addition, a transistor having excellent characteristics can be manufactured by minimizing the invasion of the active region.

On the other hand, the present invention is not limited to the above-described specific preferred embodiments, and various changes can be made by those skilled in the art without departing from the gist of the invention claimed in the claims. will be.

Claims (10)

Forming a first sacrificial layer and a first nitride layer and a sacrificial layer on a semiconductor substrate, and then etching the sacrificial layer and the first nitride layer to form a residual sacrificial layer pattern; Performing an ion implantation process using the residual sacrificial layer pattern as a mask to form an LDD ion implantation layer in a semiconductor substrate; Forming spacers on both sides of the residual sacrificial layer pattern; Forming a source / drain ion implantation layer on a lower portion of the LDD ion implantation layer by performing an ion implantation process using the residual sacrificial layer pattern and the spacer as a mask; Forming a source / drain region by thermally forming a second nitride film and a second oxide film over the entire product in turn; After performing the CMP process on the second oxide film and the second nitride film so that the upper surface of the remaining sacrificial film pattern is exposed, the residual sacrificial film pattern is etched and removed, and the second portion of the lower portion of the remaining sacrificial film pattern is removed. Etching the oxide film; Performing an ion implantation process in the semiconductor substrate between the second spacers to form a punch-stop ion implantation layer; And And forming a gate insulating film in a portion from which the first oxide film has been removed, and forming a gate in a portion from which the residual sacrificial film pattern has been removed. The semiconductor device of claim 1, wherein the first nitride layer is used as an etch stop layer when the sacrificial layer is etched, and the first oxide layer is used as an etch stop layer when the first nitride layer is etched. Way. The method of claim 1, wherein the source / drain regions are formed first, and then the gate insulating layer and the gate are formed. The method of claim 1, wherein the first nitride film and the first oxide film are etched by wet etching. The method of claim 1, wherein polysilicon is used as the sacrificial film. The method of claim 1, wherein the second oxide film is formed in multiple layers. The method of claim 1, wherein the first nitride film forming process is omitted when the sacrificial film and the first oxide film are etched. 2. The method of claim 1, wherein the punch-stop ion implantation layer is replaced with a threshold voltage controlled ion implantation layer. The method of claim 1, wherein the second nitride film is used as a CMP stop layer in the CMP process. The method of claim 1, wherein the first oxide layer is used as an ion implantation buffer layer during the LDD ion implantation and the source / drain ion implantation.