KR100301810B1 - Semiconductor memory device and method for fabricating the same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor memory device in which bit lines are formed simultaneously in forming trench isolation layers to simplify the manufacturing process. Patterning with; Etching the exposed semiconductor substrate using the patterned nitride layer as a mask to form a trench; Forming a second oxide film on the trench bottom and side surfaces by an oxidation process; Forming a bit line by forming a poly side layer on the front surface and planarizing the poly side layer to a partial depth of the trench by the CMP process; Forming a third oxide film on portions other than the nitride layer, removing portions of the nitride layer, the first oxide film, and the third oxide film, and forming a gate oxide film over the entire surface; Forming a gate line on the gate oxide layer and forming a nitride sidewall on a side of the gate line; Forming an ILD layer on the entire surface including the gate line having the sidewalls and selectively etching the ILD layer on the bit line to form a bit line contact hole; And forming a plug layer filling the bit line contact hole.

Description

Semiconductor memory device and method for fabricating the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly, to a method of manufacturing a semiconductor memory device in which bit lines are simultaneously formed at the time of forming a trench isolation layer to be suitable for simplifying the manufacturing process and structure.

Hereinafter, a semiconductor memory device of the related art and a manufacturing process thereof will be described with reference to the accompanying drawings.

1 is a layout view of a semiconductor memory device of the prior art, and FIGS. 2A to 2G are cross-sectional views illustrating a method of manufacturing a semiconductor device of the prior art.

In the prior art semiconductor memory device, for example, in a planar configuration, a linear active region 1 is isolated by an element isolation region, and a gate line 2 and an active region crossing the active region 1. Plug layer (3) formed between the gate line (2) configured to cross the (1), connected to the plug layer 3 through the bit line contact layer (4) to the vertical direction of the gate line (2) It consists of a bit line 5 formed between the active regions (1).

In the conventional memory device configured as described above, the active regions 1 are formed in a line shape, and an isolation layer is formed between the active regions 1 and the gate line 2.

The manufacturing process of such a semiconductor memory device of the prior art is as follows.

First, as shown in FIG. 2A, the first oxide film 2 and the nitride layer 3 are sequentially formed on the entire surface of the semiconductor substrate 1.

A photoresist layer (not shown) is formed on the nitride layer 3 and selectively patterned so as to remain only on the active region.

The exposed nitride layer 3 and the first oxide film 2 are selectively etched using the patterned photoresist layer as a mask.

Next, the trench is formed by removing the photoresist layer and etching the device isolation region of the exposed semiconductor substrate 1 using the patterned nitride layer 3 and the first oxide layer 2 as a mask.

The oxidation process is performed to form a second oxide film 4 on the trench bottom and side surfaces.

Subsequently, as shown in FIG. 2B, an insulating material layer 5 is formed on the entire surface including the trench and planarized by a chemical mechanical polishing (CMP) process to form a device isolation layer.

The device isolation layer is formed at the same height as the upper surface of the semiconductor substrate 1.

2C, the exposed nitride layer 3 and the first oxide film 2 on the upper surface are removed.

Subsequently, the gate oxide layer 6 is formed on the entire surface, and the gate forming material layer 7 and the gate cap nitride layer 8 are sequentially formed.

A gate line is formed by selectively patterning the gate cap nitride layer 8 and the gate forming material layer 7 by a photolithography process.

Subsequently, as shown in FIG. 2D, a stopper nitride layer 9 is deposited on the entire surface including the gate line and etched back to form sidewalls on the side of the gate line and form an ILD layer 10 on the gate line. .

As shown in FIG. 2E, the ILD layer 10 is etched by a self-aligned contact process to form a plug contact hole 11.

Subsequently, as shown in FIG. 2F, the plug poly layer is deposited and etched back on the entire surface including the plug contact hole 11 to form the plug layer 12.

The second oxide film 13 is deposited on the entire surface including the plug layer 12.

Next, as shown in FIG. 2G, a bit line contact hole is formed by selectively etching the second oxide layer 13 on the plug layer 12, and the bit line poly layer 14 is formed on the entire surface including the bit line contact hole. Tungsten silicide layer 15 is deposited and selectively patterned to form bit lines.

The semiconductor memory device of the related art forms a bit line on the gate line by using a plug layer and a bit line contact to form a bit line in a line-type active structure.

The semiconductor memory device of the prior art has the following problems.

First, since the bit line is formed on the gate line, the step is large, thus increasing the difficulty of the subsequent contact process and the planarization process between the cell and another region.

Second, a plug structure other than a bit line contact is added on the line type active structure.

Third, a lot of interlayer insulating films are required to isolate each layer, which increases the complexity of the process.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem of the prior art semiconductor memory device, and provides a method for manufacturing a semiconductor memory device suitable for simplifying the manufacturing process by simultaneously forming bit lines at the time of forming the trench isolation layer. The purpose is.

1 is a layout view of a conventional semiconductor memory device

2A to 2G are cross-sectional views illustrating a method of manufacturing a semiconductor device of the prior art.

3 is a layout view of a semiconductor memory device according to the present invention;

4A to 4G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

Explanation of symbols for main parts of the drawings

41. Semiconductor Substrate 42. First Oxide Film

43. Nitride layer 44. Second oxide film

45. Tungsten silicide layer 46. Bitline poly layer

47. Third oxide film 48. Gate oxide film

49. Gate poly layer 50. Gate cap nitride layer

51. Stopper nitride layer 52. ILD layer

53. Bitline contact hole 54. Poly plug layer

A method of manufacturing a semiconductor memory device according to the present invention for achieving the above object comprises the steps of sequentially forming and selectively patterning a first oxide film, a nitride layer on the entire surface of the semiconductor substrate; Etching the exposed semiconductor substrate using the patterned nitride layer as a mask to form a trench; Forming a second oxide film on the trench bottom and side surfaces by an oxidation process; Forming a bit line by forming a poly side layer on the front surface and planarizing the poly side layer to a partial depth of the trench by the CMP process; Forming a third oxide film on portions other than the nitride layer, removing portions of the nitride layer, the first oxide film, and the third oxide film, and forming a gate oxide film over the entire surface; Forming a gate line on the gate oxide layer and forming a nitride sidewall on a side of the gate line; Forming an ILD layer on the entire surface including the gate line having the sidewalls and selectively etching the ILD layer on the bit line to form a bit line contact hole; And forming a plug layer filling the bit line contact hole.

Hereinafter, a semiconductor memory device and a manufacturing process thereof according to the present invention will be described with reference to the accompanying drawings.

3 is a layout view of a semiconductor memory device according to the present invention, and FIGS. 4A to 4G are cross-sectional views illustrating a method of manufacturing the semiconductor device according to the present invention.

The present invention is to form a bit line in a semiconductor substrate to eliminate the planarization process, plug formation process and the like of the interlayer insulating film.

First, an active region formed between a bit line 31 formed in a surface of a semiconductor substrate, a gate line 32 formed thereon in a form crossing the bit line 31, and the bit lines 31. And a bit line contact layer 34 connecting the active region 33 and the bit line 31.

The structure is first insulated from the semiconductor substrate 41, the active region 33 formed with the long axis in the first direction of the semiconductor substrate 41, and the active region 33 in the surface of the semiconductor substrate 41. A bit line 31 buried in the first direction, a gate oxide film 48 formed on the semiconductor substrate 41 on which the bit line 31 is formed, and a second direction perpendicular to the bit line 31. The ILD layer includes gate lines 32 formed to cross the active region 33 and contact holes formed on the bit lines 31 and is formed on the entire surface including the gate lines 32. And a poly plug layer 54 formed by filling the contact hole and connected to the bit line 31.

In the semiconductor memory device having the structure as described above, first, as shown in FIG. 4A, the first oxide film 42 and the nitride layer 43 are sequentially formed on the entire surface of the semiconductor substrate 41.

A photoresist layer (not shown) is formed on the nitride layer 43 and selectively patterned so as to remain only on the active region.

The exposed nitride layer 43 and the first oxide layer 42 are selectively etched using the patterned photoresist layer as a mask.

Next, the trench is formed by removing the photoresist layer and etching the device isolation region of the exposed semiconductor substrate 41 using the patterned nitride layer 43 and the first oxide layer 42 as a mask.

The oxidation process is performed to form a second oxide film 44 on the bottom and side surfaces of the trench.

Subsequently, as shown in FIG. 4B, a tungsten silicide layer 45 is deposited on the entire surface, and a bit line poly layer 46 is formed on the tungsten silicide layer 45.

4C, a polyside layer (not shown) is formed by an annealing process and the polyside layer is planarized by a CMP process to a part depth of the trench to form a bit line.

In the oxidation process, the third oxide film 47 is formed at the portion except the nitride layer 43.

Subsequently, as shown in FIG. 4D, portions of the nitride layer 43, the first oxide layer 42, and the third oxide layer 47 are removed and a gate oxide layer 48 is formed on the entire surface.

The gate poly layer 49 and the gate cap nitride layer 50 are deposited on the gate oxide layer 48 and selectively patterned by a photolithography process to form a gate line.

Subsequently, as shown in FIG. 4E, the stopper nitride layer 51 is deposited on the front surface including the gate line and etched back to form sidewalls (not shown in the cross section in the present cross-section as indicated by dotted lines) on the side of the gate line. do.

In addition, an ILD layer 52 is formed on the entire surface including the gate line on which the sidewalls are formed.

Next, as shown in FIG. 4F, the bit line contact hole 53 is formed by selectively etching the ILD layer 52 on the bit line where the gate line is not formed.

The bit line contact hole 53 is filled with polysilicon to form a poly plug layer 54.

The semiconductor memory device and the method of manufacturing the same according to the present invention are formed so that the bit line is embedded in the semiconductor substrate so that it is not necessary to form separate insulating layers and interlayer insulating layers.

Such a method of manufacturing a semiconductor memory device according to the present invention has the following effects.

Since the bit line is formed in the semiconductor substrate, it is possible to eliminate the planarization process and the plug process of the interlayer insulating film generated in the structure of forming the bit line on the upper side of the gate line.

This reduces the formation height of the cell region, which facilitates the etching process in subsequent memory and metal contacts, and facilitates the deposition of conductors in the contacts.

Claims (3)

Forming and selectively patterning a first oxide film and a nitride layer on the entire surface of the semiconductor substrate; Etching the exposed semiconductor substrate using the patterned nitride layer as a mask to form a trench; Forming a second oxide film on the trench bottom and side surfaces by an oxidation process; Forming a bit line by forming a poly side layer on the front surface and planarizing the poly side layer to a partial depth of a trench by a CMP process; Forming a third oxide film on portions other than the nitride layer, removing portions of the nitride layer, the first oxide film, and the third oxide film, and forming a gate oxide film over the entire surface; Forming a gate line on the gate oxide layer and forming a nitride sidewall on a side of the gate line; Forming an ILD layer on the entire surface including the gate line having the sidewalls and selectively etching the ILD layer on the bit line to form a bit line contact hole; And forming a plug layer filling the bit line contact hole. The method of claim 2, wherein the polyside layer is formed by sequentially depositing and annealing a tungsten silicide layer and a bitline poly layer. The method of claim 2, wherein the gate line is formed by depositing a gate poly layer and a gate cap nitride layer on the gate oxide layer and selectively patterning the same by a photolithography process.