KR100289056B1 - Manufacturing Method of Power Device Using Insulating Film Inclined Etch - Google Patents

Abstract

PURPOSE: A fabrication method of a power device is provided to increase a reliability of a power device by preventing a breakage of an insulating layer due to a high electric field at a gate extended region. CONSTITUTION: A p-channel LDMOS(Lateral Double Diffused MOS) having a silicon gate pattern(15) is formed by depositing a gate low temperature insulating layer(12) on a first gate oxide layer(11). After forming a first gate oxide layer(11a) and the gate low temperature insulating layer(12) on the gate extended region, the first gate oxide layer(11a) and the gate low temperature insulating layer(12) is etched slightly by a wet etching process using a photoresist mask. After growing a second gate oxide layer(13), an n-channel LDMOS having a polysilicon gate pattern(15) is formed, thereby reducing a surface step coverage by etching a portion of the field oxide layer of the n-channel and the p-channel LDMOS devices during the wet etching process of the gate low temperature insulating layer.

Description

Manufacturing Method of Power Device Using Insulating Film Inclined Etching

The present invention relates to a manufacturing process of a lateral double diffused MOS (LDMOS) device fabricated by using an insulator gradient etching process of a gate extension region in a drift region as a high voltage power device that can be used for driving ICs of PDP and FED. will be.

When the LDMOS is applied to a 100V power driving IC, the gate oxide film is thick at about 1500 to 3000 mW for the p-channel LDMOS, while the n-channel LDMOS is thin at about 200 to 300 mW. Therefore, in the n-channel LDMOS having a thin oxide film, dielectric breakdown occurs easily due to a high electric field when the oxide film in the gate extension region is operated, and the reliability of the device is drastically reduced.

1 is a cross-sectional view of a high voltage LDMOS fabricated by a conventional manufacturing process.

In the case of a 100V power driving IC, the gate insulating film grows a high temperature oxide film to about 1500 to 3000 kW thick for a p-channel LDMOS, and then grows a thin oxide film of about 200 to 300 kW thick and then forms a gate pattern with polysilicon. Therefore, the n-channel LDMOS remains a fragile portion where insulation breakdown occurs easily when a high field is applied to the oxide film of the gate extension region ('Le' region) in the n-drift region.

As described above, the gate extension region of the n-channel LDMOS is made equal to the thickness of the insulating layer of the channel region. The gate pattern of the polysilicon includes the gate channel region, the gate extension region, and even a partial region of the field oxide film in the n-drift region. Here, the gate extension region of the n-channel LDMOS remains a weak part where insulation breakdown occurs in terms of reliability when a high field is applied. In addition, when fabricating n-channel and p-channel LDMOS simultaneously, there is a disadvantage in that a step difference between interlayer insulating films is very large due to different gate oxide thicknesses.

SUMMARY OF THE INVENTION An object of the present invention is to fabricate an n-channel and p-channel LDMOS, in which the insulating film of the gate extension region of the n-channel LDMOS is inclined to form a high voltage in the gate extension region of a power device manufactured by a conventional device process. This is to improve the dielectric breakdown phenomenon and ultimately improve the reliability of the device.

In the present invention, a low-temperature insulating film is deposited on the oxide film of the gate extension region of the n-channel LDMOS to be inclined by wet etching, thereby improving the dielectric breakdown characteristics in the gate extension region, and simultaneously reducing the step difference between the interlayer dielectric layers and the p-channel LDMOS process. It provides a high voltage power device manufacturing method that can be manufactured.

In the present invention, it is important to incline the insulating film on the gate extension region in the n-drift region in the n-channel LDMOS. To implement this, as shown in FIG. 2, a low temperature insulating film is deposited to wet-etch the insulating film of the gate extension region by wet etching, and then a polycrystalline silicon is formed by forming a gate oxide film having a thickness of 200 to 300 n in the channel region of the n-channel LDMOS. Forming a gate pattern is an important process technology task.

1 is a cross-sectional view of a power device manufactured by a conventional manufacturing process.

2 is a cross-sectional view of a power device fabricated using an insulator etched in accordance with the present invention.

Figure 3 (a) to (g) is a flow chart of the manufacturing process of the power device using the insulating film gradient etching presented in the present invention.

<Description of the symbols for the main parts of the drawings>

1: p type silicon substrate

2: p epitaxial layer

3: deep n well region

4: p drift region

5: n drift region

6: n well region

7: p well region

8: buffer oxide layer

9: silicon notride layer

10: Field oxide layer

11, 11a: 1 ^st gate oxide layer

12: Gate low temperature insulator layer

13: the second gate oxide film (gate oxide layer 2 ^nd)

14: Photoresist

15 polysilicon gate pattern

16, 16a, 16b: p ⁺ diffusion region (p ⁺ diffused region)

17, 17a, 17b: n ⁺ diffusion region (n ⁺ diffused region)

18: interlayer dielectrics

19: Source electrode

20: Gate electrode

21: drain electrode

2 is a cross-sectional view of a device in which the insulating film of the gate extension region is inclined by wet etching in an n-channel LDMOS according to the present invention.

In the present invention, a first gate oxide film 11 having a thickness of about 300 to 1000 Å is formed on a p-channel LDMOS, and then a gate insulating film 12 having a thickness of about 1000 to 3,000 Å is deposited.

Subsequently, a portion of the insulating layer 12 and the field oxide layer 10 of the p-channel LDMOS region, the n-channel gate extension region, and the field oxide layer 10 are masked with a photoresist using a photolithography process, and then the gate of the n-channel LDMOS region is wet-etched. The low temperature insulating film 12 is etched obliquely.

After that, a second gate oxide film 13 having a thickness of 200 to 300 에 is formed in the n-channel LDMOS, and a gate pattern is formed of polysilicon.

Therefore, the high voltage power device manufactured according to the present invention can increase the reliability of the device by preventing the dielectric breakdown caused by the high field by inclining the insulating film of the gate extension region in the n-channel LDMOS. In addition, by using a low temperature insulating film deposition and wet etching method to obtain a sloped insulating film it is possible to reduce the step difference between the device structure manufactured by the conventional manufacturing process.

In the present invention, as shown in FIG. 2, in the case of n-channel LDMOS, a gate region made of polysilicon is formed by a thin gate oxide film of a channel region and a thin gate diffusion region ('Le' region of FIG. 2) in an n-drift region. Up to a portion of the oxide film and the inclined insulating film structure, and a portion of the low temperature insulating film over the field oxide film in the n-row region.

In the case of the p-channel LDMOS, the gate region of the polysilicon is composed of a high temperature oxide film and a low temperature insulating layer in the gate channel region and a gate extension region and a part of the low temperature insulating film on the field oxide film in the p-drift region.

In this case, the dielectric breakdown structure of the n-channel LDMOS can be implemented to improve the dielectric breakdown characteristics at the high voltage of the on state when the device is in operation, compared to the power device having the same thickness as the oxide film of the conventional device channel region.

In addition, it can be manufactured together with the p-channel LDMOS process as a low temperature insulating film process, and has the advantage of reducing the thin film step by using wet etching. As a high voltage power device, as in a conventional power device, a high breakdown voltage is maintained by promoting a reduced surface field (RESURF) effect, and a low on resistance can be obtained.

3 (a) to (g) show a preferred embodiment of an LDMOS having an inclined gate insulating film structure according to the present invention, and the manufacturing process is described step by step in (a) to (g). The manufacturing process described in the embodiment is a process capable of simultaneously fabricating n-channel and p-channel LDMOS.

As shown in (a) of FIG. 3, after forming a low concentration of the p epi layer 2 on the p-type silicon substrate 1 by using a general LDMOS manufacturing method, a photo transfer and etching process, impurity ions Deep n wells 3 are formed in regions where p-channel LDMOS is to be formed by implantation and high temperature heat treatment processes. Thereafter, the impurity concentration is increased to form the n well region 6 and the p drifting region 4 as the channel region, and the p well region 7 and the n drifting region 5 are formed to fabricate the n channel LDMOS.

Next, the buffer oxide film 8 is grown, and the nitride film 9 is deposited. Subsequently, in order to form a field oxide film in the isolation and drift region between the elements, the vaginal membrane 9 is removed by photolithography and dry etching.

As shown in FIG. 3B, after the field oxide film 10 is grown, the nitride film 9 and the buffer oxide film 8 are removed, and after the thin oxide film is grown, the threshold voltage of the p-channel LDMOS is controlled. For this purpose, all regions except the p-channel region are masked and ion implanted as n-type impurities, and then the thin oxide film is removed. Again, a primary gate oxide film 11 of about 300 to 1000 microns thick is grown. Subsequently, the low-temperature insulating film 12 is deposited to a thickness of about 1000 to 2000 Å to form a thick gate insulating film of the p-channel LDMOS, and then the p-channel LDMOS region, the gate extension portion of the n-channel LDMOS region, and a partial region of the field oxide film are deposited by a photo transfer process. Masked with the photosensitive film 14.

As shown in FIG. 3C, the low temperature insulating film 12 of the n-channel LDMOS is etched by using a wet etching method. In this case, the wet etching solution selects a dilute solution having a low etching ratio. Here, the low temperature insulating film 12 may be a single thin film or a multilayer insulating film having different etching ratios from each other. As a result, the gate extension region (the 'Le' region in FIG. 2) of the n-channel LDMOS has an inclined insulating film structure. Subsequently, after removing the photoresist layer 14, a thin oxide layer is grown, and all regions except for the n-channel region are masked to mask the p-channel LDMOS region to control the threshold voltage of the n-channel LDMOS, thereby implanting ions as p-type impurities. After that, the photoresist film is removed.

As shown in (d) of FIG. 3, after the polycrystalline silicon 15 is deposited and doped with n-type impurities, the polysilicon gate patterns 15 of the p-channel and n-channel LDMOS are photo transferred. It is formed by a process and an etching process.

As shown in (e) of FIG. 3, after masking the n-channel LDMOS region with the photoresist film 14 by a photolithography process, dry-etch a thick oxide film on the active region where a source / drain of the p-channel LDMOS region is to be formed. . Subsequently, the photosensitive film 14 is removed and a thin oxide film is grown.

As shown in FIG. 3 (f), the source regions 16 and 17 and the drain region 16a of the p-channel LDMOS, the source regions 16b and 17a and the drain region 17b of the n-channel LDMOS are formed. N-type and p-type impurities are ion implanted to form n ⁺ region and p ⁺ region, respectively. Subsequently, after the heat treatment process, the interlayer insulating film 18 is deposited at a low temperature.

As shown in (g) of FIG. 3, a contact region is formed by a photolithography process and a dry etching process, and then a metal thin film is deposited. Subsequently, when the metal wiring pattern is formed and the heat treatment step is performed by the photo transfer process and the dry etching process, n, which is a high voltage power device having a source electrode 19, a gate electrode 20, and a drain electrode 21, as shown in the present invention. Channel and p channel LDMOS are fabricated.

The present invention can improve the reliability of the device by solving the dielectric breakdown phenomenon in the gate extension region due to the high electric field which is a problem in the high voltage power device. In addition, the wet etching of the low-temperature insulating film has an advantage of reducing the step coverage of the thin film, and is a manufacturing process method for manufacturing the n-channel and p-channel LDMOS power devices together. The power device manufactured through the present invention may be widely applied to PDP and FED driving ICs in the future.

Claims (4)

In the method of manufacturing a high voltage power device for manufacturing a p-channel LDMOS and n-channel LDMOS on one substrate, Depositing a gate low temperature insulating film 12 on the primary gate oxide film 11 to form a p-channel LDMOS having a polycrystalline silicon gate pattern 15; After forming the primary gate oxide film 11a and the gate low temperature insulating film 12 on the gate extension region, wet etching is inclined using a photosensitive film mask, the secondary gate oxide film 13 is grown, and then a polysilicon gate pattern ( Forming an n-channel LDMOS having 15), And etching a part of the field oxide layers of the n-channel and p-channel LDMOS devices during wet etching of the gate low-temperature insulating layer to reduce surface step coverage. In the manufacturing method of the high voltage power device which manufactures p-channel LDMOS and n-channel LDMOS on a board | substrate by the manufacturing method of LDMOS, After forming the field oxide film 10 to form an active region of the p-channel LDMOS and the n-channel LDMOS using the LDMOS manufacturing method, After growing a thin oxide film, masking all regions except the p channel region to control the threshold voltage of the p-channel LDMOS, implanting ions as n-type impurities, removing the thin oxide film, and then removing the first gate oxide film 11 , 11a), depositing the low temperature insulating film 12 to form a thick gate insulating film of the p-channel LDMOS, and then masking the p-channel LDMOS region, the gate extension of the n-channel LDMOS, and a portion of the field oxide layer with a photoresist by a photolithography process; Wet etching the low temperature insulating film to have an inclined swjfdus film structure in a gate extension region of an n-channel LDMOS using the photoresist mask; Subsequently, after removing the photoresist layer and forming a thin oxide film, masking all regions except the n-channel region to control the threshold voltage of the n-channel LDMOS, ion implanting p-type impurities, and then removing the photoresist layer. A method of manufacturing a high voltage power device, characterized in that the power device is fabricated by forming the gate low temperature insulating film of the n-channel LDMOS region inclined. The method of claim 2, And the primary gate oxide film is grown to a thickness of 300 to 1000 kW, and the gate low temperature insulating film is deposited to a thickness of 1000 to 2000 kW. The method of claim 2, wherein the low temperature insulating film, A method of manufacturing a high voltage power device, characterized in that it is either a single thin film or a multilayer insulating film having a different etching ratio from each other.

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