KR0136481B1 - Gate electrode manufacturing method - Google Patents
Gate electrode manufacturing methodInfo
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- KR0136481B1 KR0136481B1 KR1019940029721A KR19940029721A KR0136481B1 KR 0136481 B1 KR0136481 B1 KR 0136481B1 KR 1019940029721 A KR1019940029721 A KR 1019940029721A KR 19940029721 A KR19940029721 A KR 19940029721A KR 0136481 B1 KR0136481 B1 KR 0136481B1
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- film
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- polysilicon film
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- amorphous silicon
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D64/661—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation
- H10D64/662—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures
- H10D64/663—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures the additional layers comprising a silicide layer contacting the layer of silicon, e.g. polycide gates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
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- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
본 발명은 트랜지스터의 게이트전극 제조방법에 관한 것으로, 특히 비정질실리콘의 상변화로 인한 응력변화를 최소화하며 또한 폴리사이드 구조의 게이트전극 제조시 실리사이드로 부터의 게이터 산화막내로의 금속성 불순물 및 불소의 확산을 막는 게이트전극 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a gate electrode of a transistor, and in particular, to minimize the stress change due to the phase change of amorphous silicon and to prevent the diffusion of metallic impurities and fluorine from the silicide into the gator oxide film during the production of the gate electrode of polyside structure. The film relates to a method of manufacturing a gate electrode.
Description
제1A도 내지 제1I도는 본 발명의 일실시예에 따른 게이트전극형공정을 나타내는 공정단면도.1A to 1I are cross-sectional views illustrating a gate electrode process according to an embodiment of the present invention.
제2A도 내지 제2D도는 본 발명의 다른 실시예에 따른 폴리사이드 구조의 게이트전극 형성공정을 나타내는 공정단면도.2A through 2D are cross-sectional views illustrating a process of forming a gate electrode having a polyside structure according to another exemplary embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10:인시류로 도핑된 폴리실리콘막 20:자연산화막10: polysilicon film doped with poems 20: natural oxide film
21:실리사이드21: Silicide
본 발명은 트랜지스터의 게이트전극 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a gate electrode of a transistor.
인시튜로 PH3도핑된 폴리실리콘 게이트는 도핑 공정의 단순화 및 그에 따른 온도유지비용(Thermal Budget)의 감소 그리고 결정립 성장을 통한 결정입자의 크기가 커지면서 비저항감소를 통해 게이트전극의 두께가 감소되는 등의 장점이 있으나 비정질(Amorphous) 상태로 종착되기 때문에 이후 열처리공정 동안에 상변화가 일어나면서 길이방향(tensile)으로 큰 응력변화를 받게되고 이에 따라 전체 활성영역이 크면서 소자격리를 위한 단차(Isolation Topology)를 갖는 게이트 산화막의 절연파괴(Breakdown) 특성을 악화시켜 수율을 감소시키게 된다.In-situ PH 3 doped polysilicon gates reduce the thickness of the gate electrode by reducing the resistivity as the doping process is simplified, the thermal budget is reduced, and the grain size is increased through grain growth. However, since it is terminated in an amorphous state, phase change occurs during the subsequent heat treatment process, so that a large stress change is received in the longitudinal direction, and accordingly, the overall active area is large and the isolation topology for device isolation is achieved. Deterioration of the breakdown characteristics of the gate oxide film having the () decreases the yield.
한편, 고집적 반도체 소자 제조시 소자의 고속화를 목적으로 게이트는 저항이 낮은 폴리사이드(polycide) 구조가 주로 이용되는데 폴피실리콘막 위에 실리사이드가 증착되는 과정 및 열처리 과정 동안에 반응하지 못한 금속성 불순물(metallic impurity) 및 반응부산물이 폴리실리콘막을 통해 게이트산화막으로 확산 침투함으로써 게이트산화막의 절연파괴 특성을 악화시켜 수율 및 신뢰성이 저하된다. 특히 텅스텐 폴리사이드의 경우는 불소(Fluorine) 확산으로 인한 게이트산화막의 비이상적 두께증가 현상을 초래하게 된다.On the other hand, in the fabrication of high-density semiconductor devices, the gate has a low-resistance polycide structure mainly used for the purpose of speeding up the device. The metallic impurity that failed to react during the deposition of silicide on the polysilicon film and the heat treatment process And diffusion and penetration of the reaction by-products into the gate oxide film through the polysilicon film deteriorate the dielectric breakdown characteristics of the gate oxide film, thereby lowering the yield and reliability. In particular, in the case of tungsten polysides, non-ideal thickness increase of the gate oxide layer due to fluorine diffusion occurs.
따라서, 상기와 같은 문제점을 해결하기 위하여 안출된 본 발명은 비정질실리콘의 상변화로 인한 응력변화를 최소화하는 게이트전극 제조방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for manufacturing a gate electrode which minimizes the stress change caused by the phase change of amorphous silicon.
본 발명의 다른 목적은 폴리사이드 구조의 게이트전극 제조시 실리사이드로부터의 게이터 산화막 내로의 금속성 불순물 및 불소의 확산을 막는 게이트전극 제조방법을 제공하는데 있다.Another object of the present invention is to provide a method of manufacturing a gate electrode which prevents diffusion of metallic impurities and fluorine from a silicide into a gator oxide film in manufacturing a gate electrode having a polyside structure.
상기 목적을 달성하기 위하여 본 발명은 인시류(In-situ)로 불순물 도핑된 폴리실리콘막을 게이트전극으로 이용할 경우 상변화로 인한 큰 응력변화를 줄이기 위한 게이트전극 제조방법에 있어서, 예정된 게이트전극 형성부위에 비도핑 폴리실리콘막을 증착하는 단계;인시류로 불순물 도핑된 비정질실리콘막을 증착하는 단계 및 열처리 단계를 포함하여 이루어지는 것을 특징으로 한다.In order to achieve the above object, the present invention provides a gate electrode forming part in a method of manufacturing a gate electrode for reducing a large stress change due to a phase change when a polysilicon film doped with in-situ is used as a gate electrode. Depositing an undoped polysilicon film; depositing an amorphous silicon film doped with impurity with an impurity and a heat treatment step.
또한, 본 발명은 폴리사이드 구조의 게이트전극 제조시 실리사이드로부터의 게이터 산화막 내로의 불순물 확산을 억제하는 게이트전극 제조방법에 있어서, 실리사이드의 하층구조인 도핑된 폴리실리콘막의 표면에 화학적으로 유기된 자연산화막을 생성시켜 실리사이드의 하부층을 폴리실리콘막과 자연산화막의 이중구조로 형성하는 것을 특징으로 한다.In addition, the present invention is a method of manufacturing a gate electrode to suppress the diffusion of impurities into the gator oxide film from the silicide during the production of the gate electrode of the polycide structure, a natural oxide film chemically organically organically formed on the surface of the doped polysilicon layer of the silicide It is characterized in that the lower layer of the silicide is formed in a double structure of the polysilicon film and the natural oxide film.
이하, 첨부된 도면을 참조하여 본 발명을 상술한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
본 발명은 폴리실리콘막은 상변화가 일어나지 않기 때문에 열처리시에 나타나는 응력변화가 작다는 점에 착안하여 서로 다른 증착 시스템을 사용하여 게이트산화막 위에 비도핑 폴리실리콘막을 증착하고 HF 크리닝을 통해 상기 비도핑 폴리실리콘막 상부에 생성되는 자연산화막을 최대한도로 억제시킨 후 다른 저압화학기상증착 시스템(LPCVDSystem)에서 고농도의 인시류로 PH3도핑된 폴리실리콘막을 증착한 다음 충분히 열처리함으로써 비정질실리콘이 결정을 이루도록 하며, 동시에 불순물을 비도핑 폴리실리콘층까지 확산시킴으로써 불순물 분포를 균일하게 만든다. 이를 통해 비정질실리콘의 상변화로 인한 응력변화를 하층의 폴리실리콘층을 통해 줄여 줄 수 있을 뿐만 아니라, 한 시스템 내에서 인시류로 도핑된 폴리실리콘막과 도핑된 비정질실리콘막을 연속적으로 형성할 때 증착온도가 변함으로 인해 발생될 수 있는 시스템 불안정을 최소화 한다.In view of the fact that the polysilicon film does not have a phase change, the stress change during heat treatment is small, and thus, the undoped polysilicon film is deposited on the gate oxide film using a different deposition system, and the undoped polycrystalline film is subjected to HF cleaning. After suppressing the natural oxide film formed on the silicon film to the maximum, after depositing a PH 3 doped polysilicon film with a high concentration of phosphorus in another low pressure chemical vapor deposition system (LPCVD System), the amorphous silicon is crystallized by sufficient heat treatment. At the same time, the impurity distribution is made uniform by diffusing the impurities to the undoped polysilicon layer. This not only reduces the stress change due to the phase change of amorphous silicon through the lower polysilicon layer, but also deposits when successively forming doped polysilicon film and doped amorphous silicon film in a system. Minimize system instability that can be caused by temperature changes.
제1A도 내지 제1I도는 인시튜로 PH3도핑된 폴리실리콘막을 게이트전극으로 적용하기 위한 주변공정을 포함한 공정단면도로, 먼저, 제1A도는 고집적화된 디바이스에서 개별 소자를 전기적 및 구조적으로 격리시키는 필드산화막을 형성하기 위해서 반도체기판(1)에 패드산화막(2) 150Å을 열산화법으로 성장시키고, 폴리실리콘막(3) 500A과 Si3N4(4) 2000Å을 증착한 후 감광막패턴(5)을 형성한 상태의 단면도이다.1A to 1I are process cross-sectional views including a peripheral process for applying a PH 3 doped polysilicon film as a gate electrode in situ. First, FIG. 1A is a field for electrically and structurally isolating individual elements in a highly integrated device. In order to form an oxide film, 150 패드 of the pad oxide film 2 was grown on the semiconductor substrate 1 by thermal oxidation, and 500, of polysilicon film 3 and 2000 Si of Si 3 N 4 (4) were deposited. It is sectional drawing of the state formed.
제1B도는 필드산화막이 형성될 영역의 질화막이 노출된 부위를 폴리실리콘막이 소정정도 잔류하도록 상기 질화막(4), 폴리실리콘막(3)을 식각한 상태의 단면도이다.FIG. 1B is a cross-sectional view of the nitride film 4 and the polysilicon film 3 being etched such that the polysilicon film remains to a predetermined extent in the portion where the nitride film is exposed in the region where the field oxide film is to be formed.
제1C도는 상기 감광막(5)을 제거한 후 열산화 공정에 의해 필드산화막(6)을 형성시킨 상태의 단면도이다.FIG. 1C is a cross-sectional view of a state in which the field oxide film 6 is formed by a thermal oxidation process after removing the photosensitive film 5.
제1D도는 필드산화막이 형성되지 않은 활성영역의 상기 질화막(4) 및 폴리실리콘막(3)을 제거한 상태의 단면도이다.FIG. 1D is a cross-sectional view of the nitride film 4 and the polysilicon film 3 in the active region where no field oxide film is formed.
제1E도는 상기 필드산화막 형성을 위한 열공정 중에 활성영역과 인접된 필드산화막의 가장자리에서 생성될 수 있는 화이트리본(WhiteRibon) 등을 제거하기 위해 희생산화막(7)을 형성한 상태의 단면도이다.FIG. 1E is a cross-sectional view of the sacrificial oxide film 7 being formed to remove white ribbon and the like that may be generated at the edge of the field oxide film adjacent to the active region during the thermal process for forming the field oxide film.
제1F도는 상기 희생산화막(7)을 HF로 제거한 후 게이트산화막(8)을 형성한 상대의 단면도이다.1F is a cross-sectional view of a counterpart in which the gate oxide film 8 is formed after removing the sacrificial oxide film 7 with HF.
제1G도는 상기 게이트산화막(8) 위에 비도핑 폴리실리콘막(9)(Si2N6및 SiH4)을 620℃에서 증착한 후 PH3flow Rate를 350sccm으로 크게하고,510℃ 증착온도에서 인시류로 PH3 도핑된 비정질실리콘막(10)을 증착한 후 850℃,lhr동안 N2분위기 하에서 열처리함으로써 도핑된 비정질실리콘막을 결정화하면서 동시에 주입된 불순물을 비도핑 폴리실리콘층까지 확산시켜 폴리실리콘막 내에서 불순물 분포를 균일하게 한다. 이때 폴리실리콘막과 도핑된 비정질실리콘막의 두께비는 0.2내지 0.3으로 한다. 이로써 인시류로 PH3도핑된 비정질실리콘막의 상변화에 따른 응력별로 인한 게이트산화막에 주는 손실(Damage)을 줄일 수 있을뿐만 아니라 결정화된 폴리실리콘막과 비정질실리콘막을 증착하는 시스템이 달라 인시류로 한 장비에서 도핑된 폴리실리콘막과 인시튜로 PH3 도핑된 비정질실리콘막을 연속적으로 증착할 때 온도변화에 따른 시스템의 불안정을 제거할 수 있다.FIG. 1G shows that the undoped polysilicon layer 9 (Si 2 N 6 and SiH 4 ) is deposited on the gate oxide layer 8 at 620 ° C., and the PH 3 flow rate is increased to 350 sccm, and is observed at 510 ° C. deposition temperature. By depositing PH3 doped amorphous silicon film 10 and heat treatment under N 2 atmosphere at 850 ° C. for 1 hr to crystallize the doped amorphous silicon film and simultaneously diffuse the impurity implanted into the undoped polysilicon layer in the polysilicon film. The impurity distribution is made uniform at. At this time, the thickness ratio of the polysilicon film and the doped amorphous silicon film is 0.2 to 0.3. This not only reduces the damage to the gate oxide film due to stress caused by phase change of the amorphous silicon film doped with PH 3, but also varies the system for depositing the crystallized polysilicon film and the amorphous silicon film. When the doped polysilicon film and the in-situ PH3 doped amorphous silicon film are continuously deposited in the equipment, it is possible to eliminate the instability of the system due to the temperature change.
제1H도는 게이트전극 형성용 마스크로 감광막(5')을 패턴형성한 상태의 단면도이다.1H is a sectional view of the photosensitive film 5 'patterned with a gate electrode forming mask.
제1I도는 상기 감광막을 마스크로 상기 인시류로 도핑된 폴리실리콘막(10), 비도핑 폴리실리콘막(9), 게이트산화막(8)을 차례로 선택식각함으로써 게이트전극을 형성한 상태의 단면도이다.FIG. 1I is a cross-sectional view of a state in which a gate electrode is formed by selectively etching the polysilicon film 10, the undoped polysilicon film 9, and the gate oxide film 8 which are doped with the phosphorus using the photosensitive film as a mask.
다음으로, 제2A도 내지 제2I도는 본 발명의 다른 실시예로서, 폴리사이드 게이트에서 실리사이드로부터 금속성 불순물 및 불소가폴리실리콘의 결정입자 경계(grain boundary)를 통해 확산해 들어간다는 사실에 착안하여 폴리실리콘막을 두구조로 나누어 하층부위는 PoCl3도핑된 폴리실리콘으로 하고 상층부위는 인시튜로 PH3도핑된 비정질실리콘막을 증착한 후 열처리 함으로써 결정화시키는 과정을 나타내는 공정단면도이다.Next, FIGS. 2A to 2I illustrate another embodiment of the present invention, in which the metallic impurities and fluorine diffuse from the silicide through the grain boundary of the polysilicon in the polyside gate. Dividing the silicon film into two structures, the lower layer is made of PoCl 3 doped polysilicon, and the upper layer is a process cross-sectional view showing a process of crystallizing by depositing and thermally treating the PH 3 doped amorphous silicon film in situ.
먼저, 제2A도는 상기 일실시의 제1F도까지의 공정과 동일하게 진행하여 게이트산화막(8)까지를 형성한 상태의 단면도이다.First, FIG. 2A is a sectional view of a state in which up to the gate oxide film 8 is formed in the same manner as the process up to FIG. 1F of the above embodiment.
제2B도는 상기 게이트산화막(8) 위에 SiH4또는 Si3N4가스를 사용해서 620℃에서 폴리실리콘막(9)을 증착한 후 최종적으로 NH4oH로 크리닝함으로써 화학적으로 유기된 자연산화막(chemical inducednative oxide,20)을 형성한 후 실리사이드(21)을 형성한다. 여기에서 폴리실리콘막(9)에 대한 실리사이드(21)의 두께비는 0.5내지 1.5로 한다. 이때 실리사이드 증착공정 및 이후의 열처리 공정 동안에 실리사이드로부터의 금속성 불순물 및 불소가 폴리실리콘막 표면 위의 산화막에 의해 게이트산화막 내로 확산해 들어가는 것을 억제시킨다.FIG. 2B shows a chemically organically grown natural oxide film by depositing a polysilicon film 9 at 620 ° C. using SiH 4 or Si 3 N 4 gas on the gate oxide film 8 and finally cleaning with NH 4 oH. After forming the inducednative oxide 20, the silicide 21 is formed. Here, the thickness ratio of the silicide 21 to the polysilicon film 9 is set to 0.5 to 1.5. At this time, metallic impurities and fluorine from the silicide are prevented from diffusing into the gate oxide film by the oxide film on the surface of the polysilicon film during the silicide deposition process and the subsequent heat treatment process.
제2C도는 상기 실리사이드(21) 상부에 감광막패턴(5')을 형성한 상태의 단면도이다.FIG. 2C is a cross-sectional view of the photosensitive film pattern 5 'formed on the silicide 21. Referring to FIG.
제2D도는 감광막패턴(5' )을 차단막으로 상기 실리사이드(21), 자연산화막(20), 폴리실리콘막(9), 게이트산화막(8)을 차례로 식각하여 게이트전극을 형성한 상태의 단면도이다.FIG. 2D is a cross-sectional view of a gate electrode formed by sequentially etching the silicide 21, the natural oxide film 20, the polysilicon film 9, and the gate oxide film 8 by blocking the photoresist pattern 5 ′.
상기와 같이 이루어지는 본 발명은 고집적화된 MOSFET 디바이스에서 인시튜로 PH3도핑된 폴리실리콘 게이트 적용시 상변화로 인한 길이방향의 응력변화를 줄여 게이트산화막의 절연파괴 특성을 개선시켜 수율을 향상시킬 뿐만 아니라, 폴리실리콘 증착 시스템과 인시튜로 PH3도핑된 비정질실리콘 증착 시스템을 별도로 함으로써 시스템을 안정화(systems-tabilization) 시킬 수 있다.The present invention made as described above improves the yield by improving the dielectric breakdown characteristics of the gate oxide by reducing the stress change in the longitudinal direction due to the phase change in the application of PH 3 doped polysilicon gate in situ in a highly integrated MOSFET device The system can be stabilized by separating the polysilicon deposition system and the PH 3 doped amorphous silicon deposition system in situ.
또한, 폴리사이드 구조의 게이트전극 적용시 실리사이드로부터 금속성 불순물 및 불소가 게이트산화막 내로 확산되는 것을 억제하며, 특히 텅스텐 폴리사이드 게이트 적용시 게이트산화막의 비이상적인 두께증가 현상을 억제하는 효과를 얻을 수 있다.In addition, when the gate electrode of the polycide structure is applied, it is possible to suppress the diffusion of metallic impurities and fluorine from the silicide into the gate oxide layer, and in particular, when the tungsten polyside gate is applied, an effect of suppressing an abnormal increase in thickness of the gate oxide layer can be obtained.
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