KR0118637Y1 - Integrated injection logic device - Google Patents
Integrated injection logic deviceInfo
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- KR0118637Y1 KR0118637Y1 KR2019940026229U KR19940026229U KR0118637Y1 KR 0118637 Y1 KR0118637 Y1 KR 0118637Y1 KR 2019940026229 U KR2019940026229 U KR 2019940026229U KR 19940026229 U KR19940026229 U KR 19940026229U KR 0118637 Y1 KR0118637 Y1 KR 0118637Y1
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- impurity diffusion
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
- H10D84/65—Integrated injection logic
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
- H03K19/091—Integrated injection logic or merged transistor logic
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- Mathematical Physics (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
본 고안은 집적주입 논리회로소자에 관한 것으로, 반도체기판의 소정영역에 p형 불순물을 확산시켜 형성된 피웰과, 상기 피웰의 소정영역에 p+형 불순물을 주입, 확산시켜 형성된 p+ 불순물 확산영역과, 적어도 한면 이상이 상기 p+ 불순물 확산영역과 겹쳐지지 않도록 상기 피웰 내에 n+형 불순물을 주입, 확산시켜 형성된 다수의 n+ 불순물 확산영역을 포함하여 구성되며, 상기와 같이 n+ 불순물 확산영역과 p+ 불순물 확산영역이 적어도 일면이상 서로 겹치지 않게 하여, 공정의 변경이나 추가없이 출력 엔피엔 트랜지스터측 콜렉터 면적을 넓힘으로써 베이스 영역의 재결합을 감소시키고 이에따라 전류이득을 증가시킴으로써 안정된 로직을 구현할 수 있는 효과가 있다.The present invention relates to an integrated injection logic circuit device, comprising: a pwell formed by diffusing a p-type impurity into a predetermined region of a semiconductor substrate, a p + impurity diffusion region formed by implanting and diffusing a p + type impurity into a predetermined region of the pewell, and And a plurality of n + impurity diffusion regions formed by injecting and diffusing n + type impurities into the pewell so that at least one surface thereof does not overlap with the p + impurity diffusion regions. By not overlapping one or more sides, the area of the output NPE transistor-side collector can be increased without changing or adding a process, thereby reducing the recombination of the base region and thus increasing the current gain, thereby achieving stable logic.
Description
제1도는 종래의 기술에 의한 집적주입 논리회로소자의 내부 회로도.1 is an internal circuit diagram of an integrated injection logic circuit device according to the prior art.
제2도는 종래의 기술에 의한 집적주입 논리회로소자의 레이아웃도.2 is a layout diagram of an integrated injection logic circuit device according to the related art.
제3도는 제2도의 XX'선을 기준으로 자른 집적주입 논리회로소자의 단면도.3 is a cross-sectional view of an integrated injection logic circuit taken along the line XX 'of FIG.
제4도는 제2도의 YY'선을 기준으로 자른 집적주입 논리회로소자의 단면도.4 is a cross-sectional view of an integrated injection logic circuit taken along the line YY ′ of FIG. 2.
제5도는 본 고안에 의한 집적주입 논리회로소자의 제1실시예의 레이아웃도.5 is a layout diagram of a first embodiment of an integrated injection logic circuit device according to the present invention;
제6도는 본 고안에 의한 집적주입 논리회로소자의 제2실시예의 레이아웃도.6 is a layout diagram of a second embodiment of an integrated injection logic circuit device according to the present invention;
제7도는 본고안에 의한 집적주입 논리회로소자의 제3실시예의 레이아웃도.7 is a layout diagram of a third embodiment of an integrated injection logic circuit device according to the present invention.
제8도는 제5도의 XX'선을 기준으로 자른 집적주입 논리회로소자의 단면도.FIG. 8 is a cross-sectional view of an integrated injection logic circuit taken along the line XX ′ of FIG. 5.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1:제1 n+ 불순물 확산영역2:제1 p+ 불순물 확산영역1: first n + impurity diffusion region 2: first p + impurity diffusion region
3:제2 p+ 불순물 확산영역4:제2 n+ 불순물 확산영역3: second p + impurity diffusion region 4: second n + impurity diffusion region
5, 6:제1 및 제2 접촉부7:불순물 겹침영역5, 6: first and second contacts 7: impurity overlap region
8:피웰9:에피텍셜층8: PEWELL 9: epitaxial layer
10:매몰층11:기판10: buried layer 11: substrate
본 고안은 집적주입 논리회로소자(IIL:Integrated Injection Logic device)에 관한 것으로, 특히 각 출력 콜렉터(collector)의 유효면적을 증가시켜 전류이득을 높이기 위한 집적주입 논리회로소자에 관한 것이다.The present invention relates to an integrated injection logic device (IIL), and more particularly, to an integrated injection logic device for increasing current gain by increasing the effective area of each output collector.
집적주입논리회로소자는 피인피(PNP) 트랜지스터와 엔피엔(NPN) 트랜지스터가 하나의 단위셀을 구성하며, 에피택셜층(epitaxial layer)을 상기 엔피엔 트랜지스터의 에미터로 하고, 여러개의 콜렉터가 동시에 출력하여 로직을 구성하도록 되어 있는 바이폴라형 논리회로소자로서, 제1도의 (a)도에 도시한 바와 같이 3개의 단위셀로 간단하게 구성할수도 있으며, 상기한 바와 같이 (b)도의 하나의 셀은 입력(X)에 대해 각 멀티 콜렉터들이 X의 출력을 내게 되어 여러 로직을 구성할 수 있도록 되어 있다.In the integrated injection logic circuit, a PNP transistor and an NPN transistor constitute one unit cell, and an epitaxial layer is used as an emitter of the EPI transistor. A bipolar logic circuit device configured to output and configure logic at the same time, which may be simply configured as three unit cells as shown in FIG. 1A, and as shown in FIG. The cell is configured for multiple inputs, with each multi-collector giving the output of X so that it can configure multiple logic.
그리고 상기 (b)도의 저항(R)을 제외하면, 제2도에 도시한 바와 같이 엔피엔 트랜지스터의 n형 에피텍셜층(9) 내에 제1전도형으로서 예를들면 n+ 이온을 확산시킨 제1 n+ 불순물 확산영역(1)과, p+ 이온을 확산시킨 제2 p+ 불순물 확산영역(3)과, 상기 제2 p+ 불순물 확산영역(3)상에 엔피엔 트랜지스터의 콜렉터로 사용하기 위해 일정 간격으로 n+ 이온을 확산시킨 제2 n+ 불순물 확산영역(4)과, 상기 제2 p+ 및 n+ 불순물 확산 영역이 겹쳐진 불순물 겹침영역(7)과, 상기 제2 n+ 불순물 확산영역(4)상에 형성된 엔피엔 트랜지스터의 콜렉터 접촉용 제1 접촉용(5)와, 하측에 위치하는 상기 엔피엔 트랜지스터의 베이스 접촉 및 피엔피 트랜지스터의 콜렉터가 공통으로 접촉하기 위한 제2접촉부(6)로 레이아웃할 수 있다.Except for the resistance R shown in FIG. 2B, the first conductive type, for example, n + ions diffused into the n-type epitaxial layer 9 of the ENP transistor as shown in FIG. n + impurity diffusion region 1, a second p + impurity diffusion region 3 in which p + ions are diffused, and n + at regular intervals for use as a collector of an ENP transistor on the second p + impurity diffusion region 3 An n-P transistor formed on the second n + impurity diffusion region 4 in which ions are diffused, the impurity overlap region 7 in which the second p + and n + impurity diffusion regions overlap, and the second n + impurity diffusion region 4. The first contact 5 for collector contact and the second contact part 6 for common contact between the base contact of the NPP transistor located below and the collector of the PNP transistor can be in common contact.
또한 제2도의 상기 XX'선을 기준으로 자르면 집적주입 논리회로소자는 제3도에 도시한 바와 같이, 기존수직구조의 엔피엔 트랜지스터의 반대구조를 가지므로 전류이득이 감소하기 때문에 이를 해결하기 위해 엔피엔 트랜지스터의 베이스영역에서의 재결합을 감소시키도록 상기 제2도에서는 상기 제2 n+ 및 p+ 불순물 확산영역과 레이아웃이 거의 일치하여 도시되지 않은 피웰(8)을 사용하며, 상기 피웰(8)의 중앙에는 제2 n+ 불순물 확산영역(4)이 형성되어 있으며, 그 양측에는 제2 p+ 불순물 확산영역(3)이 형성되어 있다.In addition, when cutting based on the line XX 'of FIG. 2, the integrated injection logic circuit device has a structure opposite to that of the conventional ENF transistors, as shown in FIG. In order to reduce recombination in the base region of the N-Pen transistor, in FIG. 2, the layout of the n < n > The second n + impurity diffusion region 4 is formed in the center, and the second p + impurity diffusion region 3 is formed on both sides thereof.
그리고 상기 제2도의 YY'선을 기준으로 자르면, 제4도에 도시한 바와 같이 Y측으로는 제1 n+ 불순물 확산영역(1)이, Y'측으로는 제1 p+ 불순물 확산영역(2)이 형성되어 있으며, 중앙에는 다수의 콜렉터를 형성하기 위해 피웰(8) 내에 제2 p+ 불순물 확산영역(3)과 제2 n+ 불순물 확산영역(4)이 불순물 겹침영역(7)에서 일정 면적 겹쳐지면서 교대로 형성되어 있다.As shown in FIG. 4, the first n + impurity diffusion region 1 is formed on the Y side, and the first p + impurity diffusion region 2 is formed on the Y 'side, as shown in FIG. In the center, the second p + impurity diffusion region 3 and the second n + impurity diffusion region 4 are alternately overlapped with each other in the impurity overlap region 7 so as to form a plurality of collectors. Formed.
그러나 상기와 같은 종래의 집적주입 논리회로소자는, 한정된 영역안에 여러개의 출력 콜렉터들을 심어야 하므로 콜렉터의 크기가 감소되어 출력단이 불안정하며, 이로인해 엔피엔 트랜지스터의 전류이득이 낮을뿐만 아니라, 상기한 바와 같이 기존 수직구조의 엔피엔 트랜지스터의 반대구조로 인해 전류이득이 적은 것을 극복하기 위한 피웰 사용에 있어서도 상기 제 2 p+ 불순물 영역(3)에서는 에미터영역으로부터 주입되는 소수 캐리어들이 모두 재결합이 이루어져 콜렉터 영역으로 다다를수 없기 때문에 콜렉터의 실제 면적이 제3도에 도시한 바와 같이 a로 제한되며, 이에따라 피웰을 완전히 활용하지 못함으로써 전류이득의 증가가 매우 어려운 문제점이 있다.However, in the conventional integrated injection logic circuit as described above, the output stage is unstable because the size of the collector is reduced because a plurality of output collectors must be planted in a limited region, which results in a low current gain of the NPI transistor. Likewise, in the second p + impurity region 3, the minority carriers injected from the emitter region are all recombined in the collector region, even in the use of a pwell to overcome the low current gain due to the opposite structure of the conventional NPP transistor. Since the actual area of the collector is limited to a as shown in FIG. 3, it is difficult to increase the current gain by not fully utilizing the Pwell.
따라서 본 고안의 목적은 상기와 같은 문제점을 해결하기 위하여 상기 피웰 내의 제2 n+ 불순물 확산영역의 일측에만 제1 p+ 불순물 확산영역이 겹치도록 형성함으로써 콜렉터 영역을 넓게하여 출력단을 안정화하고, 전류이득을 증가시킬 수 있는 집적주입 논리회로소자를 제공하는 것이다.Accordingly, an object of the present invention is to solve the above problems, by forming the first p + impurity diffusion region overlapping only one side of the second n + impurity diffusion region in the pewell, thereby widening the collector region, stabilizing the output stage, and obtaining current gain. It is to provide an integrated injection logic circuit element that can be increased.
상기 목적을 달성하기 위한 본 고안의 집적주입 논리회로소자는, 반도체기판의 소정영역에 p형 불순물을 확산시켜 형성된 피웰과, 상기 피웰의 소정영역에 p+형 불순물을 주입, 확산시켜 형성된 p+ 불순물 확산영역과, 상기 피웰 내의 상기 p+ 불순물 확산영역과 한면 이상이 겹쳐지지 않도록 n+형 불순물을 주입, 확산시켜 형성된 n+ 불순물 확산영역을 포함하여 구성된 것을 특징으로 한다.An integrated injection logic circuit device of the present invention for achieving the above object is a pwell formed by diffusing a p-type impurity in a predetermined region of the semiconductor substrate, and a p + impurity diffusion formed by injecting and diffusing a p + type impurity in the predetermined region of the pewell And an n + impurity diffusion region formed by implanting and diffusing an n + -type impurity so that at least one surface does not overlap with the p + impurity diffusion region in the pewell.
이하 첨부도면을 참조하여 본 고안을 좀 더 상세하게 설명하고자 한다.Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.
본 고안의 집적주입 논리회로소자는, 피웰(8) 내의 각 불순물 확산영역을 제외한 나머지 구조는 종래와 동일하므로, 종래의 설명을 참조하고, 상기 피웰(8) 내의 구조만 설명하면 다음과 같다.In the integrated injection logic device of the present invention, the rest of the structure except for each of the impurity diffusion regions in the pewell 8 is the same as in the prior art. Referring to the conventional description, only the structure in the pewell 8 will be described below.
먼저, 제1실시예의 경우 수평위치에서 살펴보면 제5도에 도시한 바와 같은 깊은 머리빗살 형태로서, 제2 n+ 불순물 확산영역(4)은 일면이 상기 제2 p+ 불순물 확산영역(3)과 겹쳐지며, 상기 제2 p+ 불순물 확산영역(3)과 겹쳐지는 일면과 수직을 이루는 양면은 전면에 걸쳐 상기 제2 p+ 불순물 확산영역(3)과 일정간격을 유지하며, 상기 제2 p+ 불순물 확산영역(3)과 겹쳐지는 일면의 대응면은 상기 피웰(8)과 접하도록 구성도 된다.First, the first embodiment has a deep hair comb shape as shown in FIG. 5 when viewed from a horizontal position. The second n + impurity diffusion region 4 is overlapped with the second p + impurity diffusion region 3. Both surfaces perpendicular to one surface overlapping with the second p + impurity diffusion region 3 maintain a predetermined distance from the second p + impurity diffusion region 3 over the entire surface of the second p + impurity diffusion region 3. The corresponding surface of one surface overlapping with) may be in contact with the pewell (8).
그리고 제2실시예에서는, 제6도에 도시한 바와 같은 얕은 머리빗살 형태로서, 상기 제2 n+ 불순물 확산영역(4)은 일면이 상기 제2 p+ 불순물 확산영역(3)과 겹쳐지며, 또한 상기 제2 p+ 불순물 확산영역(3)과 겹쳐지는 일면과 수직을 이루는 양면은 일부분이 상기 제2 p+ 불순물 확산영역(3)과 겹쳐지고, 상기 제2 p+ 불순물 확산영역(3)과 겹쳐지는 일면의 대응면과 상기 일부분이 제2 p+ 불순물 확산영역(3)과 겹친 양면의 마너지 부분은 상기 피웰(8)과 접하도록 구성된다.In the second embodiment, as shown in FIG. 6, a shallow hair comb form as shown in FIG. 6, wherein the second n + impurity diffused region 4 overlaps the second p + impurity diffused region 3, and Both surfaces perpendicular to one surface overlapping the second p + impurity diffused region 3 partially overlap the second p + impurity diffused region 3 and overlap the second p + impurity diffused region 3. Both side portions of the mating surface and the portion of which overlap the second p + impurity diffusion region 3 are configured to contact the pewell 8.
또한 제3실시예에서는, 제7도에 도시한 바와 같이 상기 제2 n+ 불순물 확산영역(4)은 평면 관측시 일면만 상기 제2 p+ 불순물 확산영역(3)과 겹쳐지며, 나머지 면들은 상기 피웰(8)과 접하도록 구성된다.In addition, in the third embodiment, as shown in FIG. 7, only one surface of the second n + impurity diffusion region 4 overlaps the second p + impurity diffusion region 3 in planar view, and the remaining surfaces of the second well are And (8).
즉, 상기 피웰(8) 내에 상기 제2 p+ 불순물 확산영역(3)과 적어도 한면 이상이 겹쳐지지 않도록 n+형 불순물을 주입, 확산시켜 제2 n+ 불순물 확산영역(4)를 형성함으로써, 제8도에 도시한 바와 같이 엔피엔 트랜지스터의 콜렉터의 유효면적을 b만큼 넓게하여 에미터로부터 출발된 캐리어들을 받아들이는 면적의 확장에 의해 베이스 영역의 재결합을 감소시킬 수 있다.In other words, the second p + impurity diffusion region 3 is implanted and diffused into the pewell 8 such that at least one or more surfaces of the second p + impurity diffusion region 3 are not overlapped to form the second n + impurity diffusion region 4. As shown in FIG. 5, the effective area of the collector of the NPI transistor can be increased by b to reduce the recombination of the base region by the expansion of the area receiving the carriers from the emitter.
이상에서와 같이 본 고안에 의하면 공정의 변경이나 추가없이 출력엔피엔 트렌지스터측이 콜렉터 면적을 넓힘으로써 베이스 영역의 재결합을 감소시키고 이에따라 전류이득을 증가시킴으로써 안정된 로직을 구현할 수 있는효과가 있다.As described above, according to the present invention, there is an effect that a stable logic can be realized by reducing the recombination of the base region and thus increasing the current gain by increasing the collector area of the output NPT transistor side without changing or adding a process.
Claims (5)
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| KR2019940026229U KR0118637Y1 (en) | 1994-10-07 | 1994-10-07 | Integrated injection logic device |
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| KR2019940026229U KR0118637Y1 (en) | 1994-10-07 | 1994-10-07 | Integrated injection logic device |
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| KR0118637Y1 true KR0118637Y1 (en) | 1998-07-01 |
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