KR0183685B1 - Digital magnetic record reproducing apparatus - Google Patents

Abstract

The present invention relates to a digital magnetic recording and reproducing method and apparatus, wherein a glitch component removing unit, a data edge detection unit and a data reproducing unit are provided in the output terminal of the data detector in a dependent manner to remove the glitch component that causes an error in the first half of the reproducing system, By transmitting only data, it is possible to prevent malfunctions of devices installed at the rear end such as the reproduction clock recovery unit and the demodulation unit, and to improve the BER of the entire reproduction system.

Description

Digital magnetic recording and playback device

1 is a block diagram showing a reproduction system of a conventional digital magnetic recording and reproducing apparatus.

2 is a block diagram showing a reproduction system of the digital magnetic recording and reproducing apparatus according to the present invention.

FIG. 3 is a detailed circuit diagram showing digital data correction means in FIG.

4 is an operation timing diagram of each part in FIG.

FIG. 5 is a detailed circuit diagram showing the first embodiment of the data reproducing section in FIG.

6 is an operation timing diagram of each part in FIG.

FIG. 7 is a detailed circuit diagram showing a second embodiment of the data reproducing section in FIG.

8 is an operation timing diagram of each part in FIG.

* Explanation of symbols for main parts of the drawings

10: reproduction amplifier 20: reproduction equalizer

30: data detector 40: glitch component removal unit

41: data rising edge calculator 46: data falling edge calculator

60: data edge detector 61: data rising edge detector

65: data falling edge detector 70: data reproduction unit

100: digital data correction means

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital magnetic recording and reproducing apparatus, and in particular, eliminates error pulses other than signal components that may occur when reproducing recorded digital data, thereby preventing malfunctions of the subsequent apparatuses to which the detected digital data is applied. The present invention relates to a digital magnetic recording and reproducing apparatus for reducing a bit error rate (BER).

The apparatus for recording and reproducing digital data converts the received analog signal into digital data, and then records it on a magnetic recording medium, i.e., magnetic tape, reproduces the recorded digital data with digital data at the time of recording, and then recreates the original analog signal. Convert to

A block diagram showing a reproduction system of a conventional digital magnetic recording / reproducing apparatus is shown in FIG.

In FIG. 1, the digital data recorded on the magnetic recording medium is read out by the reproducing head and applied to the reproducing amplifier section 10. The reproducing amplifier section 10 reproduces this signal closer to the analog signal due to the characteristics of the magnetic recording medium. The signal is amplified at a predetermined amplification rate and applied to the reproduction equalizer 20. The reproduction signal processed by the reproduction equalizer 20 in a state where the digital data can be easily detected is restored by the data detector 30 to the digital data at the time of recording, and the reproduction clock recovery unit 80 uses the digital data from the digital data. The reproduction clock is recovered and applied to the demodulation unit 90 together with the digital data output from the data detector 30 to demodulate the original digital data. The demodulated digital data is subjected to error correction decoding by the error correction (ECC) decoder 95 and then applied to a subsequent compression signal expander (not shown) and a digital / analog converter (not shown).

However, in the reproducing system of the conventional digital magnetic recording and reproducing apparatus, since the magnetic recording medium itself has a characteristic closer to the analog signal, when the digital data recorded on the magnetic tape is reproduced, unwanted signal components are reproduced together. There was a case. The unwanted signal component, ie error pulse Glitch, has a sharp digital data form that is much shorter than the minimum run length of the detected digital data. Accordingly, in the data detector, waveforms of unexpected error components, that is, glitches, may be mixed and detected according to a detection method.

When the data including the glitch is transmitted to the next stage as it is, there is a burden to improve the error correction capability of the error correction decoder 95, and in particular, the reproduction clock recovery unit 80 for recovering the clock of the reproduction system, that is, the PLL ( When glitch mixed data is applied to an input signal source of a phase locked loop, this glitch component causes a problem that the reproduction clock becomes unstable.

In addition, due to the unstable reproduction clock, the correction capability of the E. C. C decoder 95 is confronted, resulting in an increase in the overall bit error rate (BER) and a decrease in reproduction quality.

Accordingly, an object of the present invention is to solve the above-mentioned problem, when an error pulse other than the original signal component is detected during the reproduction of the recorded digital data, the digital magnetic recording and reproduction for reproducing only the original signal component by removing the error pulse. To provide a device.

In order to achieve the above object, the present invention provides a reproduction amplifier for amplifying digital data read out from a recording medium through a reproduction head, and a reproduction equalizer for compensating for degradation such as frequency characteristics of a signal output from the reproduction amplifier. And a data detector for detecting digital data at the time of recording from the output signal of the reproduction equalizer, a demodulator for demodulating the digital data detected by the data detector, and error correction decoding on the output signal of the demodulator. An error correction decoder, a compression signal expander for extending the output signal of the error correction decoder into a signal before compression, a digital / analog converter for converting the output signal of the compressed signal extender into an analog signal, and the data detector Connected between the demodulator and the demodulator, A digital magnetic recording and reproducing apparatus comprising digital data correction means for removing error components such as glitches mixed into digital data detected by the device, and applying only pure digital data to the demodulator, wherein the digital data correction means comprises: the data; A glitch component removing unit for removing a glitch component included in the digital signal output from the detector; A data edge detector for detecting only an edge portion of original digital data in a signal output from the glitch component remover; And a data reproducing unit for recovering original digital data from the signal output from the data edge detector and applying it to the demodulation unit.

Next, the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram showing a reproduction system of the digital magnetic recording and reproducing apparatus according to the present invention.

The block diagram shown in FIG. 2 is designed to compensate for deterioration of the frequency characteristics of the output signal of the reproduction amplifier 10 and the reproduction amplifier 10 for amplifying the digital data read out through the reproduction head. A reproduction equalizer 20, a data detector 30 for detecting digital data at the time of recording from an output signal of the reproduction equalizer 20, and digital data detected by the data detector 30 by correcting the first data. Digital data correction means 100 for application to demodulation section 90 in FIG.

The digital data correction means 100 includes a glitch component removing unit 40 for removing the glitch component included in the output signal of the data detector 30, and the original digital data from the output signal of the glitch component removing unit 40. A data edge detector 60 for detecting only the edge portion, and a data reproducing section 70 for restoring original digital data from the output signal of the data edge detector 60 and applying it to the demodulator 90 in FIG. It is composed.

3 is a detailed circuit diagram showing the digital data correction means 100 in FIG.

The configuration of the detailed circuit diagram shown in FIG. 3 is largely composed of the glitch component removing unit 40, the data edge detection unit 60, and the data reproducing unit 70.

The glitch component removing unit 40 includes a data rising edge calculator 41 for calculating only a signal including the rising edge component of the digital data detected by the data detector 30, and the data rising edge detector 41. And a data falling edge calculator 46 for calculating only a signal including falling edge components of the digital data.

The data rising edge calculator 41 includes a primary delayer 45 for first-delaying a half of a minimum information interval among detected digital data, and a pulse for removing a glitch component from the detected digital data. An AND gate for performing logical multiplication on the digital data delayed first through the first run length selector 42 and the first delay length 45 and the signal from which the glitch component is removed through the first run length selector 42. It consists of 41a.

The first run length selector 42 compares the first integrator 43 for integrating the detected digital data and the digital data integrated through the first integrator 43 with a predetermined level, so that only a signal interval of a predetermined level or more is provided. And a level comparator 44 for selecting and transmitting the square wave.

The data falling edge calculator 46 has a second run length selector 47 for removing the pulse of the glitch component from the digital data delayed by the primary delayer 45 of the data rising edge calculator 41. Digital delayed first by the primary delayer 45 of the data rising edge calculator 41 and the secondary delayer 48 installed at the beginning of the second run length selector 47. Performing an AND on the first AND gate 46a for performing an AND on the data, an output signal of the first AND gate 46a, and a signal from which the glitch component has been removed by the second run length selector 47. It consists of a second and gate 46b for.

The second run length selector 47 includes a second delay unit 48 for delaying the first delayed digital data by 1 / n of the first delay period and a second integrator for integrating the second delayed digital data. 49) and a level comparator 50 for comparing the digital data integrated through the second integrator 49 with a predetermined level and selecting only a signal section of a predetermined level or more and transmitting the square wave.

The data edge detector 60 includes a data rising edge detector 61 for detecting only a rising edge of data in the signal output from the data rising edge calculator 41 of the glitch component removing unit 40, and a glitch component removing unit ( And a data falling edge detector 65 for detecting only the falling edge of the data in the signal output from the data falling edge calculator 46 of 40).

The data rising edge detector 61 includes a first multiplier 64 for generating a pulse at each inversion point of the signal output from the data rising edge calculator 41 and a signal output from the data rising edge calculator 41. And an AND gate 61a for performing an AND operation on the signal output from the first multiplier 64 and outputting the result to the data reproducing unit 70.

The first multiplier 64 includes a tertiary delay 62 for delaying a signal output from the data rising edge calculator 41 for a predetermined period, and a third delay and a signal output from the data rising edge calculator 41. And an exclusive OR gate 63 for extracting and outputting only the pulse generated at the rising edge point of the digital data reproduced by performing an exclusive OR on the signal output from the controller 62.

The data falling edge detector 65 generates a pulse at each inversion point of the inverter 66 for phase inverting the signal output from the data falling edge calculator 46 and the signal output from the inverter 66. AND gate 65a for performing a logical multiplication on the second multiplier 69, the signal output from the inverter 66, and the signal output from the second multiplier 69 and outputting the result to the data reproducing unit 70. It consists of.

The second multiplier 69 outputs the fourth order delayer 67 for delaying the signal output from the inverter 66 for a predetermined period, the signal output from the inverter 66, and the fourth order delayer 67. An exclusive OR gate 68 is provided for extracting and outputting only a pulse generated at a falling edge of digital data reproduced by performing an exclusive OR on the signal.

4 is an operation timing diagram of each part in the circuit diagram shown in FIG. 3, (a) is an output signal of the data detector 30, (b) is an output signal of the first integrator 43, and (c) is The output signal of the level comparator 44, (d) is the output signal of the primary delay unit 45, (e) is the output signal of the AND gate 41a, (f) is the output of the secondary delay unit 48 Signal, (g) is the output signal of the second integrator 49, (h) is the output signal of the level comparator 50, (i) is the output signal of the first and gate 46a, (j) is the second The output signal of the AND gate 46b, (k) is the output signal of the tertiary delay circuit 62, (l) is the output signal of the exclusive OR gate 63, (m) is the output signal of the AND gate 61a , (n) is the output signal of the inverter 66, (o) is the output signal of the quaternary delay 67, (p) is the output signal of the exclusive OR gate 68, (q) is the AND gate ( The output signal of 65a) and (r) represent the output signal of the data reproducing section 70, respectively.

FIG. 5 is a detailed circuit diagram showing the first embodiment of the data reproducing section 70 in FIG.

The configuration of the detailed circuit diagram shown in FIG. 5 includes the inverter 71 for inverting the phase of the signal output from the data rising edge detector 61 and the phase of the signal output from the data falling edge detector 65. An inverter 72 for inverting and an output signal of the inverter 71 are applied to a preset (PR) terminal, and an output signal of the inverter 72 is applied to a clear (CLR) terminal, (D) The input terminal and the clock CK terminal are formed of a D flip-flop 73 connected to ground.

6 is an operation timing diagram of each part in the circuit diagram shown in FIG. 5, (a) is an output signal of the inverter 71, (b) is an output signal of the inverter 72, and (c) is D. FIG. The output signal of the flip-flop 73 is shown, respectively.

FIG. 7 is a detailed circuit diagram showing a second embodiment of the data reproducing section 70 in FIG.

The configuration of the circuit diagram shown in FIG. 7 includes a NOR gate 74 for performing NOR logic on the signal output from the data rising edge detector 61 and the signal output from the data falling edge detector 61, and ( J) A signal output from the data rising edge detector 61 is applied to the input terminal, a signal output from the data falling edge detector 65 is applied to the (K) input terminal, and a NOR gate is applied to the inverted clock (CK) terminal. It consists of a JK flip-flop 75 to which an output signal of 74 is applied.

8 is an operation timing diagram of each part in the circuit diagram shown in FIG. 7, (a) is an output signal of the data rising edge detector 61, (b) is an output signal of the data falling edge detector 65, ( c) denotes an output signal of the NOR gate 74, and (d) denotes an output signal of the JK flip-flop 75, respectively.

The overall operation of the present invention will now be described with reference to FIG.

In FIG. 2, the digital data signal recorded on the magnetic recording medium is read by the reproduction head and applied to the reproduction amplifier 10, and the reproduction amplifier 10 converts the read reproduction digital signal to a predetermined amplification ratio. After amplification is applied to the reproduction equalizer 20.

The reproduction equalizer 20 compensates for the distorted portion of the digital signal, converts it into a form that can be easily detected as digital data, and applies it to the data detector 30, and the data detector 30 supplies the reproduction equalizer 20. The digital data at the time of recording is recovered from the output signal of the digital signal and applied to the digital data correcting means 100. The digital data correcting means 100 corrects the digital data detected by the data detector 30 to demodulate 90 of FIG. Is applied.

The operation of the digital data correction means 100 will be described with reference to FIGS. 3 and 4 as follows.

First, the operation of the glitch component removing unit 40 is as follows.

Digital data in which the glitch component (hatched portion) is mixed from the data detector 30 with the original pure data component (remaining portion except the hatched) as shown in FIG. The first run length selector 42 and the primary delay unit 45 of the rising edge calculator 41 are respectively applied. In FIG. 4 (a), T _min represents a minimum run length of pure data excluding glitch from reproduction data.

In the first run length selector 42, the first integrator 43 integrates the output signal of the data detector 30 (FIG. 4 (a)) to calculate an inversion section area and integrates the integrated signal (FIG. b)) is applied to the level comparator 44.

In the first run length selector 42, the level comparator 44 sets a constant voltage level (+ V _ref1 in FIG. 4B) in the output signal of the first integrator 43 (FIG. 4B). In this section, the square wave shown in FIG. 4 (c) is generated and applied to the AND gate 41a.

The primary delay unit 45 delays the data signal of FIG. 4 (a) by a time corresponding to 1/2 of the minimum information interval T _min , and the delayed signal (FIG. 41a).

The AND gate 41a performs an AND operation on the output signal of the level comparator 44 (FIG. 4 (c)) and the output signal of the primary delay unit 45 (FIG. 4 (d)). A signal such as (e) is output to the data rising edge detector 61 of the data edge detector 60. The signal in FIG. 4E is the final output of the data rising edge calculator 41, and the signal in which the signal in FIG. 4A is first delayed by (T _min / 2) (FIG. 4D). ) Outputs only a square wave signal including the rising edge of the pure data (part ↑ of FIG.

On the other hand, the signal output through the primary delay unit 45 (Fig. 4 (d)) is a second run length selector 47 and the first end gate 46a of the data falling edge calculator 46, respectively Is approved.

In the second run length selector 47, the secondary delay unit 48 outputs the signal (FIG. 4 (d)) output through the primary delay unit 45 to the delay time T of the primary delay unit 45. _The delayed signal (Fig. 4 (f)) is applied to the first and second integrators 49a and 49 by delaying the time T _min / 4 corresponding to 1/2 of _min / 2). .

The first and gate 46a performs a logical product on the output signal of the primary delay unit 45 (FIG. 4 (d)) and the output signal of the secondary delay unit 48 (FIG. 4 (f)). As a result, a signal (FIG. 4 (i)) is applied to the second and gate 46b.

In the second run length selector 47, the second integrator 49 integrates the output signal of the secondary delay unit 48 (FIG. 4 (f)), calculates each inversion section region, and integrates the signal ( 4 (g) is applied to the level comparator 50.

In the second run length selector 47, the level comparator 50 sets a constant voltage level (+ V _ref2 in FIG. 4 g) in the output signal of the second integrator 49 (FIG. 4 g). In this case, a square wave as shown in FIG. 4 (h) is generated and applied to the second and gate 46b.

The second and gate 46b performs an AND on the output signal of the first and gate 46a (FIG. 4 (i)) and the output signal of the level comparator 50 (FIG. 4 (h)). A signal such as 4 degrees (j) is outputted to the data falling edge detector 65 of the data edge detector 60. The signal in FIG. 4 (j) is the final output of the data falling edge calculator 46, and the signal in which the signal in FIG. 4 (a) is first delayed by (T _min / 2) (FIG. 4 (d) ) Outputs only a square wave signal including the falling edge of the pure data (the ↓ part in FIG.

The operation of the data edge detector 60 is described below.

The output signal (FIG. 4E) of the data rising edge calculator 41 is applied to the data rising edge detector 61 and is applied to the first multiplier 64 and the AND gate 61a, respectively.

In the first multiplier 64, the tertiary delayer 62 delays the output signal of the data rising edge calculator 41 (FIG. 4E) for a predetermined time, which is at least the data rising edge calculation. It is set to a value smaller than the minimum information section (E _{min in} FIG. 4 (e)) of the output signal of FIG. (K) is applied to the exclusive OR gate 63.

The exclusive OR gate 63 performs an exclusive OR on the output signal of the data rising edge calculator 41 (FIG. 4 (e)) and the output signal of the tertiary delay unit 62 (FIG. 4 (k)). As a result, the resultant signal (Fig. 4 (l)) is applied to the AND gate 61a.

The AND gate 61a performs an AND on the output signal of the data rising edge calculator 41 (Fig. 4 (e)) and the output signal of the exclusive OR gate 63 (Fig. 4 (l)). The result signal (Fig. 4 (m)) is applied to the data reproducing section 70. The signal of FIG. 4 (m) is the final output of the data rising edge detector 61, and is composed of sharp square waves including only rising edges among the pure data of FIG.

On the other hand, the output signal (FIG. 4 (j)) of the data falling edge calculator 46 is applied to the inverter 66 while being applied to the data falling edge detector 65.

The inverter 66 phase-inverts the output signal of the data falling edge calculator 46 (FIG. 4 (j)) to convert the inverted signal (FIG. 4 (n)) into the second multiplier 69 and the AND gate. It is applied at 65a.

In the second multiplier 69, the fourth order delayer 67 delays the output signal of the inverter 66 (Fig. 4 (n)) for a predetermined time, which is at least the data falling edge calculator 46. ) Is set to a value smaller than the minimum information interval (J _{min in} FIG. 4 (j) and n in FIG. 4) of the output signal (FIG. 4 (j)) of the output signal (fourth delay unit 67) (O) is applied to the exclusive OR gate 68.

The exclusive OR gate 68 performs an exclusive OR on the output signal of the inverter 66 (FIG. 4 (n)) and the output signal of the quaternary delay unit 67 (FIG. 4 (o)). The resultant signal (Fig. 4 (p)) is applied to the AND gate 65a.

The AND gate 65a performs an AND on the output signal of the inverter 66 (FIG. 4 (n)) and the output signal of the exclusive OR gate 68 (FIG. 4 (p)), and the resultant signal ( FIG. 4 (q) is applied to the data reproducing section 70. FIG. The signal of FIG. 4 (q) is the final output of the data falling edge detector 65 and is composed of sharp square waves including only the falling edge of the pure data of FIG.

That is, the output signal of the data rising edge detector 61 (FIG. 4 (m)) and the output signal of the data falling edge detector 65 (FIG. 4 (q)) are the final output of the data edge detection unit 60. The signal composed of the pulses detected at each rising and falling edge of the pure data is applied to the data reproducing unit 70, and the data reproducing unit 70 detects the pulses detected at each rising and falling edge of the pure data. It recovers the original digital data from which the glitch has been removed from the signal consisting of the multiplexed signals.

The operation of the first embodiment of the data reproducing section 70 will now be described with reference to FIGS. 5 and 6.

In Fig. 5, the inverters 71 and 72 respectively output an output signal of the data rising edge detector 61 (Fig. 4 (m)) and an output signal of the data falling edge detector 65 (Fig. 4 (q). ) Is applied to the D flip-flop 73 by reversing the phase.

In the D flip-flop 73, the output signal of the inverter 71 (FIG. 6A) is applied to the preset terminal PR, and the output signal of the inverter 72 (the sixth terminal) is applied to the clear terminal CLR. (B) is applied, the D input terminal and the clock terminal CK are connected to ground, so that the signal of the Q output terminal is a preset signal (FIG. 6A) as shown in FIG. When applied, the operation state is maintained at the logic level of 'low' to 'high', and when the clear signal (Fig. 6 (b)) is applied, the operation of changing from 'high' to 'low' logic level is repeated.

7 and 8, the operation of the second embodiment of the data reproducing section 70 will be described. The second embodiment of FIG. 7 is a J-K flip-flop, whereas the first embodiment of FIG. 5 is a D flip-flop.

In FIG. 7, the NOR gate 74 is connected to the output signal of the data rising edge detector 61 (Fig. 8 (a)) and the output signal of the data falling edge detector 65 (Fig. 8 (b)). Negative logic is applied to the resultant signal (Fig. 8 (c)) to JK flip-flop 75.

In the JK flip-flop 75, an output signal (Fig. 8 (a)) of the data rising edge detector 61 is applied to the J input terminal, and an output signal of the data falling edge detector 65 (eighth) to the K input terminal. (B) is applied, and the output signal (No. 8 (c)) of the NOR gate 74 is applied to the clock terminal CK so that the signal of the Q output terminal outputs the same signal as in FIG. 8D. do.

As described above, in the digital magnetic recording and reproducing method and apparatus according to the present invention, a glitch component removing unit, a data edge detection unit and a data reproducing unit are provided in the output terminal of the data detector in a dependent manner to eliminate the glitch component that causes an error in the first half of the reproducing system. By transmitting only pure data, the devices installed at the rear end such as the reproduction clock recovery unit and the demodulation unit can be prevented from malfunctioning, and the BER of the entire reproduction system can be improved.

Claims (14)

A reproduction amplifier for amplifying the digital data read out from the recording medium through the reproduction head, a reproduction equalizer for compensating for degradation such as frequency characteristics of the signal output from the reproduction amplifier, and an output signal of the reproduction equalizer. A data detector for detecting digital data at the time of recording, a demodulator for demodulating the digital data detected by the data detector, an error correction decoder for performing error correction decoding on the output signal of the demodulator, and the error A compression signal expander for extending the output signal of the correction decoder to a signal before compression, a digital / analog converter for converting the output signal of the compressed signal expander into an analog signal, and between the data detector and the demodulator, Is incorporated into the digital data detected by the data detector. A digital magnetic recording and reproducing apparatus having digital data correction means for removing error components such as glitches and applying only pure digital data to the demodulator, wherein the digital data correction means is included in the digital signal output from the data detector. A glitch component removing unit for removing the glitch component; A data edge detector for detecting only an edge portion of original digital data in a signal output from the glitch component remover; And a data reproducing section for recovering original digital data from the signal output from the data edge detection section and applying the same to the demodulation section. 2. The apparatus of claim 1, wherein the glitch component removing unit comprises: a data rising edge calculator for calculating only a signal including a rising edge component of digital data detected by the data detector; And a data falling edge calculator for calculating only a signal including falling edge components of the digital data detected by the data detector. 3. The apparatus of claim 2, wherein the data rising edge calculator comprises: a primary delayer for first-delaying a half of a minimum information interval among digital data detected by the data detector; A run length selector for removing a pulse of a glitch component from the digital data detected by the data detector; And an AND gate for performing an AND function on the digital data delayed first through the first delay unit and the signal from which the glitch component is removed through the first run length selector. 4. The apparatus of claim 3, wherein the run length selector comprises: an integrator for integrating digital data detected by the data detector; And a level comparator for comparing the digital data integrated through the integrator with a predetermined level and selecting only a signal section of a predetermined level or more and transmitting the square wave. 3. The apparatus of claim 2, wherein the data falling edge calculator comprises: a run length selector for removing pulses of glitch components from the first order delayed digital data in the data rising edge calculator; A first and gate for performing an AND operation on the first delayed digital data in the data rising edge calculator and the second delayed digital data in the run length selector; And a second end gate for performing an AND operation on the output signal of the first end gate and the signal from which the glitch component is removed by the run length selector. 6. The apparatus of claim 5, wherein the run length selector comprises: a secondary delayer for delaying first-delayed digital data by one-half of the first delay period in the data rising edge calculator; An integrator for integrating the second delayed digital data in the secondary delay unit; and a level comparator for selecting only a signal section of a predetermined level or more and transmitting the square wave by comparing the digital data integrated through the integrator with a predetermined level. A digital magnetic recording and reproducing apparatus, characterized in that. The data edge detector of claim 1, wherein the data edge detector comprises: a data rising edge detector for detecting only the rising edge of the data in the signal output including only the rising edge from the glitch component removing unit; And a data falling edge detector for detecting only falling edges of data in a signal output from the glitch component removing unit including only falling edges. 8. The apparatus of claim 7, wherein the data rising edge detector comprises: a multiplier for generating pulses at each inversion point of the signal output including only the rising edges from the glitch component removing unit; And an AND gate for performing an AND operation on the signal output including only the rising edge and the signal output from the multiplier and outputting the result to the data reproducing section. The multiplier of claim 8, wherein the multiplier comprises: a third order delayer for delaying a signal output including only a rising edge from the glitch component removing unit for a predetermined period; And extracting and outputting only a pulse generated at a rising edge of digital data reproduced by performing an exclusive OR on a signal output including only a rising edge and a signal output from the tertiary delay unit by the glitch component removing unit. A digital magnetic recording and reproducing apparatus characterized by comprising an exclusive-OR gate. 10. The digital magnetic recording and reproducing apparatus according to claim 9, wherein the delay time of the tertiary delay unit is set to a value smaller than a minimum information section of a signal output including only a rising edge of the glitch component removing unit. 8. The apparatus of claim 7, wherein the data falling edge detector comprises: an inverter for phase inverting a signal including only falling edges from the glitch component remover; A multiplier for generating a pulse at each inversion point of the signal output from the inverter; And an AND gate for performing an AND operation on the signal output from the inverter and the signal output from the multiplier and outputting the result to the data reproducing unit. 12. The apparatus of claim 11, wherein the multiplier comprises: a fourth order delayer for delaying a signal output from the inverter for a predetermined period; And an exclusive OR gate for extracting and outputting only a pulse generated at a falling edge of digital data reproduced by performing an exclusive OR on the signal output from the inverter and the signal output from the fourth delay unit. Digital magnetic recording and reproducing apparatus. 13. The digital magnetic recording and reproducing apparatus according to claim 12, wherein the delay time of the fourth order delay unit is set to a value smaller than a minimum information section of a signal output including only the falling edge of the glitch component removing unit. 2. The apparatus of claim 1, wherein the data reproducing unit comprises: a plurality of logic gates for generating a logic recognition signal to recover original digital data from the rising edge signal and the falling edge signal detected from the data edge detector; And flip-flops for recovering original digital data from the rising edge signal and the falling edge signal detected by the data edge detector by the logic recognition signal output from the logic gate.