KR0177781B1 - Ferroelectric non-volatile semiconductor memory device - Google Patents

Abstract

1. The technical field to which the invention described in the claims belongs:

A nonvolatile semiconductor memory device using a capacitor formed by using a ferroelectric material as a memory.

2. The technical problem the invention is trying to solve:

Disclosed is a nonvolatile semiconductor memory device for minimizing polarization reduction caused by switching of a ferroelectric capacitor.

3. Summary of the Solution of the Invention:

A plurality of memory cell array units each symmetrically divided by a sense amplifier, each of which comprises a driving transistor and a capacitor having one end connected to the bit line;

A reference cell portion connected to the bit line, having a voltage level preset by a write control signal, and including a reference cell portion for reading and writing data of the memory cell array in correspondence with the voltage level.

4. Important uses of the invention:

Ferroelectric capacitors are suitable for nonvolatile semiconductor memory devices.

Description

Ferroelectric Nonvolatile Semiconductor Memory Devices

1 is a view illustrating a data input / output unit of a nonvolatile semiconductor memory device having a ferroelectric capacitor according to an embodiment of the prior art.

2 is a diagram illustrating a unit cell structure of a reference cell and a memory cell array according to an embodiment of the prior art.

3 illustrates a data input / output unit of a nonvolatile semiconductor memory device having a ferroelectric capacitor according to an embodiment of the present invention.

4 is a timing diagram showing a waveform of a write control signal controlled to a chip enable signal according to the present invention.

The present invention relates to a nonvolatile semiconductor memory device, and more particularly, to a ferroelectric capacitor nonvolatile semiconductor memory device using a capacitor formed by using a ferroelectric material as a memory.

Typically, semiconductor memory devices using ferroelectric capacitors have nonvolatile properties. The nonvolatile semiconductor memory device is composed of standard ram cells and has a small battery in which ferroelectric materials are sandwiched between two metal electrodes. Recently, NEC has started a chip with the largest memory capacity of 1MBIt using the above-mentioned ferroelectric capacitor. The memory cell of the nonvolatile semiconductor memory device is composed of one MOS field effect transistor and one ferroelectric capacitor. Therefore, the difference in the polarization direction of the ferroelectric capacitor is read as a charge. The structure description of the above-described nonvolatile semiconductor memory device is described in US Patent U.S.P., issued February 23, 1993, by inventor Kazuhiro Hoshiba. No. A detailed description is given under 5,189,594 in the heading capacitor in a semiconductor intergrated circuit and non-volatile memory using same.

1 illustrates a data input / output unit of a nonvolatile semiconductor memory device having a ferroelectric capacitor according to the related art. FIG. 2 is a diagram illustrating a unit cell structure of a reference cell and a memory cell array according to FIG. 1. Referring to FIGS. 1 and 2, both reference cells 101 of transistors 115 and 116 are connected to two adjacent bit lines BL and BLb, and gated according to an equalization control signal and connected to the pair of bit lines. Equalizes the voltage levels stored in, 102, 109, and 110 to intermediate levels. That is, if 1 is stored in the reference cell 101 connected to the BL and 0 in the reference cell array 102 connected to the BLb, 0 is stored in the reference cell 101 connected to the BL, and 1 is stored in the reference cell array 102 connected to the BLb. 115 equalizes to the intermediate level of the stored data 1 and 0, and then reads or writes the data of the memory cell arrays 107 and 108 through the sense amplifiers 105 and 106 at that level.

Similarly, data values of the reference cells 109 and 110 at the lower ends of the sense amplifiers 105 and 106 are equalized by the transistors 116 so that the data of the memory cell arrays 103 and 104 are compared and read and written through the sense amplifiers. In this case, the reference cell is composed of a driving transistor 111 having one end connected to a bit line and a capacitor 112 made up of a ferroelectric material connected between the other end and the ground voltage, as shown in FIG. As is the case, the configuration of the unit cells of the memory cell arrays 103, 104, 107, and 108 is the same. In the reference cell of this structure, a ferroelectric capacitor having a data of 1 causes a switching phenomenon every time data of the memory cell array is read and written. Here, it is generally known that a ferroelectric capacitor has a hysteresis curve, and a pulsed voltage is applied to read a charge of the capacitor, and when a threshold voltage or more is applied, the polarity of the charge is changed and the charge is changed. The amount of change in becomes large. In addition, at this time, the polarity of the charge is changed to cause characteristic fatigue and aging of the ferroelectric capacitor, which affects the lifetime of the ferroelectric capacitor. In other words, in view of the ferroelectric characteristics in which the polarization is reduced every time the above-described switching phenomenon occurs, the life of the reference cell is unbalanced because it has a considerably short life compared to the life of the ferroelectric capacitor having zero data.

Accordingly, an object of the present invention is to provide a nonvolatile semiconductor memory device for minimizing polarization reduction caused by switching of a ferroelectric capacitor.

Another object of the present invention is to provide a nonvolatile semiconductor memory device for minimizing aging of ferroelectric capacitors.

According to the technical idea of the present invention for solving the above object, a memory cell array having a plurality of memory cells consisting of a single access transistor and a ferroelectric capacitor, and the memory cell array is provided at one end of a channel of the access transistor. The symmetrically divided bit lines and complementary bit lines are connected to the sense amplifiers connected to each other, and selectively receive a word line control signal through a gate of the access transistor. The bit line has the same structure as that of the memory cell. And a pair of reference cells each connected to a complementary bit line and having a pair of reference cells symmetrically arranged by the sense amplifier, wherein the write is connected to and applied between one end of a capacitor of the pair of reference cells. Signal of symmetric split structure to invert control signal The inverting section and the data control mode alternately shift the level of the write control signal at regular intervals to provide the signal inverting section so that data in the pair of reference cells is alternately shifted. The reference level equalized by the sense amplifier is provided to each input of the sense amplifier, and the data level provided from the selected memory cell symmetrically divided into the equalized pair of reference cells is provided to the other input of the sense amplifier, respectively. It characterized in that it comprises a control unit. A nonvolatile semiconductor memory device having a plurality of memory cell array portions each comprising a driving transistor and a capacitor having one end connected to a bit line and symmetrically divided around a sense amplifier, each adjacent to the memory cell array portion, And a reference cell portion connected to the bit line and having a voltage level preset by a write control signal and providing a reference voltage for reading and writing data in the memory cell array corresponding to the voltage level. do.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a view illustrating a data input / output unit of a nonvolatile semiconductor memory device having a ferroelectric capacitor according to the present invention. Referring to FIG. 3, the memory cell array parts 121, 122, 125, and 126 are each symmetrically divided by sense amplifiers 123 and 124, and include a driving transistor 113 and a ferroelectric capacitor 114 having one end connected to bit lines BL and BLb. do. The reference cell units 119, 120, 128, 129 are connected to the bit line, have a voltage level (1 or 0) preset by a write control signal, and correspond to the memory cell arrays 121, 122, 125, Read and write 126 data. In this case, the reference cell units 119, 120, 128, and 129 are configured of the same driving transistor and ferroelectric capacitor as the memory cell array unit, and alternately change voltage levels of a first state and a second state in response to the write control signal. Save it. The write control signal is controlled by a chip enable signal and provided to one end of a driving transistor of the ferroelectric capacitor. The write control signal inverted by the inverters 117 and 116 is provided to the complementary bit line BLb adjacent to the bit line. That is, the write control signal is a signal for writing data back high or low by changing the polarization state of the ferroelectric capacitor 111 of the reference cells 119, 120, 128, and 129. The reference cell units 119 and 120 have different opposite values by the inverter 117 and are used as a reference when reading and writing data of the memory cell arrays 125 and 126. (Case 1) The reference cell units 128 and 129 have different opposite values and are used as a reference when reading and writing the cell data of the memory cell arrays 121 and 122. In this case, the equalization signal is set to a middle value of high and low in BL and BLb by connecting different opposite values of the reference cell 119 and the reference cell 120 in the operation of case 1 above. The write control signal is controlled by the chip enable signal and is an output of a circuit having an opposite output signal each time the chip enable signal is applied to the device. This circuit can also be implemented with binary counters and other circuits. The write control signal is a main concept. When the Nth chip is enabled, high data is written to the reference cell 119 and low data is written to the reference cell 120. When the N + 1th chip is enabled, the low data is written to the reference cell 119. The high data is written to prevent excessive fatigue of only the capacitor having the high data among the reference cells. Since the capacitors of the reference cell unit 119 and the reference cell unit 120, that is, the two cell units alternately have high data and accordingly, switching occurs, only one capacitor of the cell has a longer lifetime than when switching occurs.

4 is a timing diagram showing the waveform of the write control signal controlled to the chip enable signal according to the present invention. Referring to FIG. 4, the reference cell portion having 1 data in the T1 section has 0 data in the T2 section. At this time, it is apparent to those skilled in the art that a means for generating a light control signal for changing data in the reference cell unit is a known technique.

Therefore, according to the present invention, it is possible to make the life of the reference cell uniform and to minimize aging and fatigue of the ferroelectric capacitor due to polarization.

Claims (13)

A nonvolatile semiconductor memory device having a plurality of memory cell array portions each comprising a driving transistor and a capacitor, each of which is symmetrically divided about a sense amplifier, and one end of which is connected to a bit line; A reference voltage adjacent to the memory cell array unit, connected to the bit line, having a voltage level preset by a write control signal, and corresponding to the voltage level for reading and writing data in the memory cell array; A nonvolatile semiconductor memory device comprising a reference cell portion provided to a sense amplifier. 2. The nonvolatile semiconductor as claimed in claim 1, wherein the capacitor is a ferroelectric capacitor having one end connected to a ground voltage terminal and having a reduced polarization when switching, and the ferroelectric capacitor is a nonvolatile semiconductor device in which stored data is not destroyed even when power is removed. Memory device. The method of claim 1, wherein the reference cell unit comprises the same driving transistor and the ferroelectric capacitor as the memory cell array unit, and alternately stores the voltage level of the first state and the second state in response to the write control signal. Nonvolatile semiconductor memory device, characterized in that. The light control signal of claim 1 or 2, wherein the write control signal is provided at one end of a driving transistor of the ferroelectric capacitor, and the complementary bit line adjacent to the bit line is provided with an inverted light control signal by an inverting means. Nonvolatile semiconductor memory device characterized in that. The nonvolatile semiconductor memory device of claim 1, wherein the write control signal is a signal controlled by a chip enable signal and inverted by the chip enable signal. A memory cell array having a plurality of memory cells composed of a single access transistor and a ferroelectric capacitor, and the memory cell array having a sense amplifier connected to bit lines and complementary bit lines commonly connected to one end of a channel of the access transistor. Divided symmetrically with respect to the gate, and selectively receives a word line control signal through a gate of the access transistor, and is connected to the bit line and the complementary bit line in the same structure as the memory cell, and symmetrically by the sense amplifier. A nonvolatile semiconductor memory device having a pair of reference cells dividedly arranged; A signal inverting unit having a symmetric division structure for inverting a light control signal connected to one end of the capacitors of the pair of reference cells; In the data access mode, the level of the write control signal is alternately shifted at regular intervals and provided to the signal inverting unit so that the data in the pair of reference cells are alternately shifted, and the reference is equalized by either reference cell. And a control unit to provide a level to each input of the sense amplifier, and to provide the data level provided from the selected memory cell symmetrically divided into the equalized pair of reference cells to the other input of the sense amplifier. Nonvolatile semiconductor memory device, characterized in that. The nonvolatile semiconductor memory device of claim 6, wherein the signal inverting unit comprises one or more inverters. The light control signal of claim 6, wherein the write control signal is controlled by a chip enable signal and changes the polarization state of the capacitor to write back the stored data to the voltage level of the first state or the second state. Volatile semiconductor memory device. A nonvolatile semiconductor memory device comprising a reference cell array portion symmetrically arranged with respect to a bit line having an equalization circuit and a complementary bit line, and a memory cell array; And a control unit for alternately storing voltage levels of a first state and a second state at one end of each of the symmetrically divided reference cell array units. 10. The nonvolatile semiconductor memory device of claim 9, wherein the control unit is a binary counter circuit for outputting a write control signal, and further includes inverting means for providing different signals to the symmetrically divided reference cell unit. The binary counter circuit of claim 9 or 10, wherein the binary counter circuit is driven by a chip enable signal, and alternately stores voltage levels of the first state and the second state in response to the chip enable signal. And outputting the write control signal to the memory device. The method of claim 9, wherein the reference cell portion and the memory cell array portion is composed of a driving transistor and a capacitor, the capacitor is a ferroelectric capacitor whose one end is connected to the ground voltage terminal, the polarization is reduced during switching, the ferroelectric capacitor is the power source is removed Nonvolatile semiconductor memory device characterized in that the stored data does not disappear even if. The nonvolatile semiconductor memory device of claim 10, wherein the write control signal is provided at one end of a driving transistor of a ferroelectric capacitor of the reference cell unit.