KR0168155B1 - Flash Y pyrom cell and manufacturing method thereof - Google Patents
Flash Y pyrom cell and manufacturing method thereof Download PDFInfo
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- KR0168155B1 KR0168155B1 KR1019950005205A KR19950005205A KR0168155B1 KR 0168155 B1 KR0168155 B1 KR 0168155B1 KR 1019950005205 A KR1019950005205 A KR 1019950005205A KR 19950005205 A KR19950005205 A KR 19950005205A KR 0168155 B1 KR0168155 B1 KR 0168155B1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0411—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having floating gates
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/68—Floating-gate IGFETs
- H10D30/681—Floating-gate IGFETs having only two programming levels
- H10D30/683—Floating-gate IGFETs having only two programming levels programmed by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/68—Floating-gate IGFETs
- H10D30/6891—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/981—Utilizing varying dielectric thickness
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Abstract
본 발명은 플래쉬 이이피롬(FLASH EEPROM) 셀 및 그제조 방법에 관한 것으로, 스프리트-게이트(Split-gate) 구조를 갖는 플래쉬 이이피롬 셀의 제조에 있어, 고전압에 의해 게이트 산화막의 특성이 저하되는 것을 방지하기 위하여 셀(Cell)의 소거(Erase) 동작시 터널링 영역(Tunneling region)을 적층 채널(Stack channel)과 분리되도록 하여 소자의 신뢰성을 향상시킬 수 있도록 한 플래쉬 이이피롬 셀 및 그제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flash EEPROM cell and a method for manufacturing the same. In the manufacture of a flash epyrom cell having a split-gate structure, the characteristics of the gate oxide film are deteriorated by high voltage. Flash IPIROM cell and a method of manufacturing the same to improve the reliability of the device by separating the tunneling region (Tunneling region) from the stack channel during the erasure operation of the cell (Cell) to prevent will be.
Description
제1a도는 종래 적층게이트 구조의 플래쉬 이이피롬 셀의 단면도.1A is a cross-sectional view of a flash Y pyrom cell of a conventional stacked gate structure.
제1b도는 종래 스프리트게이트 구조의 플래쉬 이이피롬 셀의 단면도.1B is a cross-sectional view of a flash easy pyrom cell of a conventional splitgate structure.
제2a내지 제2h도는 본 발명에 따른 플래쉬 이이피롬 셀 제조 방법을 설명하기 위한 소자의 단면도.2A through 2H are cross-sectional views of a device for explaining a method of manufacturing a flash ypyrom cell according to the present invention.
제3a 및 제3b도는 본 발명에 의해 제조된 플래쉬 이이피롬 셀의 동작을 설명하기 위한 동작 상태도.3A and 3B are operational state diagrams for explaining the operation of the flash Y pyrom cell produced by the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 실리콘 기판 2 : 필드 산화막1: silicon substrate 2: field oxide film
3 : 버리드N+영역 4 : 게이트 산화막3: Buried N + region 4: Gate oxide film
5 및 5A : 터널 산화막 6 및 12 : 플로팅 게이트5 and 5A: tunnel oxide film 6 and 12: floating gate
7 및 7A : 소오스 영역 8 및 8A : 드레인 영역7 and 7A: source region 8 and 8A: drain region
9 : 셀렉트게이트 채널 영역 10 : 제1폴리실리콘층9: select gate channel region 10: first polysilicon layer
10A : 콘트롤 게이트 11 및 11A : 인터폴리 산화막10A: control gates 11 and 11A: interpoly oxide film
13및15 : 제1 및 제2감광막 14 : 플로팅 게이트 산화막13 and 15: first and second photoresist film 14: floating gate oxide film
A : 터널링 영역A: tunneling area
본 발명은 플래쉬 이이피롬(FLASH EEPROM) 셀 및 그제조 방법에 관한 것으로, 특히 스프리트-게이트(Split-gate)구조를 갖는 플래쉬 이이피롬 셀의 제조에 있어서, 셀(cell)의 소거(Erase)동작시 터널링 영역(Tunneling region)을 적층채널(Stack channel)과 분리되도록 하여 소자의 신뢰성을 향상시킬수 있도록 한 플래쉬 이이피롬 셀 및 그제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flash EEPROM cell and a method for manufacturing the same. Particularly, in the manufacture of a flash easy pyrom cell having a split-gate structure, an erase operation of a cell is performed. The present invention relates to a flash Y-pyrom cell and a method of manufacturing the same, wherein the tunneling region is separated from a stack channel to improve device reliability.
일반적으로 반도체 소자의 제조공정에서 전기적인 프로그램(Program) 및 소거(Erase) 기능을 함께 갖는 플래쉬 이이피롬(Electrically Erasable Programmable Read Only Memory; EEPROM)셀은 크게 적층-게이트(Stack-gate) 구조와 스프리트-게이트 구조로 나누어 진다.In general, an electrically erasable programmable read only memory (EEPROM) cell having both electrical program and erase functions in a semiconductor device manufacturing process has a large stack-gate structure and split. It is divided into a gate structure.
종래의 적층-게이트 구조를 갖는 플래쉬 이이피롬 셀은 제1a 도에 도시된 바와 같이 소오스, 드레인 및 버리드 드레인 영역(7, 8 및 8')이 형성된 실리콘 기판(1) 상에 터널 산화막(5), 플로팅 게이트(6), 인터폴리 산화막(11) 및 콘트롤 게이트(12)가 순차적으로 적층되어 형성되는데, 이러한 구조는 스프리트-게이트 구조에 비하여 단위 셀의 면적(Area)은 작지만 소거시 과도소거(Over-erase)되는 문제점을 갖고 있다. 또한 스프리트-게이트 구조를 갖는 플래쉬 이이피롬 셀은 제1b도에 도시된 바와 같이 소오스 및 드레인 영역(7 및 8)이 형성된 실리콘 기판(1)상의 상기 소오스 영역(7)을 일부 포함하는 부분에 터널 산화막(5), 플로팅 게이트(6), 인터폴리산화막(11) 및 콘트롤 게이트(12)가 순차적으로 적층되어 형성되며 상기 콘트롤 게이트(12)는 상기 드레인 영역(8)의 상부까지 연장되고 상기 연장된 콘트롤 게이트(12)와 상기 드레인 영역(8) 사이에는 셀렉트 게이트 채널 영역(9)이 형성된다. 그러나 이러한 구조를 이용하면 적층-게이트 구조와 비교하여 셀의 과도소거 문제는 해결될 수 있지만 상대적으로 단위 셀의 면적이 증가되어 셀렉트 채널 길이의 변화로 셀의 특성이 저하되는 단점이 있다.A conventional flash-ypirom cell having a stacked-gate structure has a tunnel oxide film 5 on a silicon substrate 1 on which source, drain, and bud drain region 7, 8, and 8 'are formed, as shown in FIG. ), The floating gate 6, the interpoly oxide film 11, and the control gate 12 are sequentially stacked. Such a structure has a smaller area of the unit cell than the split-gate structure but is over-erased during erasing. (Over-erase) has a problem. In addition, a flash Y pyrom cell having a split-gate structure has a tunnel in a part including the source region 7 on the silicon substrate 1 on which the source and drain regions 7 and 8 are formed, as shown in FIG. An oxide film 5, a floating gate 6, an interpoly oxide film 11, and a control gate 12 are sequentially stacked, and the control gate 12 extends to the upper portion of the drain region 8 and extends. The select gate channel region 9 is formed between the control gate 12 and the drain region 8. However, using this structure, the problem of over-erasing of the cell can be solved compared to the stacked-gate structure, but the area of the unit cell is relatively increased, resulting in a decrease in characteristics of the cell due to a change in the select channel length.
또한 종래의 플래쉬 이이피롬 셀은 터널 산화막이 약 100Å 정도로 얇게 형성되기 때문에 고전압(High Voltage)을 이용한 프로그램 및 소거시 접합 영역과 게이트 전극 간의 중첩 영역(Overlap region)에서 강한 전기장(Electric Field)이 형성되고, 이는 밴드-투-밴드 터널링(Band-to-band tunneling)과 2차 핫 케리어(Second hot carrier)를 발생시켜 게이트 산화막의 특성을 저하시킨다. 그러므로 상기와 같은 문제점들에 의해 소자의 신뢰성이 저하된다.In addition, in the conventional flash Y pyrom cell, since the tunnel oxide film is formed to be about 100 kV thin, a strong electric field is formed in the overlap region between the junction region and the gate electrode during programming and erasing using high voltage. This causes band-to-band tunneling and secondary hot carriers to degrade the gate oxide. Therefore, the reliability of the device is deteriorated by the above problems.
따라서, 본 발명은 스프리트-게이트 구조를 갖는 플래쉬 이이피롬 셀의 제조에 있어서, 셀의 소거 동작시 터널링 영역을 적층채널과 분리되도록 하여 상기한 단점을 해소할 수 있는 플래쉬 이이피롬 셀 및 그 제조 방법을 제공하는데 그 목적이 있다.Accordingly, the present invention provides a flash ypyrom cell having a split-gate structure, in which a tunneling region is separated from a stacked channel in an erase operation of the cell, thereby eliminating the above-mentioned disadvantages. The purpose is to provide.
상술한 목적을 달성하기 위한 본 발명에 따른 플래쉬 이이피롬 셀의 제조 방법은 실리콘 기판의 드레인 영역 및 소자 분리 영역을 확정한 후, 드레인 영역에 고농도 불순물 이온을 주입하여 버리드 드레인 영역을 형성한 후 필드 산화막을 형성하는 단계와, 전체 구조 상부에 게이트 산화막, 제1폴리실리콘층 및 인터폴리 산화막을 순차적으로 형성하는 단계와, 제1감광막을 도포하고 마스크를 이용한 사진 및 식각 공정을 통해 상기 제1감광막을 패터닝한 후 패터닝된 상기 제1감광막을 마스크로 이용한 식각 공정으로 상기 인터폴리 산화막, 제1폴리실리콘 및 게이트 산화막을 순차적으로 패터닝하여 콘트롤 게이트를 형성하는 단계와, 상기 패터닝된 제1감광막을 제거한 후 소정의 마스크를 이용하여 드레인 지역의 실리콘 기판을 노출시키고 고농도 불순물 이온을 주입하여 드레인 영역을 형성하는 단계와, 산화공정을 실시하여 전체 구조 상부에 플로팅 게이트 산화막을 형성하고 전체 면에 제2감광막을 도포한 후 상기 드레인 지역 및 필드 지역이 노출되도록 상기 제2감광막을 패터닝한 다음 식각 공정을 실시하여 상기 드레인 영역과 상기 필드 산화막이 접하는 부분의 실리콘 기판이 노출되도록 상기 플로팅 게이트 산화막 및 필드 산화막을 식각하는 단계와, 상기 패터닝된 제2감광막을 제거하고 전체 상부면에 터널 산화막을 형성한 다음 제2폴리실리콘층을 증착하고 패터닝하여 플로팅 게이트를 형성하는 단계와, 상기 실리콘 기판의 소오스 지역에 고농도 불순물 이온을 주입하여 소오스 영역을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.In the method for manufacturing a flash Y pyrom cell according to the present invention for achieving the above object, after determining the drain region and the device isolation region of the silicon substrate, a high concentration of impurity ions are implanted into the drain region to form a bird drain region. Forming a field oxide film, sequentially forming a gate oxide film, a first polysilicon layer, and an interpoly oxide film on the entire structure, applying the first photoresist film, and performing a photo and etching process using a mask. Patterning the photoresist layer and subsequently patterning the interpoly oxide layer, the first polysilicon layer, and the gate oxide layer in an etch process using the patterned first photoresist layer as a mask to form a control gate, and forming the patterned first photoresist layer. After removal, use a mask to expose the silicon substrate in the drain area Implanting water ions to form a drain region, and performing an oxidation process to form a floating gate oxide film over the entire structure, and apply a second photoresist film over the entire surface, and then expose the drain region and the field region. Etching the floating gate oxide layer and the field oxide layer to expose the silicon substrate in a portion where the drain region and the field oxide layer are in contact with each other by patterning a photoresist layer, and removing the patterned second photoresist layer, And forming a floating gate by depositing and patterning a second polysilicon layer on the surface, and implanting a high concentration of impurity ions into a source region of the silicon substrate to form a source region. It features.
또한 본 발명에 따른 플래쉬 이이피롬 셀은 필드 산화막이 형성된 실리콘 기판 상에 적층 구조로 형성된 게이트 산화막, 콘트롤 게이트 및 인터폴리 산화막과, 상기 게이트 산화막 일측부의 하부로부터 상기 필드 산화막까지 연장되도록 두껍게 형성된 플로팅 게이트 산화막과, 상기 필드 산화막의 하부에 형성된 버리드 드레인 영역과, 상기 플로팅 게이트 산화막 하부에 형성된 드레인 영역과, 상기 게이트 산화막의 다른 일측부로부터 소정거리 이격되어 상기 실리콘 기판에 형성된 소오스 영역과, 상기 소오스 영역의 일측부로부터 상기 필드 산화막의 일부가 포함 되도록 전체 상부면에 형성되며 노출된 실리콘 기판, 인터폴리 산화막, 플로팅 게이트 산화막 및 필드 산화막과는 터널 산화막에 의해 전기적으로 분리되도록 형성된 플로팅 게이트를 포함하여 구성되는 것을 특징으로 한다.In addition, the flash Y pyrom cell according to the present invention has a gate oxide film, a control gate and an interpoly oxide film formed in a stacked structure on a silicon substrate on which a field oxide film is formed, and a floating layer thickly formed so as to extend from the lower portion of the gate oxide film to the field oxide film A gate oxide film, a buried drain region formed under the field oxide film, a drain region formed under the floating gate oxide film, a source region formed on the silicon substrate at a predetermined distance from the other side of the gate oxide film, and A floating gate is formed on the entire upper surface to include a part of the field oxide film from one side of the source region and includes a floating gate formed to be electrically separated from the exposed silicon substrate, the interpoly oxide film, the floating gate oxide film, and the field oxide film by the tunnel oxide film. It is characterized by comprising.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제2a 내지 제2h도는 본 발명에 따른 플래쉬 이이피롬 셀의 제조 방법을 설명하기 위한 소자의 단면도이다.2A through 2H are cross-sectional views of devices for explaining a method of manufacturing a flash ypyrom cell according to the present invention.
제2a도는 실리콘 기판(1)의 드레인 지역을 확정하고 N형의 고농도 불순물 이온을 주입하여 버리드 N+드레인 영역(3)을 형성한 후 필드 산화막(2)을 형성한 상태의 단면도로서, 이때 필드 산화막(2)은 LOCOS(LOCal Oxidation of Silicon)공정을 이용하여 2000 내지 5000Å 정도의 두께로 형성한다.FIG. 2A is a cross-sectional view of a state in which a field oxide film 2 is formed after the drain region of the silicon substrate 1 is determined and the N-type high concentration impurity ions are implanted to form the buried N + drain region 3. The field oxide film 2 is formed to a thickness of about 2000 to 5000 microns using a LOCOS (LOCal Oxidation of Silicon) process.
여기에서 버리드 N+드레인 영역(3)을 필드 산화막(2) 하부에 형성하는 이유는 터널링 영역인 버리드 산화막을 적층 채널로부터 분리하여 형성하기 위함이다.The reason why the buried N + drain region 3 is formed below the field oxide film 2 is to separate the buried oxide film, which is a tunneling region, from the stacked channel.
제2b도는 전체 상부면에 게이트 산화막(4)을 300 내지 500Å의 두께로 형성하고 제1폴리실리콘층(10)을 형성한 후 산화막 및 질화막을 순차적으로 형성하여 인터폴리 산화막(11A)을 형성한 상태의 단면도이다.FIG. 2B illustrates that the gate oxide film 4 is formed to a thickness of 300 to 500 GPa on the entire upper surface, the first polysilicon layer 10 is formed, and then the oxide film and the nitride film are sequentially formed to form the interpoly oxide film 11A. It is a cross section of the condition.
제2c도는 제1감광막(13)을 도포하고 마스크를 이용한 사진 및 식각 공정을 통해 제1감광막(13)을 패터닝한 후 패터닝된 제1감광막(13)을 마스크로 이용한 식각 공정으로 인터폴리 산화막(11A), 제1폴리실리콘층(10) 및 게이트 산화막(4)을 순차적으로 패터닝하여 콘트롤 게이트(10A)를 형성시킨 상태의 단면도이다.FIG. 2C illustrates that the first photoresist layer 13 is coated, the first photoresist layer 13 is patterned through a photo-etching process using a mask, and the patterned first photoresist layer 13 is used as an mask. 11A), cross-sectional view of a state in which the control gate 10A is formed by sequentially patterning the first polysilicon layer 10 and the gate oxide film 4.
제2d도는 상기 패터닝된 제1감광막(13)을 제거한 후 소정의 마스크를 이용하여 드레인 지역의 실리콘 기판(1)을 노출시키고 비소(As)와 같은 N 형의 고농도 불순물 이온을 주입하여 드레인 영역(8A)을 형성한 상태의 단면도이다.FIG. 2d illustrates the removal of the patterned first photoresist layer 13 and then exposes the silicon substrate 1 in the drain region using a predetermined mask and implants an N-type high concentration impurity ion such as arsenic (As). It is sectional drawing of the state which formed 8A).
제2e도는 습식 산화 공정을 실시하여 전체 상부면에 플로팅 게이트 산화막(14)을 형성한 상태의 단면도인데, 이때 드레인 영역(8A)의 실리콘 기판(1)에서는 제2d도에서와 같이 주입된 N 형의 불순물 이온으로 인해 산화속도가 빨라져 플로팅 게이트 산화막(14)이 두껍게 형성된다.FIG. 2E is a cross-sectional view of the floating gate oxide film 14 formed on the entire top surface by performing a wet oxidation process, in which the silicon substrate 1 of the drain region 8A is implanted as in FIG. 2D. Due to impurity ions, the oxidation rate is increased, so that the floating gate oxide layer 14 is formed thick.
제2f도는 전체면에 제2감광막(15)을 도포한 후 상기 드레인 지역 및 필드 지역이 노출되도록 상기 제2감광막(15)을 패터닝한 다음 습식 식각 공정을 실시하여 드레인 영역(8A)과 필드 산화막(2)이 접하는 부분의 실리콘 기판(1)이 노출되도록 두껍게 형성된 플로팅 게이트 산화막(14) 및 필드 산화막(2)을 식각한 상태의 단면도이다. 여기에서, 드레인 영역(8A)과 필드 산화막(2)이 접하는 부분의 실리콘 기판(1)은 공정 완료 후 셀의 동작시 터널링 영역(A)이 된다. 또한, 플로팅 게이트 산화막(14)을 두껍게 형성하므로써 게이트와 드레인 영역(8A)간에 형성되는 고전기장에 의한 영향을 억제할 수 있다.FIG. 2F illustrates the second photoresist film 15 is coated on the entire surface, and then the second photoresist film 15 is patterned to expose the drain region and the field region, followed by a wet etching process to perform drain region 8A and the field oxide film. The sectional drawing of the floating gate oxide film 14 and the field oxide film 2 which were formed thick so that the silicon substrate 1 of the part which (2) may contact may be exposed is etched. Here, the silicon substrate 1 at the portion where the drain region 8A and the field oxide film 2 are in contact with each other becomes a tunneling region A when the cell is operated after completion of the process. In addition, by forming the floating gate oxide film 14 thickly, the influence of the high electric field formed between the gate and the drain region 8A can be suppressed.
제2g도는 상기 패터닝된 제2감광막(15)을 제거하고 전체 구조 상부에 터널 산화막(5A)을 80 내지 120Å의 두께로 형성한 다음 제2폴리실리콘층을 형성하고 패터닝하여 플로팅 게이트(12)를 형성시킨 상태의 단면도이다.FIG. 2g shows the floating gate 12 by removing the patterned second photoresist film 15, forming a tunnel oxide film 5A on the entire structure to a thickness of 80 to 120 μm, and then forming and patterning a second polysilicon layer. It is sectional drawing of the state formed.
이때, 버리드 N+드레인 영역(3)이 필드 산화막(2) 하부에 형성되어 있으므로 버리드 N+드레인 영역(3) 상부의 터널 산화막(5A) 즉, 터널링 영역(A)이 콘트롤 게이트(10A)와 분리되어 형성되게 된다.At this time, since the buried N + drain region 3 is formed under the field oxide film 2, the tunnel oxide film 5A on the buried N + drain region 3, that is, the tunneling region A, is controlled by the control gate 10A. Will be formed separately.
제2h도는 상기 실리콘 기판(1)의 소오스 지역에 비소(As)와 같은 N 형의 고농도 불순물 이온을 주입하여 소오스 영역(7A)을 형성하므로써 플래쉬 이이피롬 셀의 제조가 완료된 상태의 단면도인데, 그러면 이와 같은 방법에 의해 제조된 플래쉬 이이피롬 셀의 동작을 제3a도 및 제3b도를 통해 설명하기로 한다.FIG. 2h is a cross-sectional view of a state where the manufacture of the flash Y pyrom cell is completed by forming a source region 7A by injecting a high concentration of impurity ions such as arsenic (As) into the source region of the silicon substrate 1. The operation of the flash Y pyrom cell manufactured by the above method will be described with reference to FIGS. 3A and 3B.
제3a 및 제3b도는 본 발명에 의해 제조된 플래쉬 이이피롬 셀의 동작을 설명하기 위한 동작 상태도로서, 제3a도는 상기와 같이 형성된 플래쉬 이이피롬 셀의 프로그램시의 동작상태도이다. 프로그램시 소오스단자(7A) 및 드레인 단자(8A)에는 접지전위를 인가하고 콘트롤 게이트(10A)에 약 12V 정도의 고전압을 인가하면 터널링 영역(A)에서 드레인(8A)과 플로팅 게이트(12)간의 고전기장에 의한 터널링으로 플로팅 게이트(12)에 전자가 저장된다.3A and 3B are operational state diagrams for explaining the operation of the flash easy pyrom cell manufactured by the present invention, and FIG. 3A is an operational state diagram when programming the flash easy pyrom cell formed as described above. During programming, if a ground potential is applied to the source terminal 7A and the drain terminal 8A, and a high voltage of about 12 V is applied to the control gate 10A, the tunnel between the drain 8A and the floating gate 12 in the tunneling region A Electrons are stored in the floating gate 12 by tunneling by a high field.
제3b도는 상기와 같이 형성된 플래쉬 이이피롬 셀의 소거시의 동작상태도이다. 소거시 실리콘 기판, 소오스 및 콘트롤 게이트 단자(1, 7A 및 10A)에 접지전위를 인가하고 드레인 단자(8A)에 약 12V 정도의 고전압을 인가하면, 터널링 영역(16)에서 드레인(8A)과 플로팅 게이트(12)간의 고전기장에 의한 터널링으로 플로팅 게이트(12)에 저장되어 있던 전자가 방전된다.FIG. 3B is an operating state diagram when erasing the flash EPIROM cell formed as described above. When the ground potential is applied to the silicon substrate, the source and the control gate terminals 1, 7A, and 10A and the high voltage of about 12V is applied to the drain terminal 8A during erasing, the tunneling region 16 floats with the drain 8A. The electrons stored in the floating gate 12 are discharged by the tunneling by the high electric field between the gates 12.
본 발명에 따를 플래쉬 이이피롬 셀에서 플로팅 게이트 산화막(14)을 두껍게 형성하였지만, 프로그램 및 소거시의 터널링 영역(A)은 드레인 영역(8A)과 필드 산화막(2)이 접하는 부분의 실리콘 기판(1) 상부의 터널 산화막(5A) 부분이 되므로, 프로그램 또는 소거 동작에 따른 적당한 전압을 인가하게 되면 플로팅 게이트(12)와 드레인 영역(8A) 간에 이 터널링 영역(A)을 통하여 전자가 이동할 수 있게 된다.Although the floating gate oxide film 14 is thickly formed in the flash ypyrom cell according to the present invention, the tunneling region A during programming and erasing has a silicon substrate 1 in a portion where the drain region 8A and the field oxide film 2 contact each other. The upper portion of the tunnel oxide layer 5A becomes a portion of the tunnel oxide layer 5A, and when an appropriate voltage is applied according to a program or erase operation, electrons can move between the floating gate 12 and the drain region 8A through the tunneling region A. .
또한, 종래에는 터널링 영역이 게이트와 접합 영역 사이에 형성되어 있어 프로그램 및 소거시 강한 고전기장에 의해 밴드-투-밴드 터널링 현상이나 2차 핫케리어가 발생하는 등의 문제점이 있었으나, 본 발명에서는 버리드 N+드레인 영역(3)이 콘트롤 게이트(10A)와 분리되도록 필드 산화막(2) 하부에 형성한 후 터널 산화막(5A)을 형성하고, 버리드 N+드레인 영역(3) 상부의 터널 산화막(5A)을 통해 터널링이 일어나므로 프로그램 및 소거시 고전압을 인가하더라도 밴드-투-밴드 터널링 현상이나 2차 핫 케리어 발생 문제 등은 일어나지 않게 된다.In addition, in the related art, the tunneling region is formed between the gate and the junction region, which causes problems such as band-to-band tunneling phenomenon or secondary hot carrier due to a strong high field during programming and erasing. The drain N + drain region 3 is formed below the field oxide film 2 so as to be separated from the control gate 10A, and then the tunnel oxide film 5A is formed, and the tunnel oxide film above the buried N + drain region 3 ( Because tunneling occurs through 5A), even if high voltage is applied during program and erase, the band-to-band tunneling phenomenon and the secondary hot carrier generation problem do not occur.
상술한 바와 같이 본 발명에 의하면 셀의 소거 동작시 과도소거를 방지하며 터널링 영역을 적층 채널과 분리되도록 하여 게이트 산화막의 특성 저하를 방지하므로써 소자의 신뢰성이 향상될 수 있는 탁월한 효과가 있다.As described above, according to the present invention, there is an excellent effect of preventing over-erasing during the erasing operation of the cell and separating the tunneling region from the stacked channel to prevent deterioration of the characteristics of the gate oxide layer, thereby improving reliability of the device.
Claims (5)
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950005205A KR0168155B1 (en) | 1995-03-14 | 1995-03-14 | Flash Y pyrom cell and manufacturing method thereof |
| TW085102983A TW293948B (en) | 1995-03-14 | 1996-03-12 | Flash electrically erasable programmable read only memory cell and process thereof |
| US08/614,730 US5716865A (en) | 1995-03-14 | 1996-03-13 | Method of making split gate flash EEPROM cell by separating the tunneling region from the channel |
| CN96105549A CN1091951C (en) | 1995-03-14 | 1996-03-14 | Flash eeprom cell and method of making the same |
| US08/955,375 US5852312A (en) | 1995-03-14 | 1997-10-22 | Flash eeprom cell |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
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| KR1019950005205A KR0168155B1 (en) | 1995-03-14 | 1995-03-14 | Flash Y pyrom cell and manufacturing method thereof |
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| Publication Number | Publication Date |
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| KR960036089A KR960036089A (en) | 1996-10-28 |
| KR0168155B1 true KR0168155B1 (en) | 1998-12-15 |
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| KR1019950005205A Expired - Fee Related KR0168155B1 (en) | 1995-03-14 | 1995-03-14 | Flash Y pyrom cell and manufacturing method thereof |
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| US (2) | US5716865A (en) |
| KR (1) | KR0168155B1 (en) |
| CN (1) | CN1091951C (en) |
| TW (1) | TW293948B (en) |
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| KR100221627B1 (en) | 1996-07-29 | 1999-09-15 | 구본준 | Semiconductor device and the manufacturing method thereof |
| US6051465A (en) * | 1997-07-30 | 2000-04-18 | Matsushita Electronics Corporation | Method for fabricating nonvolatile semiconductor memory device |
| TW365056B (en) * | 1997-10-13 | 1999-07-21 | United Microelectronics Corp | Flash memory cell structure with split-gate and manufacturing method thereof |
| KR100444841B1 (en) * | 1997-12-29 | 2004-10-14 | 주식회사 하이닉스반도체 | Manufacturing Method of Flash Memory Cell |
| US6303438B1 (en) * | 1998-02-02 | 2001-10-16 | Matsushita Electric Industrial Co., Ltd. | Method for manufacturing a nonvolatile semiconductor memory device having increased hot electron injection efficiency |
| US6046086A (en) | 1998-06-19 | 2000-04-04 | Taiwan Semiconductor Manufacturing Company | Method to improve the capacity of data retention and increase the coupling ratio of source to floating gate in split-gate flash |
| US6369420B1 (en) * | 1998-07-02 | 2002-04-09 | Silicon Storage Technology, Inc. | Method of self-aligning a floating gate to a control gate and to an isolation in an electrically erasable and programmable memory cell, and a cell made thereby |
| US6309928B1 (en) | 1998-12-10 | 2001-10-30 | Taiwan Semiconductor Manufacturing Company | Split-gate flash cell |
| US6200860B1 (en) | 1999-05-03 | 2001-03-13 | Taiwan Semiconductor Manufacturing Company | Process for preventing the reverse tunneling during programming in split gate flash |
| JP3640180B2 (en) * | 2001-07-23 | 2005-04-20 | セイコーエプソン株式会社 | Nonvolatile semiconductor memory device |
| JP2003078041A (en) * | 2001-08-31 | 2003-03-14 | Matsushita Electric Ind Co Ltd | Semiconductor storage device and method of manufacturing the same |
| US7388250B2 (en) * | 2004-08-13 | 2008-06-17 | United Microelectronics Corp. | Non-volatile memory cell and manufacturing method thereof |
| CN100539158C (en) * | 2004-08-25 | 2009-09-09 | 联华电子股份有限公司 | Non-volatile memory unit and manufacturing method thereof |
| KR100780866B1 (en) * | 2006-12-14 | 2007-11-30 | 삼성전자주식회사 | Nonvolatile Memory Device and Formation Method |
| CN101330057B (en) * | 2007-06-21 | 2010-10-06 | 中芯国际集成电路制造(上海)有限公司 | Electric programmable device with embedded EEPROM and preparation method thereof |
| US8076734B2 (en) * | 2007-11-29 | 2011-12-13 | International Business Machines Corporation | Semiconductor structure including self-aligned deposited gate dielectric |
| CN102339833B (en) * | 2010-07-21 | 2013-04-24 | 中国科学院微电子研究所 | High-reliability split-gate non-volatile memory structure with high-speed low-voltage operation |
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| JPH07120719B2 (en) * | 1987-12-02 | 1995-12-20 | 三菱電機株式会社 | Semiconductor memory device |
| US5231041A (en) * | 1988-06-28 | 1993-07-27 | Mitsubishi Denki Kabushiki Kaisha | Manufacturing method of an electrically programmable non-volatile memory device having the floating gate extending over the control gate |
| US5427970A (en) * | 1994-07-18 | 1995-06-27 | United Microelectronics Corporation | Method of making flash memory with high coupling ratio |
| US5445984A (en) * | 1994-11-28 | 1995-08-29 | United Microelectronics Corporation | Method of making a split gate flash memory cell |
| US5550073A (en) * | 1995-07-07 | 1996-08-27 | United Microelectronics Corporation | Method for manufacturing an EEPROM cell |
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| US5716865A (en) | 1998-02-10 |
| CN1139277A (en) | 1997-01-01 |
| KR960036089A (en) | 1996-10-28 |
| US5852312A (en) | 1998-12-22 |
| CN1091951C (en) | 2002-10-02 |
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