KR0149571B1 - Transistor structure of semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor (also known as a pie-cell) structure of a semiconductor device, wherein a channel formed in a source and a drain has a channel width of an asymmetric structure. The present invention relates to a transistor structure of a semiconductor device capable of increasing efficiency, generating hot electrons effectively even under low bias conditions, and improving integration by arranging cells of an asymmetric structure (Pie structure).

Description

Transistor structure of semiconductor device

1A is a perspective view of a device shown for explaining a transistor structure of a conventional semiconductor device.

FIG. 1B is a flowchart of a carrier shown to explain the operation of FIG. 1A.

Figure 2a is a perspective view of the device shown for explaining the transistor structure of the semiconductor device according to the present invention.

2b and 2c are a flow chart and waveform diagram of a carrier shown for explaining the operation of FIG. 2a.

Figure 2d is a state diagram showing the flow of the carrier through the cross section for a certain time.

* Explanation of symbols for main parts of the drawings

11 semiconductor substrate 12 source

13: drain 14: floating gate

15: control gate

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the structure of transistors (also known as pie-cells) in semiconductor devices. In particular, each channel formed in the source and the drain has an asymmetric channel width. The transistor structure of the semiconductor element made to have it is related.

In general, the basic principle for programming non-volatile memory cells such as EPROM cells and Flash EEPROM cells (ie, to charge the floating gates) is the ground potential on the source. (Vss) is applied, 5V voltage is applied to the drain, and a high potential of 12V is applied to the control gate. That is, drain current flows through the channel on the source side, and a high-field by channel pinch-off is formed in the drain region to generate so-called hot-electron. The hot-electron is injected into the floating gate by the vertical electric field of the control gate to program the cell.

FIG. 1A is a perspective view of a device illustrated to explain a transistor structure of a conventional semiconductor device. Referring to FIG.

The transistor structure of a conventional semiconductor device composed of a source 2, a drain 3, a floating gate 4, and a control gate 5 on the semiconductor substrate 1 has a source 2A as shown in FIG. 1B. Since the channel width W and the channel length L of the and drains 3A are formed in a rectangular symmetrical structure, the electric field in the horizontal direction is determined only by the channel length in the X-direction. Therefore, if the channel length increases in the X-direction under the same bias condition, the strength of development in the horizontal direction is weakened, causing the carrier flow to be slowed, resulting in poor program efficiency, and effectively generating hot-electron under low bias conditions. It is difficult to do this. In addition, since the cells are formed in a rectangular symmetric structure, there is a disadvantage in that the degree of integration is low.

Accordingly, an object of the present invention is to provide a transistor structure of a semiconductor device that can solve the above-mentioned disadvantages by allowing the channels formed in the source and drain to have an asymmetric channel width.

The present invention for achieving the above object is characterized in that the channel formed on the drain side is formed of a fan-shaped asymmetric structure that is narrower than the channel formed on the source side.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

FIG. 2A is a perspective view of a device illustrated to explain a transistor structure of a semiconductor device according to the present invention, which will be described below with reference to FIGS. 2B to 2D.

The transistor structure of the semiconductor device according to the present invention, which is composed of a source 12, a drain 13, a floating gate 14, and a control gate 15 on the semiconductor substrate 11, has a drain side as shown in FIG. The channel width (W2) in the X-direction channel length (L) and the Z-direction channel width (W1) are made to be the same as the fan-shaped (Pie-shaped) asymmetric structure that is narrower than the channel width (W1) of the source side And W2) determines the strength of the electric field acting in the horizontal direction. That is, the relationship between the electric field E and the carrier speed V in the horizontal direction indicates that the carrier speed V becomes a saturation state Vsat above the electric field Ecrit of the critical point as shown in FIG. 2C. It can be seen that the carrier is most efficiently generated.

FIG. 2D is a state diagram showing the flow of the carrier passing through the cross section for a certain time. Looking at the relationship between the source and drain current (Ids) of the transistor and the carrier speed (V).

From the equation Ids = dQ / dt, V = dx / dt,

Ids = dQ / dt

= qnAdx / dt

= qnAV

= qn (Wdy) V

Therefore, the speed V of the carrier

V = Ids / (qndyW).

Where dQ is the time passed by any cross-sectional area for dt time

dx: distance traveled by carrier in dt time

V: Carrier Speed

q: charge amount of one carrier

n: number of carriers per unit volume

W: Channel width of transistor (Z-Dimension)

dy: effective channel length of transistor (Y-Dimension)

A: Effective cross section area (Wdy) through which the carrier passes

Therefore, when the channel width W2 on the drain side is made smaller than the source side W1, the carrier velocity at the source side where the carrier is injected into the channel and the drain side where the carrier is swept away by the electric field, that is, V-Source and V- If you get each drain,

V-Source = Ids / (qndyW1)

V-Drain = Ids / (qndyW2)

Velocity ratio (r) at both ends is

r = V-Drain / V-Source

= W1 / W2, where Ids is the same at the drain or source due to the continuity of the current

Becomes For example, if the channel width on the drain side is cut in half compared to the source side, the current flow density in the source will double in the vicinity of the drain, where it is halved, which doubles the velocity of the local carrier through the drain. Done.

As described above, according to the present invention, the channel formed in the source and the drain has an asymmetric channel width, thereby increasing program efficiency and effectively generating hot-electron even under low bias conditions, and asymmetric. By arranging the cells of the structure (Pie structure) to cross each other, there is an excellent effect to improve the degree of integration.

Claims (1)

A transistor structure of a semiconductor device composed of a source drain, a floating gate, and a control gate on a semiconductor substrate, wherein the channel formed on the drain side is formed in a fan-shaped asymmetric structure, which is narrower than the channel formed on the source side. Transistor structure of semiconductor device.