KR0148187B1 - Double screen and pip circuit - Google Patents

Abstract

The dual screen and picture-in-picture combination circuit is a signal processing system of a split screen television for simultaneously displaying a main screen and a sub-screen on a single screen, and adds a vertical compression circuit to the double screen circuit to provide a double screen and a PIP function. In addition, the PIP function can be selectively executed, and the PIP function can be displayed at a higher resolution than the conventional PIP screen.

Description

Double screen and picture-in-picture (PIP) combined circuit

1 is a block diagram showing the configuration of a conventional double screen circuit.

2 is a diagram showing an example of the configuration of a general double-screen screen

3 is a diagram showing the configuration of a typical Picture-In-Picture screen.

4 is a block diagram showing the configuration of a double screen and picture-in-picture function circuit according to a preferred embodiment of the present invention.

5 is a timing diagram for explaining the operation of each part in the FIG. 4 apparatus.

* Explanation of symbols for main parts of the drawings

30: main image processing unit 40: main screen mode selection unit

50: sub-image processing unit 60: sub-screen mode selection unit

31, 51: Sync separation unit 32, 52: Video signal processing unit

33, 53: A / D converter 35, 55: control unit

41, 61: Low pass filter (LPF) 42, 62: Mode switch

45: line memory 65: field memory

70: screen selection switch 80: D / A conversion unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a television having a double screen function capable of displaying two screens of the same size on a single screen. In particular, a picture-ln-picture (PIP) in a double screen circuit. The present invention relates to a double screen and picture in picture (PIP) function combined circuit that enables to execute a combination of a picture and picture-out-picture (POP) function.

As the functions of televisions are gradually diversified, the use of screen splitting televisions for splitting one screen and presenting a plurality of images together has become common. These screen splitting functions include a double screen function that divides a screen into left and right screens of the same size to display two screens at the same time, and a PIP that displays another screen reduced in a certain ratio to a portion of the main screen displayed on the screen. And POP functions. Here, since the execution method of the double screen function and the PIP function is different, a circuit for implementing the same should be provided separately. That is, in the double screen, the size of the main screen and the sub-screen are reduced to 1/2 in the horizontal direction, respectively, while in the PIP, the video signal of the sub-screen is reduced by a certain ratio in the horizontal and vertical directions and displayed simultaneously with the main screen. Therefore, there is a difference in circuit configuration to implement this.

FIG. 1 is a block diagram showing the structure of a conventional double screen circuit, and FIGS. 2 and 3 are diagrams showing examples of the configuration of a general double screen screen and a PIP screen. As shown in FIG. 1, the apparatus of FIG. 1 includes a main image processor 10 and a sub image processor 20 for receiving two composite image signals and displaying them in a predetermined area of the screen. 1 also includes a line memory 15 for recording the output signal of the main image processing unit 10 and a field memory 25 for recording the output signal of the sub-image processing unit 20. The main image processing unit 10 includes a first sync separator 11 and a main composite meditation signal Vl that separate vertical and horizontal synchronization signals H and Vsync from the main composite video signal V1 to be displayed on the main screen. The first video signal processor 12 and the first video signal processor 12, which separates the luminance signal Y and the color signal C, and demodulates the separated color signal, convert the output signals of the first video signal processor 12 into a digital main picture signal. A 1 A / D converter 13 is provided. The main image processing unit 10 also receives the horizontal and vertical synchronizing signals separated by the first synchronous separator 11, and writes and outputs the above-described line memory 15 and the first A / D converter 13. A first control unit 14 for controlling the operation is provided. The line memory 15 records the above-mentioned main picture signal in accordance with the write clock CW _L applied from the first controller 14, and writes in accordance with the read clock CR applied from the first controller 14. The data is read and output to the screen selection switch 16. On the other hand, the sub-image processing unit 20 receives the sub-complex video signal (V2) to perform the same operation as the main image processing unit 10, the second synchronous separation unit 21, the second video signal processing unit 22 ), The sub-screen signal input from the second A / D converter 23 is recorded in accordance with the write clock CWp applied from the second A / D converter 23 and the second controller 24, and the first controller 14 In accordance with the read clock (CR) applied from the read data is read and output to the screen selection switch (16). The screen selection switch 16 adaptively selects outputs of the line memory 15 and the field memory 25 in response to the switching signal SW applied from the first control unit 14 to convert the D / A conversion unit 17. )

The operation of the conventional double screen circuit configured as described above will be described in more detail.

In the FIG. 1 apparatus, in the case of displaying only one screen, the screen selection switch 16 is always connected to (a) the connection end. Then, the operation of the sub-image processing unit 20 is not executed, only the operation of the main image processing unit 10 is executed. That is, the main image processing unit 10 receives the main composite image signal Vl and processes the image, and then writes it in the line memory 15 according to the write clock CW _L applied from the first control unit 14. At this time, since the write clock CW _L and the read clock CR output from the first controller 14 to the line memory 15 are made of a clock signal having the same frequency as the output frequency of the first A / D converter 33. , The final video signal output through the D / A converter 17 is a normal screen without the reduction of the screen. On the other hand, when executing the double screen function, the screen selection switch 16 switches the connection terminals (a) and (b) in response to the switching signal SW from the first control unit 14. In addition, both of the above-described main image processing unit 10 and the sub image processing unit 20 are operated. That is, the main image processing unit 10 receives the main composite image signal Vl and processes the image, and transmits the main screen signal to the line memory 15 according to the write clock CW _L applied from the first controller 14. The sub-image processing unit 20 receives the sub-complex image signal V2 and performs image processing, and outputs the sub-screen signal according to the write clock CW _F applied from the second control unit 24. To record. At this time, the first controller 14 outputs the clock frequency of the read clock CR to twice the clock frequency of the write clock CW _L to the line memory 15. Then, the size of the screen on which the main composite video signal Vl is displayed is reduced to ½. When the read operation of the line memory 15 is completed, the first controller 14 outputs the read clock CR having the same frequency as that of the read clock CR of the line memory 15 to the field memory 25. Then, the sub picture signal recorded in the field memory 25 is read out in accordance with the read clock CR from the first controller 14 and supplied to the D / A converter 17 through the screen selection switch 16. . At this time, the contact of the screen selection switch 16 is switched according to the switching signal SW applied from the first control unit 14 to output the output signal of the line memory 15 and the output signal from the field memory 25. By sequentially applying to the A conversion section 17, the double screen function is executed.

In the conventional double screen circuit as described above, the main screen and the sub-screen are compressed to 1/2 size, respectively, so that two images of the same size can be displayed together on one screen. However, in the case of the PIP function, the video signal displayed on the sub-screen is reduced by sampling in the horizontal and vertical directions and displayed together with the main screen, so that the PIP function cannot be executed in the above-described conventional double screen circuit. In addition, in the general PIP screen, the screen is reduced by downsampling the video data corresponding to the sub-screen at a predetermined ratio to compress the screen, thereby reducing the resolution by the sampling rate.

Accordingly, an object of the present invention is to add a vertical compression circuit to the double screen circuit to selectively execute the double screen and the PIP function, and at the same time, when the PIP function is executed, the PIP screen having a higher resolution than the conventional PIP screen It is to provide a double screen and picture-in-picture circuit that enables the display.

In order to achieve the above object, the double screen and picture-in-picture combined circuit of the present invention is a signal processing system of a split-screen television for simultaneously displaying a main screen and a sub-screen on a single screen. Video signal processing means for receiving the composite video signal and the sub-complex video signal corresponding to the sub-screen and processing the video into a main screen signal and a sub-screen signal for display on the screen; Mode selection means for selecting a screen division mode of the main screen signal and the sub picture signal outputted from the video signal processing means; A first memory for recording and outputting the main picture signal in units of scanning lines of the main picture signal; A second memory for recording and outputting sub-screen signals in field units; And a clock for controlling the selection operation of the above mode selection means by receiving horizontal and vertical synchronization signals separated from the main composite video signal and the sub composite video signal, and controlling the recording and output operations of the first memory and the second memory. System control means for generating a signal; And signal selection means for selectively outputting output signals of the first memory and the second memory in response to a switching signal applied from the system control means to perform screen division of the mode selected by the mode selection means.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is a block diagram showing the configuration of a double screen and picture-in-picture function circuit according to a preferred embodiment of the present invention. As shown in FIG. 4, the circuit of FIG. 4 includes a main screen mode selector 40 and a sub picture mode selector 60 for switching the signal processing modes of the main screen signal and the sub picture signal according to whether the double screen function and the PIP function are executed. ). The main screen mode selection unit 40 includes a first mode switching switch 42 for switching the mode Ml for executing the normal screen and the PIP function and the mode M2 for executing the double screen function to the main screen; And a first low range connected between the first A / D converter 33 in the main image processing unit 30 and the (M2) terminal of the first mode switching switch to prevent the overlapping of the horizontal frequency when the double screen function is executed. A low pass filter (hereinafter referred to as LPF) 41 is provided. The sub picture mode selection unit 60 also includes a second mode switching switch 62 for switching the mode S1 when the double screen function is executed for the sub screen and the mode S2 when the PIP function is executed, and A second low pass filter connected between the second A / D converter 53 in the sub-image processing unit 50 and the (S2) terminal of the second mode changeover switch 62 to prevent overlapping of vertical frequencies when the PIP function is executed. 61 is provided. Here, the first mode switching switch 41 and the second mode switching switch 46 are switched by the switching signals SWI and SW2 applied from the first control unit 35 and the second control unit 45, respectively. Further, the first low pass filter 41 is a filter for pixels in the horizontal direction, and the second low pass filter 61 is a filter for pixels in the vertical direction. The other circuit configuration is the same as that of the first circuit.

The operation of the double screen and the picture-in-picture combined circuit according to the present invention configured as described above will be described in more detail with reference to FIGS. 2 to 5.

FIG. 5 is a timing diagram illustrating the operation of each part in the apparatus of FIG. 4.

In general, in case of NTSC, the A / D conversion clock of the main screen uses 910f _H , but for the convenience of explanation, the A / D conversion clock of 20f _H is used here. Furthermore, only the luminance signal Y of the luminance signal Y and the color difference signals RY and BY of the video signal is shown.

In FIG. 4, the signal processing in the case of displaying only one normal screen is the same as the operation of the first circuit. That is, the first synchronous separator 31 in the main image processor 30 separates the horizontal and vertical synchronous signals H and Vsync of the main composite image signal Vl and outputs them to the first controller 35. The first video signal processor 32 separates the main composite video signal Vl into a luminance signal Y, a red difference signal RY, and a blue difference signal BY, and displays the image on the screen. The data is output to the first A / D converter 33. The first A / D converter 33 performs the above-described luminance signal Y and color difference signals RY and BY according to the main picture A / D conversion clock (main picture A / D CK) applied from the first control unit 35. These signals are converted into digital main picture signals and output. At the beginning of FIG. 5, the main picture signal in which the luminance signal Y, the red difference signal RY, and the blue difference signal BY are respectively quantized into 8 bits is shown as an example of the luminance signal Y. Main Screen A / D out). FIG. 5A is a timing diagram illustrating operations of the main image processing unit 30 and the main screen mode selection unit 40 when the normal screen or the PIP function is executed. When displaying the normal picture, the first mode changeover switch 42 of the main picture mode selector 40 is connected to the (Ml) end. Then, the main picture signal output from the first A / D converter 33 does not pass through the first LPF 41, but directly to the line memory 45 in accordance with the write clock CW _L from the first control unit 35. Ml out. The line memory 45 reads the main screen signal recorded according to the read clock CR _L applied from the first controller 35 and outputs the main screen signal to the screen selection switch 70. As shown in FIG. 5A, the clock frequencies of the write clock CW _L and the read clock CR _L of the line memory 50 are the same. On the other hand, when displaying the normal screen, the screen selection switch 70 is always connected to the (a) stage, so that the main screen signal read out from the line memory 45 is output to the D / A converter 70 ((a ) out) Therefore, the original main picture signal which is not reduced is displayed on the screen.

5 (b) is a timing diagram showing the operation of each part when the double screen function is executed. When the double screen function is to be executed, the first control unit 35 switches the first mode switching switch 42 of the main screen mode selection unit 40 to the M2 stage. Then, the main picture signal output from the first A / D converter 33 is input to the line memory 45 through the first LPF 41. Herein, when the first LPF 41 samples the main picture signal in the horizontal direction 1/2 and writes it to the line memory 45 to execute the double screen function, the overlapping between adjacent spectra of the frequency band is performed. In order to prevent this from occurring, the frequency band width of the main picture signal quantized in units of predetermined bits (8 bits in FIG. 5) in the first A / D converter 33 is limited to less than half of the sampling frequency. do. At this time, the first controller 35 outputs the write clock CW _L , which is 1/2 of the clock frequency for A / D conversion, to the line memory 45.

Then, the main picture signal quantized in units of 8 bits by the first A / D converter 33 is sampled by a predetermined transfer function and recorded in the line memory 45. An example of the shape of the sampled main picture signal is shown in the front half of {[M2, S1) out} in FIG. 5 (b), and the aforementioned transfer function is assumed to be (1 + Z ⁻¹ ) ÷ 2. That is, the line memory 45 records data obtained by averaging the data currently input and the previous data input one clock before the write clock CW _L applied from the first controller 35. The first control unit 35 also outputs a read clock CR _L having the same frequency as the clock frequency for A / D conversion to the line memory 45 to read the recorded signal {(a) out}. In FIG. 5 (b), the data indicated by (Y ₀ ′, Y ₁ ′…) reads the data recorded in the line memory 45 by the above-described transfer function in accordance with the above-described read clock CR _L. It represents. On the other hand, the second controller 55 switches the second mode selector switch 62 of the sub picture mode selector 60 to the step S1. Then, the sub picture signal output from the second A / D converter 53 is directly input to the field memory 65 without passing through the second LPF 61. At this time, the second controller 55 outputs the A / D conversion clock of half the frequency of the sampling frequency for the above described main screen in the 2A / D converter 53, and write this in the same clock frequency (CW _F ) Is output to the field memory 65. Then, the sub-picture signal quantized in units of 8 bits in the second A / D converter 53 is sampled as shown in the rear half of {(M2, 51) out} of FIG. The data is written to the address of the field memory 65 set by the horizontal and vertical synchronization signals H and Vsync of the sub picture. Here, the A / D conversion clock frequency of the sub picture is 1/2 of the main screen sampling frequency, which is used only when the double screen and the PIP function are executed in the sub picture, so it is necessary to use a high sampling frequency like the main picture. It is based on the absence. The field memory 65 reads out the sub picture signal recorded in accordance with the read clock CRr applied from the first control unit 35 and outputs it to the screen selection switch 70 ((b) out). The frequency of the read clock CR _F described above is the same as the read clock CR _L of the line memory 45. That is, since the read clock CR _F of the field memory 65 is twice the frequency of the write clock CW _F , the screen reduced to 1/2 such as the main screen can be displayed. At this time, the first controller 35 outputs the {(b) out} signal of the address corresponding to the line number of {(a) out} shown in FIG. 5 (b) to the D / A converter 80. It generates a switching signal (SW _M ) to enable to switch the mode of the screen selection switch (70). When the switching signal SW _M is applied as shown in FIG. 5 (b), the signal output from the screen selection switch 70 to the D / A converter 80 becomes the same as the {D / A converter IN}. The double screen as shown in Figure 2 is executed.

FIG. 5C is a timing diagram showing the signal processing operation of the sub picture signal when the PIP function is executed in the FIG. 4 circuit, and FIG. 5D is a diagram showing the signal processing operation in the general PIP circuit. . In general, in order to execute the PIP function, the sub screen should be reduced with a certain ratio in the horizontal and vertical directions and displayed together with the main screen. First, in the case of horizontal reduction, the screen is reduced by making the read clock CR _f faster than the write clock CW _F of the field memory by the ratio to reduce the sub screen. In this case, in the general PIP circuit, the read memory CRr of the field memory is left as it is, and the PIP function is executed by lowering the write clock CWr frequency by a ratio to reduce the resolution. On the other hand, in the case of vertical reduction, the number of scanning lines of the sub picture signal is downsampled and reproduced by the ratio to be reduced. That is, in the case of reducing the size 1/3 times in the horizontal and vertical directions, the read clock CR _F frequency of the above-described field memory should be three times the frequency of the write clock CW _F , and the second controller writes to the field memory. The field memory must be controlled to read only lines corresponding to the number of 1/3 scan lines of each field.

In the case of executing the PIP function in the circuit of FIG. 4, the first controller 35 switches the above-described first mode selector switch 42 to the (Ml) stage. Then, the signal processing operation of the main picture signal is the same as that of the normal picture display shown in FIG. In addition, the second controller 55 switches the above-described second mode selection switch 62 to the step S2. Then, the sub picture signal output from the second A / D converter 53 is output to the field memory 65 through the second LPF 61. Here, the second LPF 61 is for preventing the overlapping of the vertical frequency when sampling the scanning line of the sub picture signal by the ratio to be reduced in order to execute the PIP function. At this time, the second controller 55 maintains the write clock CW _{F of} the field memory 65 as it is, and increases the signal by increasing the read clock CR _F frequency by the ratio desired to reduce the signal written in the field memory 65. Read out. In FIG. 5 (C), an example is shown in which the horizontal resolution of the PIP screen is doubled by making the read clock CRr frequency of the field memory 65 twice as large as the write clock CW _F frequency. When the PIP screen is to be reduced by 1/3 times in the vertical direction, the second controller 55 counts the horizontal synchronization signal in synchronization with the horizontal synchronization signal of the sub-screen signal, and stores the horizontal synchronization signal in the field memory 65. Only lines corresponding to 1/3 scan lines of the field are read out. In the case of NTSC, only the lines proceeding from 1, 4, 7 ... to 262.5 lines are read out for each field, and vertical compression is performed. At this time, it is also possible to write only 1/3 of the lines in the field memory 65 from the beginning and read them as they are. Further, in FIG. 4, an embodiment in which the line memory is expanded to a field memory and the field memory is extended to a frame memory or the like may be replaced.

When the PIP function is executed as described above, the double screen and the PIP function can be selectively executed by simply adding a simple circuit to the existing double screen circuit. In addition, when the PIP function is executed in the circuit of the present invention, there is an effect that the horizontal resolution can be improved by twice or more than the conventional PIP circuit.

Claims (13)

A signal processing system of a split-screen television for simultaneously displaying a main screen and a sub-screen on one screen, wherein the main composite video signal corresponding to the main screen and the sub-complex video signal corresponding to the sub-screen are input to the screen. Image signal processing means for performing image processing on the main picture signal and the sub picture signal for display; Mode selection means for selecting a screen division mode of the main picture signal and the sub picture signal outputted from the video signal processing means; A first memory for recording and outputting the main picture signal in units of scanning lines of the main picture signal; A second memory for recording and outputting the sub picture signal in field units; And receiving horizontal and vertical synchronization signals separated from the main composite video signal and the sub composite video signal to control the selection operation of the mode selection means, and to control the recording and output operations of the first memory and the second memory. System control means for generating a clock signal; And a signal selecting means for selectively outputting output signals of the first memory and the second memory in response to a switching signal applied from the system control means to perform screen division of the mode selected by the mode selecting means. Screen and picture-in-picture circuit. The display apparatus of claim 1, wherein the video signal processing unit receives the main composite video signal, converts the main video signal into a main screen signal to be displayed on the screen, and outputs the main video signal to the sub-complex video signal. A dual screen and picture in picture function combined circuit comprising a sub-image processing unit for converting and outputting a signal. 3. The apparatus of claim 2, wherein the main image processing unit and the sub image processing unit comprise video signal processing means for performing synchronous separation and color difference separation on the input composite video signal and demodulating the separated color signal; And an A / D converter for converting the signal demodulated by the video signal processing means into a digital main picture signal or a sub picture signal and outputting the converted picture to the first memory or the second memory. Double screen and picture-in-picture circuit. The display apparatus according to claim 3, wherein the mode selection means includes a main screen mode selection unit for selecting a screen division mode of the main screen, and a sub picture mode selection unit for selecting a screen division mode of the sub screen. Double screen and picture-in-picture combination circuit. 5. The apparatus of claim 4, wherein the main picture mode selection unit switches between a first mode for selecting a normal picture and a picture-in-picture function of the main picture and a second mode for selecting a double screen function under the control of the system control means. A first mode switch; And a first low range connected between the first A / D converter provided in the main image processing unit and the second mode selection terminal of the first mode changeover switch to prevent overlapping of horizontal frequencies when the double screen function is executed. Double screen and picture-in-picture circuit with pass filter. The method of claim 4, wherein the sub-screen mode selection unit switches a third mode for selecting a double screen function of the sub-screen and a fourth mode for selecting a picture-in-picture function under the control of the system control means. A mode switch; And a second low range connected between a second A / D converter provided in the sub-image processing unit and a fourth mode selection terminal of the second mode selector switch to prevent the aliasing of the vertical frequency when the picture in picture function is executed. Double screen and picture-in-picture circuit with pass filter. The method of claim 1, wherein the system control means controls the switching operation of the first mode changeover switch according to the screen division mode of the main screen, and converts clock frequencies of write and read clocks applied to the first memory. A first control unit converting a clock frequency of a read clock applied to the second memory according to the screen division mode of the sub-screen, and generating a switching signal for controlling the signal selection means; And setting a sampling frequency of the sub-screen to 1/2 of a sampling frequency of the main screen, outputting the same to a second A / D converter in the sub-image processing unit, according to the screen division mode of the sub-screen. And a second control unit which controls a switching operation of a mode switching switch and applies a write clock for recording the sub-screen signal to the second memory. 8. The method of claim 7, wherein the first control unit switches the first mode changeover switch to the second mode when the double screen function is executed, and sets the read clock frequency of the first memory to twice the write clock frequency. And a read clock having a frequency equal to the read clock frequency of the first memory to the second memory. The second memory of claim 8, wherein the second control unit switches the second mode changeover switch to the third mode when the double screen function is executed, and writes a write clock having a frequency equal to a sampling frequency for the sub-screen. Double screen and picture-in-picture combined circuit, characterized in that applied to. 8. The method of claim 7, wherein the first control unit switches the first mode switch to the first mode when the picture-in-picture function is executed, and makes the write clock and read clock frequencies of the first memory the same. And applying to one memory and applying the read clock frequency of the second memory to the second memory faster than the write clock frequency of the second memory by the ratio of horizontally reducing the sub-screen. And a picture-in-picture function circuit. 11. The method of claim 10, wherein the first control unit reads the sub-clock signal to read the sub-screen signal by reducing the number of vertical lines by a ratio corresponding to the vertical compression ratio of the sub-screen when the picture-in-picture function is executed. And a double screen and a picture-in-picture function circuit which is generated and applied to the second memory. The double screen of claim 11, wherein the second control unit switches the second mode switch to the fourth mode when the picture in picture function is executed, and does not change the write clock of the second memory. And a picture-in-picture function circuit. The display apparatus of claim 12, wherein the signal selecting means comprises a main screen signal read from the first memory in response to a switching line applied from the first memory in response to a scan line of the main screen signal. A double screen and picture-in-picture circuit, which operates to continuously output a sub-screen signal read out from an address.