JPS63269127A - Manufacturing method of active matrix liquid crystal display panel - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is an active matrix type display panel, that is, a display drive circuit is provided between each pixel electrode in the substrate of the display panel and a scanning electrode that applies a display voltage to the pixel electrode. The present invention relates to a method of manufacturing a liquid crystal display panel in which a thin film semiconductor element is incorporated.

[Conventional technology]

Liquid crystal display panels are popular for their thinness and are widely used as display panels for small electronic devices such as calculators and watches, but they are also used for displaying more complex images such as on televisions. Its uses are expanding, and this new field requires larger display areas and higher density image quality.

In order to both increase the area and improve the image quality, it is necessary to increase the number of pixels of the display panel to at least tens of thousands or more, but the external circuit for driving the display panel needs to increase accordingly. Therefore, the above-mentioned active matrix type display panel, in which a relatively simple thin film semiconductor element is incorporated into the display panel substrate as a display driving active element, has become advantageous.

Thin film transistors (
TPT), MIM (metal-insulator-metal) elements, and varistors.

They are broadly classified into two terminal nonlinear elements such as diodes, but the latter type, which has a simpler structure, is generally easier to manufacture, has less variation in characteristics, and has stable operation when incorporated into display panels. It is said to be advantageous in that it has good characteristics. Figure 6 shows the structure of a conventional liquid crystal display panel using anti-parallel connected diodes as built-in active elements with two terminals, and Figure 7 shows the manufacturing process of one diode section using the conventional technology. .

FIG. 6 shows an enlarged view of one pixel of a pair of substrates constituting a display panel in which a display driving element is incorporated, and the pixel electrode 20 is the display electrode for this one pixel,
A scanning electrode strip 30 is provided in common for a large number of pixel electrodes 20 arranged in the left-right direction in the figure. Two f1111 diodes 11.12 are inserted between these pixel electrodes 20 and scan electrodes 30 in anti-parallel connection. One of the diodes 11 is provided on the bulge 30a of the scanning electrode 30 and connected to the pixel electrode 20 via the connection layer 50, and the other diode 12 is provided on the pixel electrode 20. It is connected to the scanning electrode 30 via another connection layer 50. The pixel electrode 2 corresponds to the bulge 30a of the scanning electrode 30.
A notch 20a is made on the side of 0, and a diode 12 is placed on the side of the notch 20m, so that both diodes 11 and 12 are concentrated in one corner of the rectangle of one pixel. An alignment film 20b for aligning liquid crystal molecules is deposited on the remaining part of the 0 pixel electrode 20, excluding the part where the diode is arranged or the connection part with the diode, as shown by partial hunting in the figure. The part to which the alignment film is applied becomes the actual display part whose brightness changes depending on the display voltage. The ratio of this display area to the total area of the pixel is called the aperture ratio, and is one important indicator of the performance of the display panel.

FIG. 7 shows the manufacturing process of one diode section shown in FIG. 6 in a cross section taken along the line X--X, and the other diode is similarly manufactured in the same process.

In the process shown in FIG. 1a), a thin transparent conductive film 2 made of, for example, ITO (indium tin oxide) is deposited on the entire upper surface of the substrate l, which is a transparent glass plate.

In the photoetching step (color in the same figure), the pixel electrode 20 and the scanning electrode 30 are formed by predetermined patterning using an appropriate mask layer M1. In the same figure (C1 is a step of depositing a semiconductor element, a thin light-shielding film 3a made of, for example, a Cr layer, a semiconductor film 3 of a pin structure such as amorphous silicon, and the same light-shielding film 3b as before are sequentially deposited.

In the same figure (dl is a photo-etching process of a semiconductor film including a light-shielding film, a semiconductor element IEiIO is patterned by removing parts other than the diode part using a mask layer M2. step p
Approximately 0.5- for in configuration, 1 for 2-stage pin configuration
It is a thin film on the order of μ. In the same figure (el is the step of depositing the insulating film 4, for example, a Ti film of silicon nitride is grown.
The mask layer M3 is used in the photoetching process to form the sixth layer.
Two diodes 11.
The insulating layer 4o is formed by leaving a common area for 12 and removing the other portions, and a window 40a communicating with the top surface of the semiconductor element JillO is opened. Both diodes 11, 12 are thereby protected by a common insulating layer 40. The same figure (1 is the deposition process of the metal layer 5,
A metal layer 5 is deposited or sputtered so as to be in conductive contact with the light shielding film 3b on the top surface of the semiconductor element layer 10 through the window 40m. In the photo-etching process shown in FIG. 5H, a connection layer 50 is formed by patterning using the mask layer M4. As a result, the light-shielding film 3b as the upper electrode of the semiconductor element layer 10 is connected to the pixel electrode 20 via the connection N50, but at this time, the scanning electrode has the same potential as the light-shielding film 3a as the lower electrode of the semiconductor element layer 10. 30 and the pixel electrode 20 are separated from each other in terms of conductivity by the interposition of an insulator N40.

[Problem that the invention seeks to solve]

In the conventional manufacturing method described above, if you look at each step individually, there is no particular difficulty since you can use well-known processes in semiconductor technology. If even one defect occurs in a single pixel, the display panel becomes defective, so the manufacturing yield drops sharply as the number of pixels increases to make the display panel more dense and larger. There are some problems. Especially in the series of steps mentioned above, 4
Separate photomasks (Old to M4) are required, and each time a photoetching process is performed using them, a large photomask measuring several tens of square meters on a side must be accurately aligned. As is well known, the manufacturing process of integrated circuits also uses a large photomask, which is likely to cause defects in the element part. Even if a wafer contains integrated circuits and some defects occur within the wafer, the defective integrated circuit chips can be discarded and only healthy integrated circuits can be used. In the case of large display panels, even if there is no need to miniaturize the pattern in the case of integrated circuits, if even one defect occurs in more than one pixel contained in the panel, it will become defective. , manufacturing process control becomes much more difficult than for integrated circuits, and manufacturing yield problems become more acute. The same applies to defects caused by dust and the like in each process as well as photomask alignment.

In order to solve this problem, it has been proposed that thin-film semiconductor elements that are particularly prone to defects be fabricated in double or triple layers in each pixel, and that semiconductor elements with defects be separated by trimming or other means. ing. Although such means are probably necessary and have some effect, they require considerable effort and equipment to separate defective semiconductor elements, and the effective area of the display is reduced by the amount of spare semiconductor elements incorporated. Therefore, the aforementioned decrease in the aperture ratio becomes inevitable.

As described above, although there is no problem in principle in increasing the size or display density of active matrix liquid crystal display panels, the question is how to manufacture them economically without reducing production yield and quality. This can be said to be a very big problem.

In recognition of this problem, the present invention aims to provide a method suitable for manufacturing a large-screen, high-quality active matrix liquid crystal display panel by simplifying the manufacturing process.

[Means for solving problems]

According to the present invention, the above-mentioned object is achieved by a method for manufacturing a liquid crystal display panel, which includes sequentially depositing a conductive film for an electric bridge and a semiconductor film for a semiconductor element on a substrate, and then forming a portion that will become a semiconductor element. A semiconductor element layer forming process in which a semiconductor element layer is formed on a conductive film by selectively photo-etching only the semiconductor film, and a pixel electrode is formed by photo-etching the conductive film while using the semiconductor element layer as a part of a mask. an electrode forming step in which a scanning electrode is formed and a groove is formed on the underside of the semiconductor element layer by digging into the conductive film between the semiconductor element layer and the substrate from a predetermined side surface in the periphery of each semiconductor element layer; and a contact layer that covers at least a part of the side surface of the semiconductor element layer on which the groove is provided and electrically connects between the top surface of the semiconductor element layer and a predetermined electrode after depositing a metal layer. This is achieved by including a step of forming a connection layer by photo-etching.

[Effect]

In the semiconductor element layer forming process of the above-mentioned configuration, instead of photo-etching a conductive film to form pixel electrodes and scanning electrodes and then depositing a semiconductor film, as in the conventional method, a conductive film and a conductive film are formed from the beginning. After both semiconductor films are sequentially deposited, a semiconductor element layer is first formed in a first photoetching step. This first photoetching process is selective in the sense that it removes the semiconductor film leaving only the part that will become the semiconductor element, and it is also selective in the sense that it only photoetches the semiconductor film while leaving the conductive film intact. be.

As a result, a semiconductor element layer is formed on the conductive film deposited on the entire surface of the substrate, and a pixel electrode and a scanning electrode are formed in the second photoetching process in the next TSI forming process. do.

At this time, a mask layer that is different from the previous photoetching process is naturally required, but in the area where the semiconductor element layer has already been formed, a part of the periphery of the semiconductor element layer is used as a mask layer, so the semiconductor element layer is removed. There is no need for photomask alignment between the element layer and the conductive film serving as the pixel electrode or scanning electrode located below the element layer. Comparing this with the conventional method of forming a semiconductor element layer after forming pixel electrodes and scanning electrodes, it is possible that the semiconductor element layer is formed in a place that is not an electrode due to misalignment of the photomask, or that the pixel electrode and scanning electrode are There is no possibility that the semiconductor element layer is formed so as to be short-circuited, thereby causing defects due to disconnection or short-circuiting of the semiconductor element. Therefore, in the second photoetching step of the present invention, the accuracy of photomask alignment is much easier than in the past, and the pattern alignment between the semiconductor element layer and the underlying conductive film or electrode is perfect, reducing the probability of defect occurrence. Decrease.

Furthermore, in this electrode forming step of the present invention, in addition to forming the pixel electrode and the scanning electrode as described above, the underlying conductive film is slightly excavated from the side surface at a predetermined portion in the periphery of each semiconductor element layer. A groove is formed on the lower side of the semiconductor element layer. The depth of this groove is up to several microns, usually 2~
The gap formed by this groove can hold a display voltage of about several volts, which is normally applied between the pixel electrode and the scanning electrode. Therefore, according to the present invention, the step of depositing an insulating film and the step of forming an insulating layer by photo-etching it in the prior art can be completely omitted. Of course, it is not necessary to add another mask layer for digging this groove, and the semiconductor element layer itself serves as a mask layer for digging, so the problem of photomask misalignment may occur. The grooves can also be dug during the second photoetching process or in the same process following the second photoetching process.

The connection layer forming process in the present invention is similar to the conventional process, in which a metal layer is deposited and then a third photoetching process is performed to form the connection layer. A portion is left that covers at least a portion of the side surface of the semiconductor element layer in which the groove was dug in the previous step. As a result, there is always a gap formed by the groove between the connection layer and the conductive film under the semiconductor element layer, and the display voltage that may be applied between the pixel electrode and the scanning electrode is borne by this gap.

As can be seen from the above, the photoetching process of the present invention requires only three steps instead of one in the past, and the second step, which is the key point in photomask alignment of the semiconductor element layer and the electrode layer, which conventionally had many problems. Other advantages of the present invention and advantageous embodiments thereof are described in the following sections.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be specifically described with reference to the drawings, assuming that the semiconductor element is a pair of diodes connected in antiparallel, and the diodes are made of thin film amorphous silicon. FIG. 1 shows the process of the simplest and basic embodiment of the present invention in which no light-shielding film is included in the semiconductor element layer 10, and the illustrated cross section is of the diode 11 shown in FIG. This corresponds to a cross section taken along line X-X of the portion. In addition, in the figures after Figure 1, the parts corresponding to the parts shown in the previous Figures 6 and 7 are given the same reference numerals, and duplicate explanations will be omitted except for the main parts. .

FIG. 1 (al and (bl) show the state during the semiconductor element layer forming process in the present invention. As shown in FIG.
After a transparent conductive M42 such as ITO is deposited on the top to a thickness of about 700 nm by sputtering or the like, an amorphous silicon film with a pin configuration, for example, is deposited as the semiconductor film 3 by plasma CVD to a thickness of about 0.5 nm. Covered by law. The same publication) shows the photoetching process, in which the semiconductor film 3 is selectively etched using the first mask layer Ma by a plasma etching method using SF6 or the like.

A semiconductor element layer 10 is formed on the conductive film 2. The location of this formation is the location of the diodes 11, 12 in FIG.

Figures (C) to (dl) show the state during the electrode formation process in the present invention. Figure (C) shows the state where the second mask layer Mb for the second photoetching process has been created by photoprocessing. The figure (cl) shows a cross section of the semiconductor element layer 10 taken in a direction perpendicular to the plane of the paper. The semiconductor element layer 10 is used as a mask layer for the left and right sides of the rectangular semiconductor element layer 10 as shown in the same figure (C1), but the front and rear sides of the figure are as shown in the same figure (cl). is covered by the second mask JIMb, so
On the front and side surfaces, the conductive film 2 is not etched; the ITO conductive film 2 is wet-etched using a mixed aqueous solution of ferric chloride and hydrochloric acid;
After etching for about 2 minutes, a state as shown in FIG. 2D is obtained, and the pixel electrode 20 and the scanning electrode 30 are thereby formed from the conductive film 2. If the etching is continued for about one more minute, the conductive film 2 will be further over-etched, resulting in the state shown in FIG. A groove U is dug from the side surface. A top plan view of the diagram in this state can be seen for diode 11 in FIG. At this time, a groove will be dug under the mask layer Mb on the pixel electrode 20 side as well, but the pattern of the mask layer Mb should be designed in consideration of this digging depth. For example, the digging depth is 2
~3n is sufficient, and this depth should be adjusted (in order to manage it,
It is also possible to use a slightly thinner etching liquid for groove digging and to perform the groove digging etching shown in FIG.

Figure 1 (f) shows the state during the connection layer forming step in the present invention. +9) in the figure shows the state after the metal layer 5 has been deposited, and this metal layer 5 is made of, for example, aluminum with a film thickness of IP.
It is deposited by a sputtering method to a thickness of about a.

Next, as shown in FIG. A gap due to the groove U remains between the connecting layer 50 and the scanning electrode 30 on the lower side of the semiconductor element layer 10.
It serves to bear the display voltage applied between the pixel electrode 20 and the scanning electrode 30, which have the same potential as zero. Note that the connection layer 50 comes into direct contact with the left side surface of the semiconductor element layer 10 in the drawing, but since the semiconductor element 1110 has a fairly high specific resistance, this impairs the function of the semiconductor element layer as a semiconductor element. It won't happen.

The state shown in FIG. 1 (fl) is shown in a plan view in FIG. In the illustrated example, the diode 12 is provided on the scan electrode 30, so the scan electrode 30 has a bulge 30a, and the corresponding portion of the pixel electrode 20 has a notch 20a. However, as can be seen from a comparison with FIG. 6, the number of these four bulges and cutouts can be much smaller than in the conventional case.Furthermore, in the present invention, the left and right positions of the diodes 11 and 12 are different from the conventional one. It is advantageous to do the opposite.

As can be seen from a comparison with FIG. 6, in the present invention, the area conventionally reserved for the insulating layer 40 can be omitted, and the semiconductor element layers of the diodes 11 and 12 protrude beyond the electrode baths. Therefore, by omitting the wasted area and increasing the effective area for the display where orientation 1] 120b is provided,
The aperture ratio can be improved by 10% or more compared to the conventional method.

3 and 4 show embodiments of the present invention in which a light-shielding film is included on one side and both sides of the semiconductor element N10, respectively. In both cases, the above-mentioned electrode forming step is performed on the first electrode The light-shielding film 3a or 3b shown in FIG. 0, which is divided into two steps: a formation process and a second electrode formation process, originally reduces the a-performance as a semiconductor element, especially its It is provided as necessary so that its function as a threshold element in switching operation does not change, but at the same time it can also serve as an electrode layer for the scanning electrode 30 or the connection layer 50. .

The embodiment shown in FIG. 3 includes a light-shielding film 3a as the lower electrode of the semiconductor element layer 10, and the light-shielding film 3a is formed, for example, before the semiconductor film is grown after the conductive film 2 is deposited. A Cr layer of less than 0.1 μm is deposited by sputtering. The semiconductor element layer forming process in this case may be the same as in the previous embodiment, and thereby the semiconductor element layer 1o is formed on the light shield 1113a. FIG. 2 ta+ and (al) show the state during the subsequent first electrode formation step, in which the semiconductor element layer lO is used as a mask layer.
When the light-shielding film itself is a Cr layer, which fulfills its role,
For this etching, plasma etching in a mixed gas of chlorofluorocarbons and oxygen is preferably used.
Al state, that is, the light shielding film 3a is etched to the same shape as the semiconductor element 1110. Further, the light-shielding film 3a is wet-etched using a mixed aqueous solution of ceric ammonium nitrate and perchloric acid, and a groove U is dug from the periphery of the semiconductor element layer to form the state shown in FIG. Figure 1) shows the state after the second electrode formation process, in which the light shielding layer 113a etched in the previous process and the second mask layer M
b is used as a mask layer, and the pixel electrode 2 is etched by etching the conductive film 2 using the same etching solution as in the previous embodiment.
0 and the scanning electrode 30 are formed by patterning. The same figure (C
) may be exactly the same as in the previous embodiment, and a gap formed by the groove U is interposed as an insulating gap between the connection layer 50 formed thereby, the light shielding film 3a, and the scanning electrode 3o. Become.

FIG. 3 shows an embodiment in which light shielding films 3b and 3a are provided as lower electrode layers on the semiconductor element layer 10.
The same figure (al, (bl and (01) respectively show the state after the first electrode formation step, the second electrode formation step and the connection layer formation step. In this example, the semiconductor element layer formation The first mask layer used in the process is left in place, and the upper light shield 1!3b is etched and dug simultaneously with the lower light shield 113m during the first electrode formation process, except that it is similar to the previous implementation. Since it is exactly the same as the example, detailed explanation will be omitted to avoid complexity.

Although FIG. 4 shows a somewhat special embodiment, the semiconductor element layer 10
This structure adopts a structure in which the connection layer 50 is finally stored under the connection layer 50. FIG. 1al shows the state of the diode portion after the connection layer forming process according to the present invention is taken along the line XX in FIG. The front and rear sides are made slightly larger than the final dimensions. This situation can be seen in the same figure (al). After this, the connection layer 5o
By using this as a kind of mask layer and etching the portion of the semiconductor element JILLO protruding from the connection layer 50 using the same etching solution used in the previous semiconductor element layer formation process, the semiconductor element layer is etched as shown in FIG. The outer contour is reduced to within the range of the connection layer 50, so that it is completely hidden under the connection layer 50 when viewed from the top, as shown in the plan view of FIG. As can be easily seen, both diodes 11 and 12 are shielded from light from the upper surface by the connection layer 50 and are covered by it, so that they are almost completely protected from the abrasive material during the so-called rubbing process on the alignment film 20b. Ru.

As is well known, the orientation Wi420b is the pixel electrode 2
It is necessary to specify the direction in which the liquid crystal molecules are aligned by rubbing the surface with a rubbing material such as nylon cloth, for example, as shown by the arrow R in the figure. During this rubbing process, there is a risk that the diodes 11 and 12, which protrude from the substrate surface by about 2μ, may be damaged.In this embodiment, the connection layer 5° also serves as a protective layer, so there is a risk that the diodes may be damaged. can be eliminated. Further, as described above, the portion where the diode is provided is a portion that does not originally contribute to display, and by reducing the translucency of this portion by using the connection ratso, the contrast of the display can be improved even slightly.

In addition to the embodiments described above, the present invention can be implemented in various ways. For example, the photoetching method described in the embodiments is suitable for the specific materials illustrated, but as a semiconductor film. Polysilicon is used instead of amorphous silicon, tin oxide is used for the conductive film, Ti+ old, Mo, etc. are used for the light shielding film,
Cr as a metal layer.

When different materials are used, such as T++ NL Mo or a double layer of Cr and aluminum, the photoetching method, etching solution, etc. should be selected as appropriate to suit each material.

〔Effect of the invention〕

As explained above, by using the above-described semiconductor element layer formation process, electrode formation process, and connection layer formation process in combination as a manufacturing method for an active matrix type liquid crystal display panel, the number of photoetching processes can be reduced compared to the conventional technology. In addition to simplifying the manufacturing method,
Conventionally, the problem of misalignment in photomask alignment can be eliminated by aligning the semiconductor element layer pattern with the underlying pixel electrode or scanning electrode pattern, which was a key point in photomask alignment, using so-called self-lining. The probability of occurrence of defects such as disconnections and short circuits in semiconductor elements incorporated into display panels can be significantly reduced compared to the conventional method, and the manufacturing yield of display panels can be improved. Furthermore, since it is not necessary to provide an insulating layer compared to the conventional method, the problem of defects is eliminated, and the aperture ratio of the display panel can be improved by eliminating the extra area required for this.

These features of the method of the present invention are expected to exhibit their true value more and more as liquid crystal display panels continue to have larger areas and display densities.

[Brief explanation of drawings]

Figures 1 to 5 relate to the present invention, and Figure 1 is a semiconductor element section showing the state at each step of the simplest and basic embodiment of the method for manufacturing an active matrix liquid crystal display panel according to the present invention. 2 and 3 are cross-sectional views of a similar semiconductor element portion showing an embodiment in which a light-shielding film is provided on one side and both sides of the semiconductor element layer, respectively. A sectional view and a plan view of the semiconductor element portion, and FIG. 5 is a plan view of four pixels of a display panel manufactured by the method of the embodiment shown in FIGS. 1 to 3. Figures 6 and 7 relate to the prior art; Figure 6 is a plan view of one pixel of a display panel manufactured by the conventional method, and Figure 7 is a cross-section of the semiconductor element portion at each step in the conventional method. In figure 0, 1: substrate, 2: conductive film, 3: semiconductor film, 4: insulating film,
5: metal layer, 10: semiconductor element layer, 11.12: anti-parallel connected diode as semiconductor element, 20: pixel electrode,
20a: notch of pixel electrode, 20b: alignment film, 30i scan electrode, 30a: bulge of scan electrode, 40: vA green layer,
50: connection layer, Ma: first mask layer, Mb = second mask layer, Hc: third mask layer, M1 to M4j mask layer for conventional method, R direction of nilaping process, U: digging groove Or a gap. Figure 2 Figure 4 Figure 6

Claims (1)

[Scope of Claims] 1) A method for manufacturing an active matrix liquid crystal display panel in which a thin film semiconductor element for display driving is incorporated between each pixel electrode in a substrate of the display panel and a scanning electrode that applies a display voltage to the pixel electrode. Then, a conductive film for an electrode and a semiconductor film for a semiconductor element are sequentially deposited on a substrate, and only the semiconductor film is selectively photoetched, leaving the part that will become the semiconductor element, to form a layer on the conductive film. A semiconductor element layer forming process of forming a semiconductor element layer, and a conductive film is photoetched using the semiconductor element layer as a part of a mask to form a pixel electrode and a scanning electrode, and a predetermined area in the periphery of each semiconductor element layer is formed. an electrode forming step in which a conductive film between the semiconductor element layer and the substrate is dug from the side surface to form a groove on the lower side of the semiconductor element layer, and a metal layer is deposited and the groove in the semiconductor element layer is an active matrix method comprising the step of forming a connection layer by photoetching, covering at least a part of the side surface provided with the semiconductor element layer and electrically connecting between the top surface of the semiconductor element layer and a predetermined electrode; A method for manufacturing a liquid crystal display panel. 2) In the method recited in claim 1, the semiconductor element layer includes a conductive light-shielding film, and the electrode forming step is performed by connecting the semiconductor element layer and the conductive film from a predetermined side surface in the periphery of the semiconductor element layer. A first electrode forming step in which a groove is formed on the lower side of the semiconductor element layer by digging through the light-shielding film between them, and a pixel electrode and a scanning electrode are formed by photo-etching the conductive film, and the periphery of the semiconductor element layer is formed. an active matrix type liquid crystal characterized by comprising a second electrode forming step of digging into the conductive film between the semiconductor element layer and the substrate from the side surface of the inside to form a groove on the lower side of the semiconductor element layer. A method of manufacturing a display panel.