JPS6152018A - switched capacitor circuit - Google Patents

Abstract

PURPOSE:To improve the operating accuracy by connecting the 1st and 2nd capacitors to a virtual common input terminal of an operational amplifier and using an analog switch so as to switch a common and an input or output terminal of each capacitor. CONSTITUTION:An input capacitor 11 and a feedback capacitor 12 are connected to the virtual common input terminal of the operational amplifier 18. The analog switches 13, 14 switch the capacitor 11 for the input and the ground. The analog switches 16, 17 switch the capacitor 12 between the output and common. The capacitor 11 is connected to the input the capacitor 12 is connected to the common and the switch 15 is turned on at first. Then the switch 15 is turned off, the capacitor 12 is connected to the output and the capacitor 11 is connected to cmmon. The operation accuracy is improved by eliminating the effect of the clock field-through.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a switched capacitor circuit that is composed of a capacitor, an analog switch, and an operational amplifier, and performs signal calculation by charging and discharging the charge accumulated in each capacitor. This is related to high precision.

[Background of the invention]

As an example of a one-stage analog shift register configured with a switched capacitor circuit, for example, ``Two-dimensional switched register for image processing'' by Nishiyo et al. There is a method of implanting capacitor filters.

The circuit shown therein is shown in FIG. In the same figure,
1 is an input capacitor, 2 is a reset capacitor, 3 is a feedback capacitor, 4 to 9 are analog switches using, for example, 0MO3 transistors, and 10 is an operational amplifier.

Analog switches 4 to 9 are time chart 1 in Figure 2.
A control clock φ0. The input signal driven by φ2 and stored in the form of charge in the input capacitor 1 is transferred to the feedback capacitor 3, delayed by one time slot, and outputted to the operational amplifier 10. When performing a general delay operation, the capacitance values of capacitors 1 to 3 are set to be equal.

Here, a phenomenon called clock feedthrough, which is a problem when operating such a switched capacitor circuit at high speed, will be explained. Clock field-through is a phenomenon in which the control clock leaks into signal components through the parasitic capacitance of analog switches, etc. When MoS transistors are used as analog switches, we investigated this including the channel charge of the transistors. As an example,
1981, IEICE General Conference National Conference Proceedings 4
There is a ``Basic Study on the Effects of Glock Field Through in Switched Capacitor Circuits'' by Izawa et al. 79.

According to the results of this study, the channel charges of the analog switches 4 and 9 flowed into the input capacitor 1 and the reset capacitor 2, respectively, causing a decrease in the calculation accuracy of the delay circuit. The reason for this is that the electricity on the input side of input capacitor 1 and the voltage of the reset capacitor change with the input voltage Vt and output electricity v0 when φ2 is on, as shown in Figure 2. there were.

[Purpose of the invention]

An object of the present invention is to provide a switched capacitor circuit in which the influence of lock feedthrough is eliminated or reduced.

[Summary of the invention]

The present invention focuses on the fact that for analog switches that operate at a constant potential, such as ground level, the clock feedthrough described above does not change the capacitance, but can be regarded as a constant offset. The switch is operated in such a way that the total charge at the high-impedance node of the circuit is always conserved between time slots.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIGS. 3 and 4.

83(a), 11 is an input capacitor, 12 is a feedback capacitor, and 13 to 17 are analog switches using, for example, MOS transistors.

18 is an operational amplifier. Next, the operation of the analog switch will be explained assuming that an O5 transistor is used for N. In FIG. 3(a), the clock φ1. is H (=V6D)
to L (=vJlj), that is, when transitioning from on to off, the output voltage of the operational amplifier 18 becomes a value obtained by adding the clock field through of the switch 15 (a constant value) to its offset voltage. Therefore, these will be collectively referred to as offsets. Needless to say, this potential does not depend on the input voltage V. At this time, the input capacitor 11 stores a charge based on the difference between the input voltage and the offset voltage, and the feedback capacitor 12 stores a charge corresponding to the offset voltage. That will happen.

Next, as shown in Figure 3(b), switch the analog switch 16°17.
is switched, and the feedback capacitor 12 becomes operational amplifier rfi.
12 output terminals. As a result, operational amplifier 1
At the output terminal of 2, its own input offset voltage is canceled and a voltage close to ground level is generated.

Thereafter, the analog switches 13 and 14 are switched, and the charge accumulated in the input capacitor 11 is transferred to the feedback capacitor 12. If the capacitance values of the capacitors are equal, the clock field through of the analog switch 15 is added to the input voltage. (a certain value) is generated at the output terminal. What should be noted is that analog switch 13~
The clock field through portion of 14 degrees 16 to 17 does not affect this output voltage. In particular, when the analog switch 13 connected to the input is turned off first, the feedthrough depends on the input voltage, so the result is as if the capacitance of the input capacitor 11 has effectively changed. Therefore, by switching the switches according to the procedure described here, it is possible to realize a switched capacitor circuit in which the deterioration in calculation accuracy is extremely small.

FIG. 4 shows the above switch switching procedure using time chart 1. The important thing here is φ4
2. φ11 is turned off before φ1° is turned off. As a result, the total amount of charge at the inverting input terminal (virtual ground) of the operational amplifier 18 is held at a constant value regardless of the input voltage V. Therefore, the timing at which φ□ and φ11 are turned off does not necessarily have to be as shown in FIG. 4. However, in this case, since the time during which feedback is not applied becomes long, consideration must be given to prevent the voltage at the 1-inverting input terminal from deviating significantly from the ground level.

In the above explanation, an NHO2 transistor is used as an analog switch, but it is clear that similar effects can be obtained using PM (JS or CMO3).

〔Effect of the invention〕

As described above, according to the present invention, it is possible to eliminate or reduce the influence of tallock buy-through, which is a problem in switched capacitor circuits that perform high-speed operation, and to improve the computational complexity. It becomes possible.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of a conventional example, FIG. 2 is a tie-11 chart explaining its operation, FIG. 3 is a circuit diagram showing the configuration and operation of an embodiment of the present invention, and FIG. 4 is a circuit diagram showing the configuration and operation of an embodiment of the present invention. It is a time chart for explaining the operation. DESCRIPTION OF SYMBOLS 1... Input capacitor, 2... Capacitor for reset, 3... Capacitor for feedback, 4-9... Analog switch, 10... Operational amplifier, 11... Input capacitor. 12... Feedback capacitor, 13-17... Analog Figure 1 Figure 2 Figure 4 Foil 3 Figure (a-) (b-n (C)

Claims (1)

[Claims] A switched capacitor circuit consisting of a capacitor, an analog switch, and an operational amplifier, wherein the first and second capacitors are connected to the virtual ground input terminal of the operational amplifier, and the remaining terminal of the first capacitor is connected to the input terminal. and a second analog switch that selectively connects the remaining terminal of the second capacitor to the output terminal of the operational amplifier and the ground, and a virtual ground of the operational amplifier. It has a third analog switch that connects the input terminal and the output terminal, and in the first time slot, the first analog switch is set to the input side, the second analog switch is set to the ground side, and the third analog switch is turned on. means for connecting the second analog switch to the output terminal of the operational amplifier after turning off the third analog switch in the second time slot; and means for connecting the first analog switch to the ground side. A switched capacitor circuit comprising means for connecting.