JPS61119056A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS61119056A JPS61119056A JP24101384A JP24101384A JPS61119056A JP S61119056 A JPS61119056 A JP S61119056A JP 24101384 A JP24101384 A JP 24101384A JP 24101384 A JP24101384 A JP 24101384A JP S61119056 A JPS61119056 A JP S61119056A
- Authority
- JP
- Japan
- Prior art keywords
- silicon
- semiconductor substrate
- silicon semiconductor
- etching
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
(技術分野)
本発明は、シリコン半導体基板上に絶縁分離溝を有する
半導体装置の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a method of manufacturing a semiconductor device having an isolation trench on a silicon semiconductor substrate.
(従来技術)
従来シリコン半導体基板に分離溝を形成するには、シリ
コン半導体基板上に絶縁膜を形成し、該絶縁膜に開孔部
を形成し、該絶縁膜をマスクとして、該開孔部の前記シ
リコン半導体基板を異方性喰刻法により喰刻し、分離溝
を形成するが、この方法によると前記シリコン半導体基
板表面と該分l@溝の境界部が僑直であるために、該分
#オ形成後の熱酸化工程において核境界部に応力がかか
り欠陥の発生等の素子特性上好ましくな込事が発生する
。このため分m溝と素子の距離が大きくなり、素子の高
集積化には障害となる。(Prior art) Conventionally, in order to form an isolation trench in a silicon semiconductor substrate, an insulating film is formed on the silicon semiconductor substrate, an opening is formed in the insulating film, and the opening is formed using the insulating film as a mask. The silicon semiconductor substrate is etched by an anisotropic etching method to form a separation groove, but according to this method, the boundary between the silicon semiconductor substrate surface and the corresponding groove is straight; In the thermal oxidation step after the #O formation, stress is applied to the nuclear boundary portion, resulting in undesirable problems in terms of device characteristics such as generation of defects. Therefore, the distance between the m-groove and the element becomes large, which becomes an obstacle to high integration of the element.
(発明の目的)
本発明は上記欠点を除去し、シリコン半導体基板表面と
分離溝の酸化二組における応力の低減化を可能とする半
導体装置の製造方法を提供するものである。(Object of the Invention) The present invention provides a method for manufacturing a semiconductor device that eliminates the above-mentioned drawbacks and makes it possible to reduce the stress in the oxidized two sets of the silicon semiconductor substrate surface and the isolation trench.
(発明の構成)
本発明は、シリコン半導体基板上に窒化珪素膜を形成す
る工程と、該窒化珪素膜を選択的に喰刻する工程と該窒
化珪素膜の喰創部の前記シリコ/半導体基板を選択的に
酸化し、二酸化珪素膜を形成する工程と該二酸化珪素膜
を除去する工程と、前記窒化珪素膜をマスクとして前記
シリコン半導体基板を異方性喰刻法により、喰刻し絶縁
分離溝を形成する工程とを有することを特徴とする半導
体装置の製造方法である。(Structure of the Invention) The present invention includes a step of forming a silicon nitride film on a silicon semiconductor substrate, a step of selectively etching the silicon nitride film, and a step of etching the silicon nitride film on the silicon/semiconductor substrate. A step of selectively oxidizing to form a silicon dioxide film, a step of removing the silicon dioxide film, and etching the silicon semiconductor substrate by an anisotropic etching method using the silicon nitride film as a mask to form an insulating isolation groove. 1. A method of manufacturing a semiconductor device, comprising: a step of forming a semiconductor device;
(発明の効果)
本発明によれば、熱酸化膜形成工程と、該熱酸化膜形成
工程によりシリコン半導体基板表面と分離溝の境界部分
く曲率を持たせることができ、該分離溝形成後の熱酸化
工程に前記境界部にかかる応力を低減化することが可能
となり、歪による素子特性の劣化欠陥の発生による素子
の不良を抑えることができるため、分*溝と素子の距離
を小さくでき高集積化が可能となる効果がある。(Effects of the Invention) According to the present invention, the thermal oxide film forming step and the thermal oxide film forming step can provide a curvature at the boundary between the silicon semiconductor substrate surface and the isolation trench, and It is possible to reduce the stress applied to the boundary part during the thermal oxidation process, and it is possible to suppress the deterioration of element characteristics due to strain and the occurrence of defects in the element, which allows the distance between the groove and the element to be reduced, resulting in higher height. This has the effect of enabling integration.
(実施例)
次に本発明の特徴をより良く理解するために1従来の方
法と本発明の方法について図面を用いて説明する。まず
、従来の方法について説明する。(Example) Next, in order to better understand the characteristics of the present invention, one conventional method and the method of the present invention will be explained using the drawings. First, a conventional method will be explained.
第1図(a)〜(d)は半導体装置の分離溝形成の従来
の喪遣方法の主な工程の断面図である。まず第1図(J
L) Kおhて、1はシリコン半導体基板である。FIGS. 1(a) to 1(d) are cross-sectional views illustrating the main steps of a conventional method for forming isolation trenches in semiconductor devices. First, Figure 1 (J
L) 1 is a silicon semiconductor substrate.
該シリコン牛導体基板上に二酸化珪素膜(又は窒化珪素
pa> zをcvD法gより 3oooX厚被Hし、写
真喰刻法によりパターンを形成する(第1図(b))。A silicon dioxide film (or silicon nitride pa>z) is coated on the silicon conductive substrate to a thickness of 300X using the CVD method, and a pattern is formed by photolithography (FIG. 1(b)).
しかる後、前記二酸化珪素膜2をマスクとして、前記シ
リコン半導体基板1を異方性喰刻法により3μmの深さ
に喰刻し分離溝を形成しく第1図(C))、前記二酸化
珪素膜を喰刻後前記シリコン半導体基板1を熱酸化法に
より、4000A厚酸化し@2の二酸化珪素膜3を形成
する(第1図(ψ)。Thereafter, using the silicon dioxide film 2 as a mask, the silicon semiconductor substrate 1 is etched to a depth of 3 μm by an anisotropic etching method to form a separation groove (FIG. 1C). After etching, the silicon semiconductor substrate 1 is oxidized to a thickness of 4000 Å by thermal oxidation to form a @2 silicon dioxide film 3 (FIG. 1 (ψ)).
このように従来の製造方法に従うと、前記シリコン半導
体基板1を熱酸化する際に前記分lli溝と前記シリコ
ン半導体基板表面の境界部に応力がかかり欠陥が発生す
るという欠点を有している。次に本発明を実施例により
説明する。As described above, when the conventional manufacturing method is followed, there is a drawback that when the silicon semiconductor substrate 1 is thermally oxidized, stress is applied to the boundary between the ILI groove and the surface of the silicon semiconductor substrate, causing defects. Next, the present invention will be explained by examples.
第2図(JL)〜(f)は本発明の詳細な説明するため
の半導体装置の1fri図である。第2図(&)におい
て11はシリコン半導体基板であり、該シリコン半導体
基板11上に窒化珪素膜12をCVD法くより、100
OA〜5000A軍に被着し、写真喰刻法においてパタ
ーンt−形成し、eI記シリコン半導体基板11の一部
を露出させる(第2図φ))。しかる後熱酸化法により
、前記シリコン半導体基板11を選択的に3化し1oo
oX〜20000X厚の二酸化珪素膜13を形成しく第
2図(C) ) 、該二酸化珪素膜13を等方性喰刻法
により除去する(第2図(Φ)。ついで前記窒化珪素膜
12をマスクとして、異方性喰刻法に訃(へて前記シリ
コン半導体基′Ji、11を:j!択的(で1μm〜6
μm 深ざ喰刻し、分離溝を形成しく第2図(e) )
、前記窒化珪′2讐12を喰刻後前記シリコン半導体
基板11を熱改化法により膜14を形成する(笥2LJ
(f))。FIGS. 2(JL) to 2(f) are first views of a semiconductor device for explaining the present invention in detail. In FIG. 2 (&), 11 is a silicon semiconductor substrate, and a silicon nitride film 12 is deposited on the silicon semiconductor substrate 11 by CVD method.
A layer of OA to 5000A is deposited, and a pattern T is formed by photolithography to expose a part of the silicon semiconductor substrate 11 (FIG. 2 φ)). Thereafter, the silicon semiconductor substrate 11 is selectively converted into 3 by thermal oxidation method.
A silicon dioxide film 13 having a thickness of 0X to 20,000X is formed (FIG. 2(C)), and the silicon dioxide film 13 is removed by an isotropic etching method (FIG. 2(Φ)).Then, the silicon nitride film 12 is As a mask, the silicon semiconductor substrate 'Ji, 11 is etched using an anisotropic etching method.
Figure 2 (e))
After etching the silicon nitride film 12, a film 14 is formed on the silicon semiconductor substrate 11 by a thermal modification method.
(f)).
以上説明したように本発明によれば、シリコン半導体1
1表面と分離溝の境界部は曲率を持っているため、該分
離溝形成後の熱酸化工程に該i−2が部にかかる応力が
、低減化てれ、歪による素子特性の劣化、欠陥の発生に
よる素子の不良が抑えられる。その結果、分離溝と素子
の距離を小さくでき、高集積化が可能となる。As explained above, according to the present invention, silicon semiconductor 1
Since the boundary between the first surface and the isolation trench has a curvature, the stress applied to the i-2 part during the thermal oxidation process after the isolation trench is formed is reduced, causing deterioration of device characteristics and defects due to strain. Element defects due to the occurrence of this can be suppressed. As a result, the distance between the isolation trench and the element can be reduced, making it possible to achieve high integration.
第1図(A)〜(d)は各々従来の製造方法を示す工種
、′[断面図、其2図(a)〜(f)は各々本発明実施
側による製造方法を示す工程順断面図である。
なお図において、1,11・・・・・・シリコ/半導体
基板、2・・・・・・CVD法による二酸化珪素膜、1
2・・・・・・窒素珪素膜、3.13.14・・・・・
・二酸化珪素膜。Figures 1 (A) to (d) are cross-sectional views showing the conventional manufacturing method, and Figures 2 (a) to (f) are process cross-sectional views showing the manufacturing method according to the present invention. It is. In the figure, 1, 11...Silicon/semiconductor substrate, 2...Silicon dioxide film by CVD method, 1
2... Nitrogen silicon film, 3.13.14...
・Silicon dioxide film.
Claims (1)
、該窒化珪素膜を選択的に喰刻する工程と、該窒化珪素
膜の喰刻部の前記シリコン半導体基板を選択的に酸化し
、二酸化珪素膜を形成する工程と、該二酸化珪素膜を除
去する工程と、前記窒化珪素膜をマスクとして前記シリ
コン半導体基板を異方性喰刻法により喰刻し、絶縁分離
溝を形成する工程とを有することを特徴とする半導体装
置の製造方法。A step of forming a silicon nitride film on a silicon semiconductor substrate, a step of selectively etching the silicon nitride film, and a step of selectively oxidizing the silicon semiconductor substrate in the etched portion of the silicon nitride film to form silicon dioxide. a step of forming a film, a step of removing the silicon dioxide film, and a step of etching the silicon semiconductor substrate by an anisotropic etching method using the silicon nitride film as a mask to form an insulating isolation groove. A method for manufacturing a semiconductor device, characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24101384A JPS61119056A (en) | 1984-11-15 | 1984-11-15 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24101384A JPS61119056A (en) | 1984-11-15 | 1984-11-15 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61119056A true JPS61119056A (en) | 1986-06-06 |
Family
ID=17068031
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24101384A Pending JPS61119056A (en) | 1984-11-15 | 1984-11-15 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61119056A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20020060816A (en) * | 2001-01-12 | 2002-07-19 | 동부전자 주식회사 | Method for forming trench of semiconductor element |
| US6469345B2 (en) | 2000-01-14 | 2002-10-22 | Denso Corporation | Semiconductor device and method for manufacturing the same |
| US6482701B1 (en) | 1999-08-04 | 2002-11-19 | Denso Corporation | Integrated gate bipolar transistor and method of manufacturing the same |
| US6521538B2 (en) | 2000-02-28 | 2003-02-18 | Denso Corporation | Method of forming a trench with a rounded bottom in a semiconductor device |
| US6864532B2 (en) | 2000-01-14 | 2005-03-08 | Denso Corporation | Semiconductor device and method for manufacturing the same |
-
1984
- 1984-11-15 JP JP24101384A patent/JPS61119056A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6482701B1 (en) | 1999-08-04 | 2002-11-19 | Denso Corporation | Integrated gate bipolar transistor and method of manufacturing the same |
| US6469345B2 (en) | 2000-01-14 | 2002-10-22 | Denso Corporation | Semiconductor device and method for manufacturing the same |
| US6864532B2 (en) | 2000-01-14 | 2005-03-08 | Denso Corporation | Semiconductor device and method for manufacturing the same |
| US7354829B2 (en) | 2000-01-14 | 2008-04-08 | Denso Corporation | Trench-gate transistor with ono gate dielectric and fabrication process therefor |
| US6521538B2 (en) | 2000-02-28 | 2003-02-18 | Denso Corporation | Method of forming a trench with a rounded bottom in a semiconductor device |
| KR20020060816A (en) * | 2001-01-12 | 2002-07-19 | 동부전자 주식회사 | Method for forming trench of semiconductor element |
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