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JPS592328A - Insulation type interface integrated circuit - Google Patents

Insulation type interface integrated circuit

Info

Publication number
JPS592328A
JPS592328A JP57110013A JP11001382A JPS592328A JP S592328 A JPS592328 A JP S592328A JP 57110013 A JP57110013 A JP 57110013A JP 11001382 A JP11001382 A JP 11001382A JP S592328 A JPS592328 A JP S592328A
Authority
JP
Japan
Prior art keywords
integrated circuit
insulated
control system
capacitor
insulation type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57110013A
Other languages
Japanese (ja)
Inventor
Masahiro Ueno
雅弘 上野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP57110013A priority Critical patent/JPS592328A/en
Publication of JPS592328A publication Critical patent/JPS592328A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
    • H01L2224/10125—Reinforcing structures
    • H01L2224/10126—Bump collar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48095—Kinked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)

Abstract

PURPOSE:To enable to obtain a low cost and a high mounting density by a method wherein an integrated circuit is operated at the potential of a system to be controlled by connecting to the control system side by an insulation type power source supply means and an insulation type digital signal transmitting means. CONSTITUTION:The integrated circuit (IC)1 operates by receiving the supply of the power source from the insulation type power source supply means composed of a transformer 2 and a rectifying circuit from the control system side. The transmission and reception of control signal between the control system side are performed via condensers 4 and 5, and then the control signal is insulated by the condensers 4 and 5. The signal transmitted and received is a digital signal. The IC1 can be operated at the same potential as that of the system to be controlled, and unnecessitates the insulation of complicated analog signal. Since this circuit has an insulation type wherein the power source and signal systems are independent, the control system and the circuit construction are simplified, and accordingly the realization of a low cost and high density mount is enabled.

Description

【発明の詳細な説明】 本発明は、互いに電気的絶縁を必要とする１ｅ号間を接
続する絶縁形インターフェース集積回路に係り、特に所
要部品数を最小限にした高密度実装に適した絶縁形イン
ターフェース集積回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an insulated interface integrated circuit that connects No. 1e devices that require electrical isolation from each other, and in particular an insulated interface integrated circuit that minimizes the number of required components and is suitable for high-density packaging. Relating to interface integrated circuits.

制御システムと被制御システムとの間を電気的に絶縁し
た上で信号を送受する必要性は多く、特にプロセス制御
においてこの傾向は顕著である。There is often a need to transmit and receive signals between a control system and a controlled system while electrically insulating them, and this tendency is particularly noticeable in process control.

この目的に対し、従来例えばアナログ入力インク−フェ
ースにおいてはフライイングギャバシタ等によりアナロ
グ信号を絶縁して入力した後、Ａｌ１）変換等を行なっ
ていた。−また絶縁アンプ等も使用されるが、トランス
、フォトカブラ等でアナログ信号を絶縁するため、部品
点数が多くかつ高精度が要求されるため高価にならざる
を得す、かつ実装密度も低い。For this purpose, conventionally, for example, in an analog input ink-face, an analog signal is input after being isolated by a flying gavascitor or the like, and then an Al1) conversion or the like is performed. - Isolation amplifiers are also used, but since analog signals are isolated using transformers, photo couplers, etc., they require a large number of parts and high precision, making them expensive and requiring low packaging density.

本発明の第１の目的は、安価でかつ高実装密度が得られ
る絶縁形インターノエース集ｆ★回路を得ることである
。A first object of the present invention is to obtain an insulated internoace integrated f* circuit that is inexpensive and can achieve high packaging density.

本発明の第２の目的は、１チツプ化した絶縁形インター
フェース集積回路を得ることである。A second object of the present invention is to obtain an isolated interface integrated circuit that is integrated into a single chip.

本発明の第１の特徴は、制御システム側と絶縁形電源供
給手段、絶縁形ディジタル信号伝送手段により接続し、
集積回路を被制御システム電位で動作させるようにした
ことである。The first feature of the present invention is that the control system is connected to the control system side by an isolated power supply means and an isolated digital signal transmission means,
The integrated circuit is operated at a controlled system potential.

本発明の第２の特徴は、前記絶縁形ディジタル信号伝送
手段を直列コンデンサにより構成したことである。A second feature of the present invention is that the isolated digital signal transmission means is composed of a series capacitor.

以下、本発明の第１の実施例を第１図により説明する。A first embodiment of the present invention will be described below with reference to FIG.

第１図において、１はＡ／Ｄ、Ｄ／Ａ変換等の信号処理
を行なう集積回路、２は電源供給用トランス、３は整流
回路、４．５は制御システム２００との間でディジタル
信号を送受する絶縁用コンデンサである。１００は被制
御システムとの接続端子である。In FIG. 1, 1 is an integrated circuit that performs signal processing such as A/D and D/A conversion, 2 is a power supply transformer, 3 is a rectifier circuit, and 4.5 is an integrated circuit that performs signal processing such as A/D and D/A conversion. This is an insulating capacitor for transmitting and receiving data. 100 is a connection terminal with the controlled system.

以上の構成にｋいて、集積回路（以下ＩＣと称す）１は
制御システム側からトランス２、整流回路３から成る絶
縁形電源供給手段によね電源の供給を受けて動作する。In the above configuration, the integrated circuit (hereinafter referred to as IC) 1 operates by receiving power from an isolated power supply means comprising a transformer 2 and a rectifier circuit 3 from the control system side.

該絶縁形電源供給手段を介してＩＣに必要とするクロッ
ク信号を供給することも可能である。制御システム側と
の制御信号の送受は、全てコンデンサ４．５を介して行
なわれ該制御信号は、該コンデンサ４．５により絶縁さ
れる。コンデンサ４．５を介して送受される信号はディ
ジタル信号である。It is also possible to supply the necessary clock signals to the IC via the isolated power supply means. All control signals are sent and received to and from the control system via a capacitor 4.5, and the control signals are insulated by the capacitor 4.5. The signals sent and received via capacitor 4.5 are digital signals.

本実施例によれば、ＩＣＩは制御システム側と、絶縁電
源供給手段及び絶縁形ディジタル信号処理手段により接
続されており、被制御システムと同電位で動作すること
が可能で、複雑なアナログ信号の絶縁が不要である。ま
た電源及び信号系が独立した絶縁形を有しているため、
制御方式、回路構成が簡単になり、安ｆｄｌｉでかつ高
密度実装を実現することがｉ丁内＠になる。According to this embodiment, the ICI is connected to the control system side by an isolated power supply means and an isolated digital signal processing means, and is capable of operating at the same potential as the controlled system, and is capable of handling complex analog signals. No insulation required. In addition, since the power supply and signal system are independent and isolated,
The control system and circuit configuration are simplified, and it is possible to achieve high-density mounting with low FDLI.

第２図は本発明の第２の実施例でＩＣの断面図を示す。FIG. 2 shows a cross-sectional view of an IC in a second embodiment of the invention.

第２図において２０はＩＣのパッケージ、２１はＩＣチ
ップ、２３はボンディングワイヤ、２２はリード、２４
はポンディングパッド、２５゜２６は酸化膜、リンガラ
スによる絶縁Ｉｎ、２７はポンディングパッド２４と対
向する１導′醒形を有する拡散層で、ポンディングパッ
ド２４と拡散層２７との間でコンデンサを形成する。２
８は拡散ｊ−２７を同−導′醒形を有する他の拡散層で
コンデンサ成極の端子を形成する。２９はアルミ配線で
ある。In FIG. 2, 20 is an IC package, 21 is an IC chip, 23 is a bonding wire, 22 is a lead, 24
25. 26 is an insulation film made of an oxide film and phosphor glass. 27 is a diffusion layer having a single-conductor opening facing the bonding pad 24. Between the bonding pad 24 and the diffusion layer 27 form a capacitor. 2
8 forms a terminal for capacitor polarization with another diffusion layer having the same conductive type as diffusion j-27. 29 is aluminum wiring.

以上の構成によれば、ＩＣチップ−Ｌに絶縁用コンデン
サを内蔵させ、極めて安価に絶縁形ディジタル信号伝送
手段を構成することができ、かつこのための外付部品を
必要とぜず更に高密度実装を可能にする。According to the above configuration, an insulating capacitor is built into the IC chip-L, and an insulated digital signal transmission means can be constructed at an extremely low cost, and there is no need for any external parts for this purpose, resulting in even higher density. enable implementation.

第３図は本発明の第３の実施例を示す図で、ＩＣをパッ
ケージングし、パッケージ内のリードを直視できる断面
図を示す。第３図において３０はＩＣチップ、２０はパ
ッケージ本体、３１はＩＣチップ３０に接続されたリー
ド、３２はリード３１に極めて接近して配置されたリー
ドで、リード３１．３２間でコンデンサを形成する。FIG. 3 is a diagram showing a third embodiment of the present invention, and shows a cross-sectional view in which an IC is packaged and the leads inside the package can be seen directly. In FIG. 3, 30 is an IC chip, 20 is a package body, 31 is a lead connected to the IC chip 30, and 32 is a lead placed very close to the lead 31, forming a capacitor between the leads 31 and 32. .

以上の構成によれば、コンデンサをパッケージ内で構成
しており、高耐圧コンデンサを容易に構成できる。これ
は第２の実施例が有する効果をそこなわずに実施できる
。According to the above configuration, the capacitor is configured within the package, and a high voltage capacitor can be easily configured. This can be implemented without sacrificing the effects of the second embodiment.

第４図は本発明の第４の実施例を示す図で、同図（イ）
は断面図、回は側面図、（ハ）は平面図を示す。FIG. 4 is a diagram showing a fourth embodiment of the present invention, and FIG.
1 shows a cross-sectional view, 1 shows a side view, and (c) shows a plan view.

第４図において３０はＩＣチップ、４０はボンディング
ワイヤ、４１はボンディングワイヤ４０に接続されたリ
ード、４２はリード４２に面対向配置したリードで、リ
ード４１．４２間でコンデンサを形成する。In FIG. 4, 30 is an IC chip, 40 is a bonding wire, 41 is a lead connected to the bonding wire 40, 42 is a lead disposed face-to-face with the lead 42, and a capacitor is formed between the leads 41 and 42.

本実施例によれば、コンデンサ成極を構成するリード４
１．４２の対向面積を大きくとることが可能となり、第
３の実施例の効果をそこなうことなく信号のカップリン
グを強化することが可能で、高信頼度の絶縁形ディジタ
ル信号伝送手段を得ることが可能になる。According to this embodiment, the lead 4 constituting the capacitor polarization
1. It is possible to increase the facing area of 42, and it is possible to strengthen signal coupling without impairing the effect of the third embodiment, and to obtain a highly reliable isolated digital signal transmission means. becomes possible.

以上述べた様に本発明によれば、集積回路は制御システ
ム画と、絶縁電源供給手段及び絶縁形ディジタル信号処
理手段により接続されており、被制御システムと同電位
で動作することが可能で、複雑なアナログ信号の絶縁が
不要である。また電源及び信号系が独立ＩＪ絶縁形を有
しているため、制御方式回路構成が簡単になり、安価で
かつ高密度実装を実現することが可能になる。As described above, according to the present invention, the integrated circuit is connected to the control system through the isolated power supply means and the isolated digital signal processing means, and can operate at the same potential as the controlled system. No need for complex analog signal isolation. Furthermore, since the power supply and signal systems have independent IJ isolation type, the control system circuit configuration is simplified, and it is possible to realize inexpensive and high-density packaging.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の第１の実施例を示す図、第２図は本発
明の第２の実施例を示す図、第３図は本発明の第３の実
施列を示す図、第４図は本発明の第４の実施例を示す図
である。 １・・・集積回路、２・・・電源供給用トランス、３・
・・整６１　口 第２の 茅４ （イ） ０ （ハ） ２ ６口） 々 １FIG. 1 shows a first embodiment of the present invention, FIG. 2 shows a second embodiment of the invention, FIG. 3 shows a third embodiment of the invention, and FIG. 4 shows a third embodiment of the invention. The figure shows a fourth embodiment of the present invention. 1... Integrated circuit, 2... Power supply transformer, 3.
...Adjustment 61 mouth 2nd grass 4 (a) 0 (c) 2 6 mouth) 1

Claims (1)

【特許請求の範囲】 １、制御システム及び被制御システムとを接続する絶縁
型インターフェース集積回路において、該制御システム
側の電源と絶縁された絶縁形電源供給手段と該制御シス
テム側と絶縁された絶縁形ディジタル信号伝送手段とを
有し、これらを介して上記制御システムと接続すること
を特徴とする絶縁形インターフェース集積回路。 ２、特許請求の範囲第１項において、上記絶縁形ディジ
タル信号伝送手段を直列コンデンサにより形成すること
を特徴とする絶縁形インターフェース集積回路。 ３、特許請求の範囲第２項において、該集積回路のボン
デイングパッドヲ前記コンデンサの１電極とすることを
特徴とする絶縁形インターフェース集積回路。 ４、特許請求の範囲第２項において、該集積回路のパッ
ケージのリードを前日己コンデンサの１゛−極としたこ
とを特徴とする絶縁形インターフェース集積回路。 ５、特許請求の範囲第４頃において、該コンデンサの電
極を同一面上に隣接配置したリードにより形成すること
を特徴とする絶縁形インターフェース集積回路。 ６、特許請求の範囲第４項において、該コンデンサの電
極を面対向配置したリードにより形成することを特徴と
する絶縁形インターフェース東＋★回路。[Scope of Claims] 1. In an insulated interface integrated circuit that connects a control system and a controlled system, an insulated power supply means that is insulated from a power supply on the control system side and an insulated power supply means that is insulated from the control system side. 1. An isolated interface integrated circuit characterized in that it has a digital signal transmission means and is connected to the control system via these means. 2. An insulated interface integrated circuit according to claim 1, wherein the insulated digital signal transmission means is formed by a series capacitor. 3. An insulated interface integrated circuit according to claim 2, wherein a bonding pad of the integrated circuit is one electrode of the capacitor. 4. An insulated interface integrated circuit according to claim 2, characterized in that the lead of the package of the integrated circuit is the 1-pole of a capacitor. 5. An insulated interface integrated circuit according to claim 4, characterized in that the electrodes of the capacitor are formed by leads arranged adjacently on the same plane. 6. The insulated interface Higashi+★ circuit according to claim 4, characterized in that the electrodes of the capacitor are formed by leads arranged face-to-face.
JP57110013A 1982-06-28 1982-06-28 Insulation type interface integrated circuit Pending JPS592328A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57110013A JPS592328A (en) 1982-06-28 1982-06-28 Insulation type interface integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57110013A JPS592328A (en) 1982-06-28 1982-06-28 Insulation type interface integrated circuit

Publications (1)

Publication Number Publication Date
JPS592328A true JPS592328A (en) 1984-01-07

Family

ID=14524900

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57110013A Pending JPS592328A (en) 1982-06-28 1982-06-28 Insulation type interface integrated circuit

Country Status (1)

Country Link
JP (1) JPS592328A (en)

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