JPS59218691A - Prefetching system - Google Patents

Abstract

PURPOSE:To ensure an effective prefetching operation with an operand access accompanied with the execution of instruction of a central processor when the data on the block succeeding to the operand data needed for a buffer storage does not exists. CONSTITUTION:A signal MV showing an operand access is equal to a move instruction is transmitted from an operation part 1 and set to a latch MVl to start a prefetch control circuit 6. Thus the circuit 6 transfers the data corresponding to the operand address shown by a memory address register AR2 to the operation part. Then the circuit 6 controls a selector 4 to fetch the result of a +1 adder in order to prefetch the next data block. Then the second retrieval is carried out to check whether or not the block of the corresponding address exists in a buffer storage 7. If this block does not exist, a prefetch address is sent to an address bus 11 to transfer data for prefetching. In such a way, the control is performed to transfer automatically the data block to the storage 7 from a main memory. Thus the hit factor to the storage 7 is improved in a continuous operand access mode related to the corresponding instruction.

Description

Detailed Description of the Invention (al) Technical Field of the Invention In a data processing system having a two-layer memory system of a main storage device and a buffer storage, "1. The present invention relates to a brief fetch method for transferring data from main storage to buffer storage when the data does not exist.

(bl Technology background) As data processing devices have become larger and faster in recent years, it has become necessary to speed up the access time to the main memory.
One way to achieve this is to place a buffer storage between the main memory, the central processing unit, and the data channel device, which is faster than the main memory but has a smaller storage capacity.

When accessing main memory from a data channel device,
First, the buffer storage is accessed, and if the necessary data does not exist there, the data is transferred from the main memory to the buffer storage, thereby reducing the appearance from the central processing unit and data channel device. There is a method for shortening the access time to the above main storage device.

In such a data processing system, in order to improve the HisoI ratio for the buffer storage, when the central processing unit performs memory access related to operand data, if the next block does not exist in the buffer storage, the next block is Prefetch the block of
There is a way to transfer it to buffer storage. By doing so, when the next block is accessed, since it exists in the buffer storage, data can be quickly transferred to the calculation unit, and the processing capacity of the data processing device can be improved.

However, for instructions that do not process large amounts of data, the memory access is completed in one go, so the briefetched operand data may be wasted.Therefore, a more efficient briefetch method for data transfer has been desired. .

tc+ Prior Art and Problems The briefetch method for buffer storage associated with memory access from the central processing unit that has been adopted so far is that there is an operand access from the central processing unit, and the following of the operand data required for buffer storage is When there was no data in a block, the next block was always prefetched and transferred to the above breadth storage.

However, among the instructions that make up a program, instructions that do not process large amounts of data (for example, load/store instructions) are used more frequently, and prefetched data blocks are wasted, and the memory visit time associated with the briefetch method is An increase in

Due to the above-mentioned unnecessary prefetch, data blocks that were originally required by other instructions are also replaced, which has the problem of reducing the overall processing capacity of the data processing system.

(dl) Purpose of the Invention In view of the above-mentioned conventional drawbacks, the present invention provides efficient prefetching of operand data required for buffer storage when the next block of data does not exist in operand access accompanying the execution of an instruction by a central processing unit. The purpose of this is to provide a method to do this.

According to the present invention, in a data processing device having a two-layer memory system of a main memory and a buffer storage consisting of a plurality of blocks, a large amount of continuous Only during operand access processing of an instruction that handles operand data, if the data of the next block of operand data requested by the above instruction does not exist in the buffer storage, a method of prefetching the next block and transferring it to the buffer storage. Prefetching is performed only when processing a large amount of continuous data such as a move instruction, so only data that has a high probability of being used when executing an instruction is prefetched, which is different from the conventional method. This method has the advantage of preventing a decrease in the usage efficiency of the panfer storage that occurs when using the briefetch method.

(fl Embodiments of the Invention The key point of the present invention is that in a data processing system having a two-layer memory system of main storage and breadth storage, memory access for operand data is performed and the operand data is stored in buffer storage. , when the next block data does not exist, prefetching is used to transfer the next block data to buffer storage.
This is done only when accessing the operands of an instruction that processes a large amount of continuous data, such as a move instruction.

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a diagram showing an embodiment of the present invention in a block diagram,
1 is the calculation unit, 2 is the memory address register (AR),
3 is a +1 adder, 4 is a selector that selects either a normal memory address or a memory address incremented by 1 for prefetching, and 5 is set when an instruction processes a large amount of continuous data, such as a move instruction. Lunch (MVL
), 6 is a brief fetch control circuit necessary for implementing the present invention, and 7 is a buffer storage tag section (TAG).
71 and a data section (BS) 72. 8 is buffer storage store data register <B55D11
), 9 is a buffer storage read data register (BSRDR), and 10 is a comparator, which searches for the presence or absence of a data block corresponding to a required address in correspondence to a plurality of ways consisting of a plurality of blocks constituting the buffer storage 7. In order to do this, the memory address register (
The first hit 22 of AR) 2 and the tag section (TAG) 71 of the buffer storage 7 are compared, and if a matching output is obtained, it indicates that the required data block exists in the way. . And 11 is an address bus for the main memory.

First, the operand address is calculated in the arithmetic unit 1 and stored in the memory address register (AR) 2.
The lower part 21 passes through the selector 4 to the tag part (TAG) 71 and data part (BS) of the buffer storage 7.
) Sent to access 72.

As a result, from the tag part (TAG) 71, the corresponding data part (BS)? The address having data in way 2 is output, and the output is compared with the upper part 22 of memory address register (AR) 2. If a matching output is not obtained, the data block corresponding to the operand address does not exist in the data section (BS) 72 of the buffer storage 7, and the data block corresponding to the operand address is transferred from the main memory to the buffer. In order to transfer to storage 7, the memory address register (A
R) 2 is sent to the main memory through the address bus 11, the data block at the address is read out, and the output is sent to the breadth storage store data register (BS
SDR') 8 is stored in the data section (BS) 72 of the buffer storage.

From then on, the data e (B
Operand data is read from S) 72 through the buffer storage read data register (BSRDR) 9 and sent to the arithmetic unit 1, where processing for this operand is executed.

At this time, when the instruction that requires the above operand data is an instruction that processes a large amount of continuous data, such as a move instruction, following the above data transfer, the next data block is briefetched and stored in the breadthreader storage 7. By transferring the information, it is possible to improve the hint rate for the buffer storage 7 when accessing the operand of the instruction.

Therefore, when the signal MV indicating that the operand access is the move instruction is sent from the calculation unit 1, set to launch (MVL), and starts the briefetch control circuit 6, the briefetch control circuit 6 uses the memory address register ( 8R) After transferring the data corresponding to the operand address indicated by 2 to the arithmetic unit, selector 4 selects + in order to prefetch the next data block.
1, the result of the adder is controlled to be taken out, and it is searched again to see if the block at the address exists in the buffer storage 7. If the block does not exist, the brief address is sent to the address bus 11. Then, data transfer for prefetching is performed.

The subsequent operation is the same as normal memory access.

(g) Effects of the Invention As explained in detail above, according to the present invention, when an operand access is made to a memory system consisting of two layers of main storage and buffer storage, the operand data is required. Only when the instruction is an instruction that processes continuous data such as a move instruction, if the next data block does not exist in the buffer storage, a prefetch is automatically performed to transfer the data block from the main memory to the buffer storage. This has the effect of improving the hint rate for buffer storage during consecutive operand accesses regarding the instruction, and preventing a decrease in buffer storage usage efficiency that occurs in the prior art.

[Brief explanation of the drawing]

The figure is a block diagram showing one embodiment of the present invention. In the drawing, 1 is an arithmetic unit, 2 is a memory address register (AR), 3 is a +1 adder, 5 is a latch that is set when an instruction that handles continuous data such as a move instruction, 6 is a brief fetch control circuit, and 7 is a briefetch control circuit. buffer storage, 71
is the tag part (TAG), 72 is the data part (BS)
, 8 is the buffer storage store data register (B
9 indicates a buffer storage read data register (BSRDR), 10 indicates a comparator, and II indicates an address bus. 0

Claims (1)

[Claims] In a data processing device that has a two-layer memory system consisting of a main storage device and a buffer I storage consisting of a plurality of blocks, the above is only possible when processing operand access for an instruction that handles a large amount of continuous operand data, such as a move instruction. A brief-fetch method is characterized in that if the data of the next block of operand data requested by an instruction does not exist in the buffer storage, the data of the next block is prefetched and stored in the buffer storage.