JPS59181758A - Digital signal processing circuit - Google Patents

Abstract

PURPOSE:To reduce signal distortion generated by the variation of a pulse width in case of receiving a digital signal by connecting two comparators having the almost same switching speed so as to execute an inverting operation each other. CONSTITUTION:A digital signal from a line 11 is applied to comparators 13, 14 after its level is adjusted by a pre-amplifier 12. A signal for determining a discriminating level Vth is applied to the comparators 13, 14 from a discriminating level setting circuit 15. The comparators 13, 14 have the same switching speed, and have such a relation as a logical state of an output is inverted each other. That is to say, a non-inversion input and an inversion input of the comparator 13 are connected to an inversion input and a non-inversion input of the other comparator 14, respectively. Outputs from the comparators 13, 14 are provided to a flip-flop 16. The flip-flop 16 consists of two NAND gates 17, 18. The output from the comparator 13 is provided to the NAND gate 17 as a reset input S through a line 19.

Description

[Detailed description of the invention] Technical field The present invention relates to a circuit for identifying all digital signals.

Prior Art The prior art is illustrated in FIG. Input signal 9 is fed from line 1 to preamplifier 2, adjusted to a transparent level for input to comparator 3, and then input to comparator 3. The discrimination level vth set by the discrimination level setting circuit 4 is applied to the other input of the comparator 3. The output from the comparator 3 is led out to the line 5. Comparison 3 derives a signal on line 5 that is a high level logic "l" when the soft input is greater than the discrimination level vth, and when its comparison input is at the discrimination level Vth not 74. A low level logic "0" signal is output on line 5. In the ratio 1 collector 3, the transistors used or switching circuits) 1
However, it becomes saturated when it goes into the on state, and the switching time from the on state to the off state is longer than the 1 ml when switching from the off state to the on state.

Figure 2 (1) shows the ratio 1 official power wave j of comparator 3 (<all shown,
Second section ++21fj: Shows the output wave 11 of the ratio j collector 3. Time tl when the input of the comparator 30 becomes sharper than the discrimination level vth and the output changes from low level to high level
The time t2 at which the input becomes smaller than the discrimination level vth and the output changes from high level to low level is different. The difference in these R5 response times (r, as the transmission speed becomes faster, the effect becomes greater, resulting in an increase in the sign distortion of the output signal, that is, the Parnu It1,3 distortion) .In Figure 2 (2) - reference Ifi mark VLG is 5
This is the discrimination level of the subsequent logic circuit receiving the signal from line 5. There is a relationship between the first equation and the second equation.

tHl = tH-tl + t2...°
(1) tLl = tL - t2 + tl
...(2) For example, if tl = 140ns and transmission speed is 5Mbit/s, tH = tL = 2
00ns, so tLl = 120ns,
Therefore, sign distortion cannot be reduced.

Purpose An object of the present invention is to provide a digital signal processing circuit that reduces code distortion caused by changes in pulse width when receiving a digital signal.

Embodiment @3 FIG. 3 is a block diagram of an embodiment of the present invention. The digital signal from line 11 is applied by preamplifier 12 to level IW loss 7L, comparator ib l 3 e 14. The ratio 1 collectors 13 and 14 receive a signal from the discrimination level setting circuit 15 that determines the discrimination level vth. Comparators 13 and 14 have the same switching speed and are in a relationship such that the logic states of their outputs are inverted. That is, the non-inverting input and the inverting input of the comparator 13 are connected to another comparator 14, and the inverting input and the non-inverting input, respectively. The outputs from comparators 13 and 14 are applied to flip-flop 16. The flip-flop 16 - consists of two NAND gates 17.18. The output from the comparator 13 is connected to the reset manual S via line 19.
As a result, it is given to NAND (NAND) 17. Comparator 14
The output is given as the reset force R of the flip-flop 16 through one line 20. NAND gate 17
From, the cent output Q is derived from another NANI
A reset output Q is derived from the J gate 18. The logic operation of this flip-flop 16 is as shown in Table 1.

Table 1 It is assumed that the response time 11 in the comparator 13.14 is tl (t2). The level vth is set by the discrimination level setting circuit 15.The discrimination level is indicated by the reference symbol vth.The output waveform from the comparator 13 to the line 19 is shown in FIG. The output waveform from comparator 14 to line 20 is shown in FIG. 4(2).Flip-flop 1
The set output Q given to the subsequent logic circuit from 6 is shown in FIG. 4-6), and the reset output Q is shown in FIG. 4 (4). It is assumed that the transmission code is a combination of repeated logic "O" and logic rlJ. The discrimination level vth has a value that is half the amplitude of the waveform input to the comparators 13 and 14. Therefore, the comparators 13 and 14 output the E signal delayed by the response times tl and t2.

In this embodiment, since tl (t2), the comparator 13°1
The output waveform No. 4 has a longer high level state than the input waveform.

The flip-flop 16 is composed of NAND gates 17 and 18, and when both inputs are logic rlJ as shown in Table 1 described in +IJ, the set output Q and reset output ζ have an arbitrary output state of 1''1■. Hold.

The output signal of the comparator 13, 1a is a flip 70 tube'
There are 16 set manpower S and reset manpower R.

fc, the transmission code 8 used to be a logic "0" to a logic "1"
Assuming that the fc field 43 changes to
remains at a logic "l", and therefore the cent output Q remains at a state of 611, or a logic "0". Next, when the set human power S becomes the logic rOJ, the reset input k is logic "1", so the set output Q becomes the logic rM
Convert to Kf.

Assume that the transmission code changes from logic "l" to logic rOJ. Set input 100 is logical "0" to 1 run immediately Ill
At this time, since the reset human power R is still up to -1 of logic "1", the set output Q remains in the state of the song, that is, the logic "1". Next, when the reset manual power k becomes logic "0", the set input S becomes logic "0".
1'', the set output Q changes to logic ``0''.

Here, when the state of the set output Q changes, there is a delay of response times tla and t2a of the NAND gates 17 and 18 forming one flip 70 block 16.

In this way, the original transmission code of the set output QKi is regenerated, but at this time, the set output Q is at a high level, that is, M
Pulse when Ilj is +lll] 1t H1 is -tH
L = tH - t2 - tla + t2 + t2a
= tH−tla + t2a −+5
It becomes 1. Also, the set output Q is at a low level, that is, tL
l=tl-t2-t2a+t2+tla=jL t
2a + tla ”・+
It becomes 61. Here t l a , t 2 aUNA
Although it differs depending on the type of ND gate 17.18, if a power Schottky TTL is used, t1a=
7ns.

t2a = 8ns, 1 car seat, and the difference between both tla and t2a is the response time of comparator 13.14 tl = 60ns,
The softening f'L compared to the difference of 80 ns when t2=140 ns is sufficiently small and can be almost ignored. Therefore, the pulse width tl (1, tLl is tH
.

The value is almost the same as tL, and the gradient sign 7' has little sign distortion.
+ilq can be produced.

By the way, transmission speed is 5Mbit/S, tla=7n
s.

If t2a = 8ns, LH = tL, then tL
l = tL - t2a + tla = 199ns
and the sign distortion is Tamago x 100 = L), 5%
...(7). Reset output Q If
C is derived at the same timing as the IJ'f code of the set output Q.

FIG. 5 shows block section 1 of another embodiment of the present invention.

This embodiment is similar to the previous embodiment and corresponding parts are provided with the same reference numerals. It should be noted that the flip-flop 26 consists of two NOR gates 27 and 28, and the output from the comparator 13 is applied to the NOR gate 2 as the set input S.
The output from the other comparator 14 is input to the NOR gate 28 as the set input R. ,
The output of the NOR gate 27 is the reset output Q and -N
The output of OR gate 28 is set output Q. Flip-flop 26 performs the acid operation shown in Table 2.

In Table 2, Figure 6 +l+, +jf input to comparator 13.14.
All signal waveforms from the 11u amplifier circuit are shown, the output waveform from the ratio F splitter 13 is shown in FIG. 6 (3), and the output waveform from the ratio J splitter 14 is shown in FIG. 6 1 (2). It is shown in
The set output QU of the flip 70 knob 26 is shown in FIG. 6 (6), and its reset output Q id 'd16
This is shown in Figure (4). In these 1711Ifl, the reference V26 is the discrimination level of the flip-flop 26, and the reference V30 represents the discrimination level of the subsequent self-caping circuit receiving the set output Q and the reset output Q. Here, tl ) t2. The output of comparator 13.14 is the response time t2. Since t17'ζ is delayed J'L, the low-level state jδ has a long waveform compared to an ordinary input pulse.

It is composed of a flip-flop z6id and a NOR gate, and as is clear from the above @2 table, when both the meat inputs S and R become logic "0", the set output Q and the reset output Q (r, 1 jjiT The output state of 1h"it is maintained.

If the transmission code is changed from logic "0" to logic rlJ, 4-
Assume 3. The reset output Q becomes logic "0" when the reset human power R changes from logic "0" to "1".
changes from to logic "1". On the other hand, the transmission code is logical rl
Assuming a change from J to ethics "0", the reset output Q changes from logic "1" to logic "0" as the set human power S changes from logic "0" to logic "1". Here, when the state of the reset output d changes, the response time tla, t2a of the NOR gates 27 and 28 constituting the flip-flop 26 is slower than the change in the set human power S and the reset human power R. In this way, the original transmission code is reproduced at the reset output 6. At this time, when the reset output Q is at the L-I level, that is, the logic is "1", the barne width t Hl is expressed by the eighth equation 'i - The reset output d is at a low level, that is, a logic “
0'', the result is as shown by the formula 'M9.

tH1=tH・-tl-tla+tl+t2a=tH
-tla+ t2a -(8)tLl
=tL-tl-t2a-t-tl+tla=tL-
t2a + tla - t9)
In this way, the above-mentioned embodiment and the slope of 11-1c1°
A code with less signal distortion is generated. Flip-flop.

The set output QK of No. 26 is derived at the same timing as the determined output of the reset output Q.

According to such an embodiment, the +distortion on the slope is determined only by the response time of the gates 17, 18, 27, 28, which constitute the flip-flops 16, 26, regardless of the switching speed of the softeners 13, 14. is determined, it is possible to reduce the sign distortion to a minimum of ≠S.

If the response time of the gates 17, 18, 27, 2.8 is the comparator 13, 140? The advantage of this kind of sign distortion reduction is that the response time is shorter than the response time.
Since there is a limit to reducing the response speed of 3 and 14,)IJ
High speed low power consumption type TT with 16.27 flops
It is possible to further reduce code distortion by using VC such as L, Nyotoki TTL, etc.

Further, in such an embodiment, since inverted outputs with uniform timing can be obtained, it is convenient that a high-speed logic circuit can be used in a subsequent arrangement.

Gates 17°1s, 2 constituting the flip-flop 26
7.28 types (i.e. - Complementary Oxide Semiconductor C-
It is convenient to use the same type of logic circuit elements (MOS, low power consumption type TTL, etc.) as the logic circuit elements to be connected afterwards, so that the signal levels are the same and matching can be achieved.

Effects As described above, according to the present invention, a digital signal processing circuit that can reduce code distortion is realized.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the prior art, FIG. 2A is a waveform diagram for explaining the ω1 operation of the prior art shown in FIG. 1, FIG. 3 is a block diagram of an embodiment of the present invention, and FIG. The figure shows the third
A waveform diagram for explaining the operation of the embodiment shown in FIG. 5, a block diagram of another embodiment of the invention shown in FIG. The waveform to be used for explanation is shown in (1). 13.14... Comparator, l 6, 2 ti...° flip-prop 17.18... NANO) gate, 27.28... NOR gate agent patent attorney Shikyo Kei partial procedure correction May 9, 1959, Director General of the Japan Patent Office, Patent Application No. 58-43878 2. Title of the invention Digital signal processing circuit 3. Person making the amendment Relationship to the case Applicant's address Name (583) ) Matsushita Electric Works Co., Ltd. Representative 4, Agent address: Shinkosan Building 6, 1-13-38 Nishihonmachi, Nishi-ku, Osaka, details of the invention in the specification to be amended, ij5. Column 7, Contents of the amendment (I amend the 6th line of page 3 of the specification as follows. In lines 5 to 6, the phrase "power consumption type Schottky" is corrected to "low power consumption type Schottky." (3) In the specification, page 8, line 18, and page 12, line 5 (4) In the specification, page 12, lines 17 to 18, and page 13, line 6, the phrase “low power consumption TTLJ” has been replaced with “low power consumption type”. Corrected to power consumption type Schottky TTLJ.

Claims (1)

[Claims] Two comparators with almost the same switching speed are connected so that they operate inversely to each other, and their outputs are
A digital signal processing circuit characterized by a 0 connected to a flip-flop consisting of an AND gate or a UNOR gate.