JPS5545246A - Information receiving unit - Google Patents
Information receiving unitInfo
- Publication number
- JPS5545246A JPS5545246A JP11836278A JP11836278A JPS5545246A JP S5545246 A JPS5545246 A JP S5545246A JP 11836278 A JP11836278 A JP 11836278A JP 11836278 A JP11836278 A JP 11836278A JP S5545246 A JPS5545246 A JP S5545246A
- Authority
- JP
- Japan
- Prior art keywords
- mpu
- signals
- data bus
- circuit
- processing circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Digital Computer Display Output (AREA)
- Television Systems (AREA)
Abstract
PURPOSE: To facilitate the high-speed receiving display operation of a TV character multiple broadcast by providing a write processing circuit, a main memory, a read processing circuit and a micro processor unit MPU and driving the MPU with two- phase clocks.
CONSTITUTION: Received serial signals are converted to parallel signals byte by byte by write processing circuit 3 and are supplied to a data bus. MPU 4 fetches information signals from the data bus and writes pattern signals from the data bus to main memory 7 through address control circuit 6. MPU 4 is driven by two-phase clocks ϕ1 and ϕ2 from clock control circuit 10 and is provided with a data port which becomes high-impedance during a clock period dependent upon one clocks and reads out pattern signals from memory 7 to read processing circuit 8 through the data bus during this period. Circuit 8 converts parallel pattern signals to serial signals and sends them to display circuit 9. As a result, a high-speed processing can be performed without influence on data signal fetch in MPU 4.
COPYRIGHT: (C)1980,JPO&Japio
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11836278A JPS5545246A (en) | 1978-09-25 | 1978-09-25 | Information receiving unit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11836278A JPS5545246A (en) | 1978-09-25 | 1978-09-25 | Information receiving unit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5545246A true JPS5545246A (en) | 1980-03-29 |
| JPS5745114B2 JPS5745114B2 (en) | 1982-09-25 |
Family
ID=14734820
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11836278A Granted JPS5545246A (en) | 1978-09-25 | 1978-09-25 | Information receiving unit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5545246A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56169975A (en) * | 1980-06-02 | 1981-12-26 | Hitachi Ltd | Receiver for character broadcasting |
| FR2533719A1 (en) * | 1982-09-28 | 1984-03-30 | Kitchin David | SYNCHRONOUS CLOCK STOP DEVICE FOR MICROPROCESSOR |
| US5339160A (en) * | 1992-04-24 | 1994-08-16 | Sanyo Electric Co., Ltd. | Character display device for synchronizing operation of video ram to operation of CPU |
| JP2014067415A (en) * | 2012-09-24 | 2014-04-17 | Samsung Electronics Co Ltd | Display driver integrated circuit, and display data processing method |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6518468B1 (en) | 1994-09-16 | 2003-02-11 | Albemarle Corporation | Bromination process |
-
1978
- 1978-09-25 JP JP11836278A patent/JPS5545246A/en active Granted
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56169975A (en) * | 1980-06-02 | 1981-12-26 | Hitachi Ltd | Receiver for character broadcasting |
| FR2533719A1 (en) * | 1982-09-28 | 1984-03-30 | Kitchin David | SYNCHRONOUS CLOCK STOP DEVICE FOR MICROPROCESSOR |
| US5339160A (en) * | 1992-04-24 | 1994-08-16 | Sanyo Electric Co., Ltd. | Character display device for synchronizing operation of video ram to operation of CPU |
| JP2014067415A (en) * | 2012-09-24 | 2014-04-17 | Samsung Electronics Co Ltd | Display driver integrated circuit, and display data processing method |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5745114B2 (en) | 1982-09-25 |
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