JPH1197423A - Semiconductor micro-processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to suppress the formation of an inverted layer by automatic doping and diffusion of impurities into an epitaxial layer. SOLUTION: A field oxide film 2 is formed on an n-type silicon substrate 1. With photoresist which is patterned in the specified shape as a mask, an opening part 2a is formed by etching the field oxide film 2. The photoresist is removed. Then, with the field oxide film 2 wherein the opening part 2a is formed as a mask, p-type impurities are deposited. A p+ type embedded sacrifice layer 3 is formed by performing thermal diffusion in nitrogen atmosphere. Then, a silicon oxide film 4 is formed at the formed part of the opening part 2a by performing wet oxidation or pyrogenic oxidation. Then, the field oxide film 2 and the silicon oxide film 4 are completely etched and removed along the entire surface. An n-type epitaxial layer 5 is deposited on the formed side of the p+ type embedded sacrifice layer 3 of the silicon substrate 1. At this time, p-type impurities are diffused from the p+ type embedded sacrifice layer 3 through the interface with the silicon substrate 1, and a final p-type embedded sacrifice layer 6 is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor micromachining method.

[0002]

2. Description of the Related Art Sacrificial layer etching is disclosed in Japanese Patent Application No. 9-234114.
Is a semiconductor micro-machining method used for the manufacture of sensors such as acceleration, as proposed in Japanese Patent Application No. Hei 9-234116. By using this method, a small and highly sensitive sensor can be realized. It becomes possible.

FIG. 5 is a schematic sectional view showing a part of a manufacturing process of a conventional semiconductor acceleration sensor. First, thermal oxidation is performed on an n-type silicon substrate 1 to form a field oxide film 2 of about 10000 °, and the field oxide film 2 is patterned into a predetermined shape by photolithography and etching to form an opening 2a. (FIG. 5
(A)).

Subsequently, a p-type impurity such as boron (B) is deposited using the field oxide film 2 in which the opening 2a is formed as a mask, and thermally diffused in a nitrogen atmosphere to form a p + -type impurity having a diffusion depth of about 5 μm. The buried sacrificial layer 3 is formed (FIG. 5
(B)).

Next, the field oxide film 2 on the silicon substrate 1 is removed by etching, and an n-type epitaxial layer 5 is formed on the surface of the silicon substrate 1 on which the p + type buried sacrificial layer 3 is formed. At this time, since the epitaxial growth is a kind of heat treatment process, the impurities in the p + -type buried sacrificial layer 3 diffuse to the epitaxial layer 5 side through the surface of the silicon substrate 1, and as a whole, the p + -type buried sacrificial layer 3 is formed. 6 (see FIG. 5).
(C)).

Next, a piezoresistor 7 and a contact wiring 8 are formed in the epitaxial layer 5 by deposition or ion implantation, and a photoresist 9 is applied on the epitaxial layer 5 (FIG. 5D). Then, patterning is performed to a predetermined shape by performing development.

Next, using the photoresist 9 patterned into a predetermined shape as a mask, an epitaxial layer 5 is formed using an alkaline etchant such as a potassium hydroxide solution.
By performing anisotropic etching, an etchant inlet 10 reaching the p + type buried sacrificial layer 6 is formed.
(E)).

Finally, an etchant is introduced from the etchant inlet 10 to selectively remove only the p + type buried sacrificial layer 6, thereby forming a cavity 11 (FIG. 5F).

In the following steps, a desired portion of the silicon substrate 1 and the epitaxial layer 5 is removed by etching, and a weight portion (not shown) and a bending portion (not shown) for suspending and supporting the weight portion are provided. Then, a semiconductor acceleration sensor is formed by forming a support portion (not shown) for supporting the bending portion.

[0010]

Here, in order to improve the selectivity at the time of etching the sacrificial layer, the buried sacrificial layer 6 is required.
It is known from literatures that the higher the impurity concentration is, the better and it is desirable that the impurity concentration be 2 × 10 ¹⁹ cm ⁻³ or more (B.Sc
hwartz, "Chemical Etching of Silicon", SOLID-STATE S
CIENCE AND TECHNOLOGY, pp. 1903-1909, DEC. 1976). Therefore, conventionally, the impurity concentration near the surface of the silicon substrate 1 immediately after the formation of the buried sacrificial layer 6 is extremely high, and is 1 × 10 ²⁰ cm ^−3.
It has become about.

However, since the surface of the silicon substrate 1 is completely exposed at the beginning of the epitaxial growth,
The impurities in the p + -type buried sacrificial layer 3 escape into the atmosphere for forming the epitaxial layer 5 and are taken in at the same time as the epitaxial growth. This phenomenon is generally called auto-doping, and the degree of this phenomenon naturally increases as the impurity concentration of the p + -type buried sacrificial layer 3 increases.
When the impurity concentration of the p + type buried sacrificial layer 3 is particularly high,
As shown in FIG. 6, an inversion layer 12 which is a p + type impurity region is formed near the interface between the silicon substrate 1 and the epitaxial layer 5 by auto doping even in a region where a p + type impurity region is not formed by design. As a result, there is a problem that the characteristics of the element are adversely affected.

As shown in FIG. 7, the cross section of the final element of the three-axis acceleration sensor is such that the weight portion 13 is suspended and supported at the center of the bending portion 14, and the bending portion 14 is supported by the supporting portion 15. It has become.

The principle of operation is as follows.
The displacement of No. 3 is output as a change in voltage by a piezo resistor (not shown) formed in the bending portion 14.

Here, the thickness of the bending portion 14 is obtained by subtracting the thickness of the cavity 11 formed in the epitaxial layer 5 from the thickness of the epitaxial layer 5. The target value is set from the characteristic specifications such as sensitivity.
The diffusion depth of the impurity from the p + -type buried sacrificial layer 3 to the epitaxial layer 5 side becomes deeper as the impurity concentration of the p + -type buried sacrificial layer 3 becomes higher. In order to obtain the epitaxial layer 5 having a desired thickness, In addition, there is a problem that the epitaxial layer 5 has to be grown, and the burden on the process increases.

The present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor capable of suppressing formation of an inversion layer by autodoping and diffusion of impurities into an epitaxial layer. It is to provide a micro-machining method.

[0016]

According to the first aspect of the present invention,
Forming a high concentration second conductivity type impurity region on one main surface of the first conductivity type semiconductor substrate; forming a first conductivity type epitaxial layer on one main surface of the first conductivity type semiconductor substrate; Forming a through hole reaching the high-concentration second conductivity type impurity region in the epitaxial layer, introducing an etchant through the through hole, etching away the high concentration second conductivity type impurity region, and forming a cavity. In the processing method, the impurity concentration of the high-concentration second conductivity type impurity region is reduced near one main surface of the first conductivity type semiconductor substrate.

According to a second aspect of the present invention, in the semiconductor micromachining method according to the first aspect, the impurity concentration in the high concentration second conductivity type impurity region near one main surface of the first conductivity type semiconductor substrate is set to 5%. × 10 ¹⁹ cm ^-3 or less.

According to a third aspect of the present invention, in the semiconductor micro-machining method according to the first or second aspect, the high-concentration second conductivity type impurity region is formed by impurity deposition and thermal diffusion. Alternatively, the impurity concentration of the high-concentration second-conductivity-type impurity region is reduced near one main surface of the first-conductivity-type semiconductor substrate by performing pyrogenic oxidation.

According to a fourth aspect of the present invention, in the semiconductor micro-machining method according to the first or second aspect, the high-concentration second conductivity type impurity region is directly formed on one main surface of the first conductivity type semiconductor substrate. Performing high-concentration second-conductivity-type impurity regions having a low impurity concentration near one main surface of the first-conductivity-type semiconductor substrate by performing impurity ion implantation and annealing. Things.

According to a fifth aspect of the present invention, in the semiconductor micromachining method according to the first or second aspect, after forming the high concentration second conductivity type impurity region, the high concentration second conductivity type impurity region is formed. An impurity of the first conductivity type is doped near one main surface of the first conductivity type semiconductor substrate.

According to a sixth aspect of the present invention, in the semiconductor micromachining method according to any one of the first to fifth aspects, at least the first conductivity type of the first conductivity type semiconductor substrate and the first conductivity type epitaxial layer is provided. The impurity concentration of the epitaxial layer is higher than the maximum value of the impurity concentration of the second conductivity type incorporated into the first conductivity type epitaxial layer by autodoping during epitaxial growth.

[0022]

Embodiments of the present invention will be described below with reference to the drawings. In the following embodiments, the description will be made based on the condition where the target of the diffusion depth of the p + type buried sacrificial layer 6 is 10 μm, but the present invention is not limited to this condition.

Embodiment 1 = FIG. 1 is a schematic sectional process view showing a semiconductor micromachining method according to an embodiment of the present invention. First, a field oxide film 2 is formed on an n-type silicon
An opening 2a is formed by etching the field oxide film 2 using a photoresist (not shown) patterned and formed into a predetermined shape as a mask, and the photoresist is removed by plasma ashing or the like (FIG. 1 ( a)).

Subsequently, a p-type impurity such as boron (B) is deposited using the field oxide film 2 in which the opening 2a is formed as a mask, and is thermally diffused in a nitrogen atmosphere to have a diffusion depth of about 5 μm. The p + type buried sacrificial layer 3 is formed.

Next, a silicon oxide film 4 is formed at a position where the opening 2a is formed by about 3500.degree. By performing wet oxidation or pyrogenic oxidation (FIG. 1B). At this time,
The impurity concentration in the vicinity of the surface of the silicon substrate 1 of the p + type buried sacrificial layer 3 when only thermal diffusion is performed in a nitrogen atmosphere is about 1 × 10 ²⁰
cm ^-3 is whereas, by adding a step of wet oxidation or pyrogenic oxidation, as shown in FIG. 2, p + -type buried sacrificial layer silicon substrate 1 surface impurity concentration in the vicinity of 3 to about 4 × 10 Reduced to ¹⁹ cm ^-3 .

Next, the field oxide film 2 and the silicon oxide film 4 are completely etched and removed over the entire surface, and an n-type epitaxial layer 5 is deposited on the side of the silicon substrate 1 on which the p + type buried sacrificial layer 3 is to be formed (FIG. 1 (c)). At this time, the p-type impurity is diffused from the p + -type buried sacrificial layer 3 through the interface with the silicon substrate 1 also on the epitaxial layer 5 side, and the final p + -type buried sacrificial layer 6 is formed.

In the present embodiment, by lowering the impurity concentration of the p + type buried sacrificial layer 3 near the surface of the silicon substrate 1, when the silicon substrate 1 having the impurity concentration of 1 × 10 ¹⁵ cm ⁻³ is used, The diffusion of the impurity to the epitaxial layer 5 side is about 3.5 μm compared to about 4 to 5 μm in the past.
m, and the thickness of the inversion layer by auto-doping is about 2.5 μm compared to about 5 μm in the past.
m, and the peak concentration in the inversion layer can be suppressed to the order of 10 ¹⁵ cm ⁻³ , which was conventionally of the order of 10 ¹⁶ cm ⁻³ .

Embodiment 2 = FIG. 3 is a schematic sectional process view showing a semiconductor micromachining method according to another embodiment of the present invention. First, a field oxide film 2 is formed on an n-type silicon substrate 1 by thermal oxidation for about 50 minutes.
The opening 2a is formed by etching the field oxide film 2 using a photoresist (not shown) formed and patterned into a predetermined shape as a mask, and the photoresist is removed by plasma ashing or the like (FIG. 2 ( a)).

Subsequently, a p-type impurity such as boron (B) is ion-implanted using the field oxide film 2 in which the opening 2a is formed as a mask (FIG. 2B), and annealing is performed to form ap + -type impurity. Forming an embedded sacrificial layer 3 (FIG. 2)
(C)). At this time, a silicon oxide film 7 is formed at the location where the opening 2a is formed.

Next, the field oxide film 2 and the silicon oxide film 7 are completely etched and removed over the entire surface, and an n-type epitaxial layer 5 is deposited on the side of the silicon substrate 1 on which the p + -type buried sacrificial layer 3 is to be formed (FIG. 2 (d)). At this time, the p-type impurity is diffused from the p + -type buried sacrificial layer 3 through the interface with the silicon substrate 1 also on the epitaxial layer 5 side, and the final p + -type buried sacrificial layer 6 is formed.

Here, it is known that the peak of the distribution of impurities immediately after ion implantation appears slightly deeper than the implantation surface due to the channeling effect, and this distance depends on the type of impurity and the acceleration energy during implantation. For example, when boron (B) is ion-implanted at an acceleration energy of 100 keV, a peak appears at a position approximately 2.5 μm deeper than the implantation surface. Assuming the same peak concentration, the deeper the peak position, the lower the impurity concentration on the surface of the silicon substrate 1.

Therefore, in the present embodiment, the ion implantation is performed in a state where the surface of the silicon substrate 1 is exposed. Therefore, the peak of the impurity distribution is compared with the case where the surface of the silicon substrate 1 has a protective film or the like. As a result, a peak concentration appears at a deep position from the surface of the silicon substrate 1, and the impurity concentration on the surface of the silicon substrate 1 can be suppressed. Even if diffusion in the depth direction of the silicon substrate 1 progresses by the subsequent annealing, the tendency of the impurity concentration distribution does not change. Therefore, if ion implantation conditions and annealing conditions are appropriately set, p +
The impurity concentration in the vicinity of the surface of the silicon substrate 1 can be kept low while maintaining the impurity concentration of the mold buried sacrificial layer 3 at around 10 ²⁰ cm ^-3 as a whole. Thus, diffusion of impurities to the epitaxial layer 5 side and formation of an inversion layer due to auto doping can be suppressed.

In this embodiment, the case where the annealing process is performed in the air is described. However, the present invention is not limited to this. The annealing process may be performed in a nitrogen atmosphere. However, the impurity concentration on the surface of the silicon substrate 1 can be further reduced in the case where the annealing is performed in the air as compared with the case where the annealing is performed in the nitrogen atmosphere.

Embodiment 3 = FIG. 4 is a schematic sectional process view showing a semiconductor micromachining method according to another embodiment of the present invention. First, a field oxide film 2 is formed on an n-type silicon substrate 1 by thermal oxidation for about 12 minutes.
The field oxide film 2 is formed by using a photoresist (not shown) formed in a predetermined shape and patterned in a predetermined shape as a mask.
The opening 2a is formed by performing the etching described above, and the photoresist is removed by plasma ashing or the like (FIG. 4A).

Subsequently, using the field oxide film 2 in which the opening 2a is formed as a mask, a p-type impurity such as boron (B) is deposited and thermally diffused to form a p + -type buried sacrificial layer 3.
a is formed. At this time, a thin silicon oxide film 4 is formed where the opening 2a is to be formed (FIG. 4B).

Next, ions of n-type impurities such as phosphorus (P) are implanted using the field oxide film 2 in which the opening 2a is formed as a mask (FIG. 4C), and annealing is performed in a nitrogen atmosphere. As a result, a p + type buried sacrificial layer 3b having a low impurity concentration near the surface of the silicon substrate 1 is formed (FIG. 4).
(D)). Here, at the time of ion implantation, ion implantation is performed with the silicon oxide film 4 left in order to prevent a channeling effect. In addition, it is necessary to optimally design the ion implantation conditions of the n-type impurity so that the conductivity type is not inverted in the p + -type buried sacrificial layer 3a.

Finally, the field oxide film 2 and the silicon oxide film 4 are completely etched and removed over the entire surface, and an n-type epitaxial layer 5 is deposited on the silicon substrate 1 on the side of the p + type buried sacrificial layer 3b (FIG. 4 (e)). At this time, the p-type impurity is diffused from the p + -type buried sacrificial layer 3 through the interface with the silicon substrate 1 also on the epitaxial layer 5 side, and the final p + -type buried sacrificial layer 6 is formed.

In the present embodiment, boron (B) as a p-type impurity and phosphorus (P) as an n-type impurity are both present near the surface of the silicon substrate 1 in the p + type buried sacrificial layer 3b. At the time of epitaxial growth, each impurity escapes into the atmosphere at the same time and is taken into the epitaxial layer 5, so that both are canceled out, and the formation of the inversion layer can be suppressed.

Further, since the respective impurities are simultaneously diffused to the epitaxial layer 5 side even through the surface of the silicon substrate 1, the two are offset, and the epitaxial layer 5 is removed.
The diffusion depth of the p + type buried sacrificial layer 6 formed therein can also be suppressed.

In this embodiment, after the deposition and the thermal diffusion are performed, an impurity of the opposite conductivity type is ion-implanted in the vicinity of the surface of the silicon substrate 1 in the formed p + type buried sacrificial layer 3a. However, the present invention is not limited to this. The impurity of the opposite conductivity type may be doped in the vicinity of the surface of the silicon substrate 1 in the p + -type buried sacrificial layer 3a. For example, the deposition is performed after the deposition is performed. There are a method of performing deposition diffusion after performing ion implantation, a method of performing an annealing process after ion-implanting impurities of the opposite conductivity type, and the like.

In all the embodiments described above, the impurity concentration of at least the epitaxial layer 5 in the silicon substrate 1 and the epitaxial layer 5 is higher than the impurity concentration taken into the epitaxial layer 5 by autodoping during epitaxial growth. By doing so, it is possible to cancel the taken-in impurities, to completely prevent the formation of the inversion layer, and to suppress the diffusion of the impurities to the epitaxial layer 5 side through the surface of the silicon substrate 1. can do.

In all the above embodiments,
The n-type is used as the conductivity type of the silicon substrate 1 and the epitaxial layer 5, and the p-type is formed as the buried sacrificial layer. However, the present invention is not limited to this. Applied.

[0043]

According to the first aspect of the present invention, a high-concentration second-conductivity-type impurity region is formed on one main surface of a first-conductivity-type semiconductor substrate. A conductive type epitaxial layer is formed, a through hole is formed in the first conductive type epitaxial layer to reach the high concentration second conductivity type impurity region, and an etchant is introduced from the through hole to remove the high concentration second conductivity type impurity region by etching. In the semiconductor micro-machining method of forming a cavity by forming, the impurity concentration of the high-concentration second conductivity type impurity region is reduced near one main surface of the first conductivity type semiconductor substrate. The amount of impurities that escape from the type impurity region into the atmosphere can be reduced, and the formation of an inversion layer by auto doping and the diffusion of impurities into the epitaxial layer can be suppressed. It is possible to provide a semiconductor microfabrication how.

According to a second aspect of the present invention, in the semiconductor micromachining method according to the first aspect, the impurity concentration in the high concentration second conductivity type impurity region near one main surface of the first conductivity type semiconductor substrate is set to 5 × 10 5 ^{Since it is 19} cm ^-3 or less, the amount of impurities that escape from the high concentration second conductivity type impurity region into the atmosphere at the beginning of epitaxial growth can be reduced, and the inversion layer is formed by auto doping, and Can be suppressed.

According to a third aspect of the present invention, in the semiconductor micromachining method according to the first or second aspect, the high-concentration second-conductivity-type impurity region is formed by impurity deposition and thermal diffusion, and is subjected to wet oxidation or By performing the pyrogenic oxidation, the impurity concentration of the high-concentration second conductivity type impurity region is reduced near one main surface of the first conductivity type semiconductor substrate. The amount of impurities escaping into the atmosphere can be reduced, and the formation of an inversion layer by auto doping and the diffusion of impurities into the epitaxial layer can be suppressed.

According to a fourth aspect of the present invention, in the semiconductor micromachining method according to the first or second aspect, the high-concentration second conductivity type impurity region is formed directly on one main surface of the first conductivity type semiconductor substrate. By performing the ion implantation and the annealing process, a high-concentration second-conductivity-type impurity region having a low impurity concentration is formed near one main surface of the first-conductivity-type semiconductor substrate. The amount of impurities that escape from the two-conductivity type impurity region into the atmosphere can be reduced, and the formation of an inversion layer by auto-doping and the diffusion of impurities into the epitaxial layer can be suppressed.

According to a fifth aspect of the present invention, in the semiconductor micromachining method according to the first or second aspect, after forming the high concentration second conductivity type impurity region, the first high concentration second conductivity type impurity region is formed. In the vicinity of one main surface of the conductive type semiconductor substrate, impurities of the first conductive type are doped, so that during the epitaxial growth, the impurities of the first conductive type and the second conductive type simultaneously escape into the atmosphere and form in the epitaxial layer. As a result, the two are offset and the formation of the inversion layer can be suppressed, and at the same time, the diffusion of impurities into the epitaxial layer can be suppressed.

According to a sixth aspect of the present invention, in the semiconductor micromachining method according to any one of the first to fifth aspects, at least the first conductive type epitaxial layer is selected from the first conductive type semiconductor substrate and the first conductive type epitaxial layer. Impurity concentration
Since the second conductivity type impurity concentration taken into the first conductivity type epitaxial layer by autodoping during epitaxial growth is higher than the maximum value, the impurities of the first conductivity type and the second conductivity type can be offset, and the inversion layer Formation can be completely prevented.

[Brief description of the drawings]

FIG. 1 is a schematic sectional process view showing a semiconductor micromachining method according to an embodiment of the present invention.

FIG. 2 is an impurity concentration distribution diagram with respect to a depth from a silicon substrate surface of a p + type buried sacrificial layer according to the embodiment.

FIG. 3 is a schematic sectional process view showing a semiconductor micromachining method according to another embodiment of the present invention.

FIG. 4 is a schematic sectional process view showing a semiconductor micromachining method according to another embodiment of the present invention.

FIG. 5 is a schematic cross-sectional view showing an example of a manufacturing process of a semiconductor acceleration sensor according to a conventional example.

FIG. 6 is a schematic sectional view showing a state in which a p + type buried sacrificial layer is formed in a silicon substrate according to a conventional example.

FIG. 7 is a schematic sectional view showing a three-axis acceleration sensor according to a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Field oxide film 2a Opening 3,3a, 3b p + type buried sacrificial layer 4 Silicon oxide film 5 Epitaxial layer 6 p + type buried sacrificial layer 7 Piezoresistance 8 Contact wiring 9 Photoresist 10 Etchant inlet 11 Cavity 12 Inversion layer 13 Weight part 14 Flexure part 15 Support part

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Takuro Nakamura 1048 Kadoma Kadoma, Osaka Prefecture Inside Matsushita Electric Works Co., Ltd. 72) Inventor Hitoshi Yoshida 1048 Kazuma Kadoma, Kadoma City, Osaka Inside Matsushita Electric Works, Ltd.

Claims (6)

[Claims] A first conductivity type impurity region formed on one main surface of the first conductivity type semiconductor substrate; and a first conductivity type epitaxial layer formed on one main surface of the first conductivity type semiconductor substrate. Forming a through hole reaching the high concentration second conductivity type impurity region in the first conductivity type epitaxial layer, introducing an etchant from the through hole, etching away the high concentration second conductivity type impurity region, and forming a cavity. Wherein the impurity concentration of the high-concentration second-conductivity-type impurity region is reduced near one main surface of the first-conductivity-type semiconductor substrate. 2. An impurity concentration in the high concentration second conductivity type impurity region near one main surface of the first conductivity type semiconductor substrate is set to 5 × 10 ¹⁹ cm ⁻³ or less. The semiconductor micromachining method according to claim 1. 3. The high-concentration second-conductivity-type impurity region is formed by impurity deposition and thermal diffusion, and is subjected to wet oxidation or pyrogenic oxidation.
3. The semiconductor micromachining method according to claim 1, wherein an impurity concentration of the high-concentration second conductivity type impurity region is reduced near one main surface of the first conductivity type semiconductor substrate. 4. The method according to claim 1, wherein the high-concentration second conductivity type impurity region is directly ion-implanted with an impurity and annealed on one main surface of the first conductivity type semiconductor substrate. 3. The semiconductor micromachining method according to claim 1, wherein the high concentration second conductivity type impurity region having a low impurity concentration is formed near one main surface. 5. After forming the high-concentration second-conductivity-type impurity region, an impurity of the first-conductivity-type is formed near one main surface of the first-conductivity-type semiconductor substrate in the high-concentration second-conductivity-type impurity region. 3. The method according to claim 1, wherein the doping is performed. 6. An impurity concentration of at least the first conductivity type epitaxial layer of the first conductivity type semiconductor substrate and the first conductivity type epitaxial layer is adjusted to the first conductivity type epitaxial layer by autodoping during epitaxial growth. 6. The semiconductor micromachining method according to claim 1, wherein the second conductivity type impurity concentration is higher than a maximum value.