JPH1186444A - Data slice circuit and data reproducing apparatus using the same - Google Patents

Abstract

(57) Abstract: The present invention can obtain an optimum slice level for a code string with insufficient DC suppression, and can quickly obtain an optimum slice level even when a received signal level fluctuates greatly. It is an object of the present invention to provide a data slice circuit which can be controlled to a minimum speed and a data reproducing apparatus using the same. A first DSV detecting means for calculating a DSV of data obtained by binarizing a received signal at a predetermined slice level.
Second DSV detecting means 32 to 34, 35, 3 for calculating DSVs of data obtained by sampling data obtained by sampling clocks of the data in synchronization with the data;
Computing means 38 for calculating the difference between the two DSVs;
Smoothing means 18 and 45 for generating a slice level based on the output of the calculating means 38 are provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a receiving system for receiving a digital bit stream controlled so that one polarity period is substantially equal to the other polarity period. The present invention relates to a data slice circuit for converting into binary data and an improvement of a data reproducing device using the same.

[0002]

2. Description of the Related Art As is well known, a conventional data slicing circuit used in a receiving system as described above is configured as shown in FIG. That is, the received signal supplied to the input terminal 11 is supplied to the positive input terminal + of the level comparison circuit 12. The slice level obtained from the integration circuit 13 is applied to the negative input terminal − of the level comparison circuit 12.

The level comparison circuit 12 has an H (High) level when the input level of the positive input terminal + is higher than the input level of the negative input terminal-, and otherwise, the L level is low.
(Low) level binarized data is generated. The binarized data output from the level comparison circuit 12 is led to a data processing system (not shown) at a subsequent stage via an output terminal 14, and the binarized data is output from the integration circuit 13
Supplied to

[0004] The integrating circuit 13 comprises a level comparing circuit 12.
A resistor R inserted between the output terminal and the negative input terminal
And a capacitor C having one end connected between the resistor R and the negative input terminal − of the level comparison circuit 12 and the other end connected to the input terminal 15 to which the reference DC level Vref is applied. I have. The integration circuit 13 integrates the binarized data output from the level comparison circuit 12 to generate an optimum slice level.

FIG. 9 shows the operation of the data slice circuit. First, FIG. 9A shows a transmission data waveform. This transmission data is set so that the H level period and the L level period are substantially equal, that is, DSV (DiV
gital Sum Value) is controlled to be approximately 0. The transmission data is supplied to the input terminal 11 as a sine waveform as shown in FIG. 9B by adding noise on the transmission path.

The level of the received signal shown in FIG. 9B is compared with the slice level obtained from the integrating circuit 13 by the level comparing circuit 12, so that
It is converted to binary data. Here, FIG.
Virtually, three types of slice levels SL1, SL2, and SL3 are shown. In this case, SL2 indicates the optimum slice level, and the received signal is level-sliced at the optimum level SL2, so that the binary data substantially equal to the transmission data is reproduced as shown in FIG. 9D. It is supposed to be.

First, the slice level is set to the optimum level SL2.
In a state in which the level SL1 is higher than the level SL1, as shown in FIG. 9C, the level comparison circuit 12 outputs binarized data in which the L level period occurs more frequently than the H level period. For this reason, the slice level obtained from the integration circuit 13 is sequentially reduced, and as a result, the slice level is controlled to the optimum level SL2.

The slice level is the optimum level SL2.
In a state in which the level SL3 is lower than the level SL3, the level comparison circuit 12 outputs binarized data in which the H level period occurs more frequently than the L level period, as shown in FIG. For this reason, the slice level obtained from the integration circuit 13 sequentially increases, and as a result, the optimum level SL2
It is controlled to go to.

By the way, as described above, the reason why the information to be transmitted is encoded into a code string whose DSV becomes substantially 0 is to suppress the DC (direct current) component. It is known that DC suppression generally gives redundancy to a code string and lowers coding efficiency.

On the other hand, recently, for example, DVD (Digital
High-density optical disks such as Video Disk) have been developed. In this type of optical disc, there is a demand for increasing the recording capacity by reducing the redundancy of the code sequence even if the DC suppression for the recording code sequence is somewhat sacrificed. In this case, even if the DSV is approximately 0 in the sufficiently long section, the code string is D
SV does not become sufficiently close to 0, and has a so-called DSV offset.

FIG. 10 shows the slice level fluctuation characteristics obtained from the integration circuit 13 when the code string having the DSV offset is supplied to the input terminal 11 as a received signal. FIG. 10 shows a case where a signal in which a section with a small DSV offset and a section with a large DSV offset are mixed is input as a code string.

The waveform indicated by the symbol A in FIG. 10 shows the slice level fluctuation characteristics when the integration gain of the integration circuit 13 is set small, that is, when the time constant of the integration circuit 13 is set long. The waveform indicated by the symbol B indicates the slice level fluctuation characteristics when the integration gain of the integration circuit 13 is set large, that is, when the time constant of the integration circuit 13 is set short.

As is apparent from FIG. 10, even when a code string having the same DSV offset amount is received, a large difference occurs in the slice level depending on the magnitude of the integration gain of the integration circuit 13. The fact that a difference occurs in the slice level depending on the magnitude of the integration gain of the integration circuit 13 means that an error is generated with respect to the optimum slice level without taking any measures.

In this case, when the received signal is level-sliced at a slice level having an error with respect to the optimum level,
As can be inferred from FIG.
The probability that an error will occur in the quantified data will increase. Also, it is clear that the error is more likely to occur in the generated binary data as the slice level having a larger error amount than the optimum level is used.

Therefore, even when the DC suppression is not sufficiently performed, that is, even when a code string having a DSV offset is received, the integration gain of the integration circuit 13 is set to a sufficiently small value. By generating the slice level by sufficiently smoothing the output binary data, it is possible to reduce the amount of error from the optimal level and reduce the probability of occurrence of an error in the binary data. .

However, when playing back an optical disk, for example, when the amplitude of a signal (corresponding to the above-mentioned received signal) read from the disk fluctuates greatly due to a defect on the disk or a surface run-out of the disk, the optimum speed is improved. It is required to generate a slice level.

However, as described above, if the integration gain of the integration circuit 13 is set to a sufficiently small value, it takes a long time from the time when the amplitude of the disk reproduction signal fluctuates greatly to the time when an optimum slice level is generated. Since an interval signal is required, an optimum slice level cannot be obtained quickly, and there is a problem in that an error easily occurs in the binary data.

[0018]

As described above, in the conventional data slice circuit, in order to obtain an optimum slice level for a code string with insufficient DC suppression, it is necessary to set the integral gain sufficiently small. On the other hand, when the integration gain is set to be small, there is a problem that if the received signal level fluctuates greatly, it is not possible to quickly obtain an optimal slice level.

Therefore, the present invention has been made in view of the above circumstances, and it is possible to obtain an optimum slice level for a code string with insufficient DC suppression, and even if the received signal level fluctuates greatly, It is an object of the present invention to provide an extremely good data slice circuit capable of quickly controlling to an optimum slice level and a data reproducing apparatus using the same.

[0020]

A data slice circuit according to the present invention receives a digital bit stream controlled such that one polarity period is substantially equal to the other polarity period, and converts the received signal into a binary signal. It is intended to be converted to coded data.

Then, level comparing means for comparing the level of the received signal with a predetermined slice level to generate first binary data, and a first level output from the level comparing means.
Clock generating means for generating a clock phase-synchronized with the binarized data, and sampling the first binary data output from the level comparing means with the clock output from the clock generating means to generate a second binary data. A first means for detecting a difference between one polarity period and the other polarity period of the first binarized data output from the level comparing means, and outputting the difference as a first difference value; Difference value detecting means, and a second difference value detecting means for detecting a difference between one polarity period and the other polarity period of the second binary data outputted from the sampling means and outputting the difference as a second difference value. Means for calculating a difference between the first difference value output from the first difference value detection means and the second difference value output from the second difference value detection means, and outputting the calculated difference value as a third difference value Calculation means and sampling Detecting means for detecting the amount of error in the second binary data output from the stage, and a first difference value output from the first difference value detecting means based on a detection result of the error detecting means And a third difference value output from the calculating means, and a smoothing means for smoothing the first or third difference value selected by the selecting means and generating a slice level to be given to the level comparing means. And a conversion means.

According to the above configuration, the third difference value, which is the difference between the first difference value including the DSV offset of the transmission code string and the second difference value including only the DSV offset of the transmission code string. Is only a DSV deviation amount, which is an error generated in a slice level generated from a received signal because noise is added to a transmission code string on a transmission line. For this reason, by controlling the slice level based on the DSV deviation amount, it is possible to obtain an optimal slice level with high accuracy for a code string with insufficient DC suppression. Further, since the DSV deviation amount is accurately proportional to the slice level error amount, high-speed control becomes possible, and even when the received signal level largely fluctuates, an optimum slice level can be quickly obtained.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a first embodiment of the present invention will be described in detail with reference to the drawings. That is,
In FIG. 1, reference numeral 16 denotes an input terminal to which a received signal is supplied. The received signal supplied to the input terminal 16 is supplied to the positive input terminal + of the level comparison circuit 17. A slice level obtained from a DAC (Digital Analogue Converter) circuit 18 to be described later is applied to a negative input terminal − of the level comparison circuit 17.

The level comparing circuit 17 converts the binary data which becomes H level when the input level of the positive input terminal + is higher than the input level of the negative input terminal-, and otherwise becomes L level. Has been generated. The binarized data output from the level comparison circuit 17 is led through an output terminal 19 to a subsequent data processing system (not shown).

The binary data output from the level comparison circuit 17 is a PLL for generating a channel clock.
(Phase Locked Loop) circuit 20 and an input terminal D of a register 21 composed of a D (Delay) type FF (Flip-Flop) circuit. Further, the binary data output from the level comparison circuit 17 is
The signal is supplied to the enable terminal EN of the counter 22 and is inverted by the knot circuit 23 and supplied to the enable terminal EN of the counter 24.

The PLL circuit 20 generates a channel clock of a constant frequency which is phase-synchronized with the input binary data, and outputs the channel clock to the clock input terminal of the register 21. The register 21 generates binary data synchronized with the channel clock by sampling the binary data supplied to the input terminal D with the channel clock, and outputs the binary data from the output terminal Q.

Each of the counters 22 and 24 operates so as to count up the count clock of a constant frequency supplied to the input terminal 25 only while the H level is supplied to the enable terminal EN. That is, the counter 22 performs an up-counting operation during the H level period of the binary data output from the level comparison circuit 17, and the counter 24 performs the up counting operation during the L level period of the binary data output from the level comparison circuit 17. An up-count operation is performed.

Further, a reset signal is supplied to each of the counters 22 and 24 via an input terminal 26 at its clear end CL. These counters 2
Reference numerals 2 and 24 indicate that the count value is reset to 0 in synchronization with the rising edge of the first input count clock when the reset signal is at the L level.

The count output signal of the counter 22 is supplied to an input terminal D of a register 27 comprising a D-type FF circuit. The count output signal of the counter 24 is supplied to an input terminal D of a register 28 composed of a D-type FF circuit. These registers 27 and 2
8 have input terminals 2 at their clock input terminals, respectively.
9, a data latch signal is supplied. Each of the registers 27 and 28 latches the count output signal supplied to the input terminal D in synchronization with the data latch signal, and outputs the latched count output signal from the output terminal Q.

The latch output signal of the register 27 is
The signal supplied to the positive input terminal + of the adder circuit 30 is
Is supplied to the negative input terminal of the adder circuit 30. For this reason, the adder circuit 30
The count value of the counter 24 latched by the register 28 is subtracted from the count value of the counter 22 latched by 7 and the result of the subtraction is output.

That is, the output signal of the addition circuit 30 is a level comparison circuit 1 measured at the cycle of the reset signal.
7 is a difference component between the H level period and the L level period of the binarized data output from 7, that is, DSV.

On the other hand, 2 output from the register 21
The digitized data is supplied to a frame synchronization signal detection circuit 31 described later.
Is supplied to The binarized data output from the register 21 is supplied to the enable terminal EN of the counter 32.
, And inverted by the knot circuit 33 and supplied to the enable terminal EN of the counter 34.

Each of these counters 32 and 34 operates so as to count up the count clock supplied to the input terminal 25 only during the period when the H level is supplied to its enable terminal EN. That is, the counter 32 performs an up-counting operation during the H level period of the binary data output from the register 21, and the counter 34 performs the L counting of the binary data output from the register 21.
The up-count operation is performed during the level period.

Further, these counters 32 and 34 include:
Each of the clear terminals CL is supplied with a reset signal via the input terminal 26. These counters 32,
34 is a state where the reset signal is at the L level,
The count value is reset to 0 in synchronization with the rising edge of the first input count clock.

The count output signal of the counter 32 is supplied to an input terminal D of a register 35 composed of a D-type FF circuit. The count output signal of the counter 34 is supplied to an input terminal D of a register 36 composed of a D-type FF circuit. These registers 35, 3
6 have input terminals 2 at their clock input terminals, respectively.
9, a data latch signal is supplied. Each of the registers 35 and 36 latches the count output signal supplied to the input terminal D in synchronization with the data latch signal, and outputs the latched count output signal from the output terminal Q.

The latch output signal of the register 35 is
It is supplied to the positive input terminal + of the adder circuit 37,
Is supplied to the negative input terminal of the adder circuit 37. For this reason, the adder circuit 37 stores
The count value of the counter 34 latched by the register 36 is subtracted from the count value of the counter 32 latched by 5, and the result of the subtraction is output.

That is, the output signal of the adding circuit 37 is a difference component between the H-level period and the L-level period of the binary data output from the register 21 measured at the cycle of the reset signal, that is, DSV. ing.

Here, the output signal of the addition circuit 30 is
The signal is supplied to the positive input terminal + of the addition circuit 38 and to one input terminal of the selector 39. The output signal of the addition circuit 37 is supplied to the negative input terminal of the addition circuit 38. Therefore, the addition circuit 38 subtracts the subtraction result of the addition circuit 37 from the subtraction result of the addition circuit 30.

That is, the output signal of the addition circuit 38 is the level comparison circuit 1 measured at the cycle of the reset signal.
7 and the DSV of the binary data output from
This is a difference component from the DSV of the binarized data output from 1. The output signal of the adding circuit 38 is supplied to the other input terminal of the selector 39.

The selector 39 selectively outputs the output signal of the addition circuit 30 and the output signal of the addition circuit 37 based on the selection signal output from the frame synchronization signal detection circuit 31. That is, the frame synchronization signal detection circuit 31 detects the frame synchronization signal included in the binary data output from the register 21. When the frame synchronization signal is stably detected, the frame synchronization signal is detected.
A synchronization state flag signal which is at the L level otherwise is generated.

The frame synchronization signal detection circuit 3
The synchronization state flag signal output from 1 is supplied to the selector 39 as a selection signal. This selector 39
Operates to select the output signal of the adder circuit 38 when the H-level selection signal is being supplied and to select the output signal of the addition circuit 30 when the L-level selection signal is being supplied. I do.

The signal selected by the selector 39 is supplied to one input terminal of a multiplication circuit 40. A predetermined coefficient value is input to the other input terminal of the multiplication circuit 40 via an input terminal 41. And this multiplication circuit 4
0 is the value supplied from the selector 39 and the input terminal 41
And the multiplication result is output to one input terminal of the addition circuit 42.

The addition circuit 42 adds the value supplied from the multiplication circuit 40 and the value obtained from the output terminal Q of the register 43 composed of a D-type FF circuit, and
Output to the DAC circuit 18 and the register 43
Is output to the input terminal D. The register 43 time-shifts the output of the adder circuit 42 by a shift clock supplied to an input terminal 44 of the register 43 via an input terminal 44, and outputs the result to the adder circuit 42.

That is, the multiplying circuit 40, the adding circuit 42, and the register 43 constitute a smoothing circuit 45 for integrating and smoothing the output of the selector 39. The integral gain (time constant) of the smoothing circuit 54 is determined by the coefficient value supplied to the input terminal 41. And
The DAC circuit 18 generates a DC level corresponding to the output of the smoothing circuit 45, and outputs this as a slice level to the negative input terminal − of the level comparison circuit 17.

The operation of the data slice circuit configured as described above will be described below with reference to FIG. 2A to 2Q show waveforms at points (a) to (q) in FIG. 1, respectively. That is, when the level comparison circuit 17 outputs binary data as shown in FIG. 2A, the PLL circuit 20 outputs the binary data as shown in FIG.
Is output as shown in FIG. For this reason, as shown in FIG. 2C, the register 21 outputs binary data obtained by latching the binary data output from the level comparison circuit 17 at the rising edge of the channel clock.

Then, a count clock as shown in FIG. 2D is supplied to the input terminal 25, and the input terminal 26 is set at the L level for one cycle of the count clock at a period as shown in FIG. When the reset signal is supplied, the counter 22 counts the count clock during the H level period of the binary data output from the level comparison circuit 17 at the cycle of the reset signal as shown in FIG. Is counting up.

At the same time, the counter 24
As shown in (h), the count clock is counted up during the L level period of the binary data output from the level comparison circuit 17 in the cycle of the reset signal. When a data latch signal as shown in FIG. 2F is supplied to the input terminal 29, the registers 27 and 28 cause the rising edge of the data latch signal as shown in FIGS. To latch the outputs of the counters 22 and 24.

As a result, the addition circuit 30 outputs
As shown in (k), a value obtained by subtracting the count value latched by the register 28 from the count value latched by the register 27 is output.

As shown in FIG. 2 (l), the counter 32 counts up the count clock during the H level period of the binary data output from the register 21 in the cycle of the reset signal. At the same time, the counter 34
Is the cycle of the reset signal, as shown in FIG.
The count clock is counted up during the L level period of the binary data output from the register 21.

The registers 35 and 36 latch the outputs of the counters 32 and 34 at the rising edge of the data latch signal, respectively, as shown in FIGS.
As a result, the value obtained by subtracting the count value latched by the register 36 from the count value latched by the register 35 is output from the adder circuit 37, as shown in FIG. For this reason, the addition circuit 38 outputs the signal shown in FIG.
As shown in FIG.
7 is output.

Next, the frame synchronization signal detection circuit 31
Will be described with reference to FIG. That is,
FIG. 3A shows a transmission code string, and a hatched portion in the figure shows a frame synchronization signal. In the frame synchronization signal detection circuit 31, the 2
The frame synchronization signal included in the coded data is detected, and FIG.
In the state where the detection pulse as shown in (b) is generated and this detection pulse is stably obtained, the selector selects the H level synchronization state flag signal as shown in FIG. 39.

Here, FIG. 3 shows a case where the PLL circuit 20 is in an unlocked state, that is, a state in which the channel clock is changed from an asynchronous state to a synchronous state and then becomes an asynchronous state again. In this case, first, in the asynchronous state of the channel clock, since the frame synchronization signal detection circuit 31 cannot detect the frame synchronization signal, no detection pulse is generated.

Then, when the PLL circuit 20 is in the locked state, that is, in the synchronized state of the channel clock, the frame synchronization signal detection circuit 31 generates a detection pulse every time the frame synchronization signal is detected. Note that even in this synchronized state,
In some cases, the frame synchronization signal is not detected due to a code or the like. In such a case, the frame synchronization signal detection circuit 31
Does not generate a detection pulse.

Thereafter, when the channel clock is again in an asynchronous state, the frame synchronization signal detection circuit 31 cannot detect the frame synchronization signal, so that no detection pulse is generated.

Here, the frame synchronization signal detection circuit 31
Sets the synchronization state flag signal to the H level when the detection pulse is detected twice consecutively in a prescribed cycle. Then, even if there is a state where the detection pulse is not detected only once in the middle, the frame synchronization signal detection circuit 31 holds the synchronization state flag signal at the H level. Further, the frame synchronization signal detection circuit 31 sets the synchronization state flag signal to L level when the detection pulse is not detected twice consecutively in a prescribed cycle.

That is, the frame synchronization signal detection circuit 31 detects the frame synchronization signal included in the binary data output from the register 21 so that the binary data output from the register 21 has few errors. The state is determined. That is, when the frame synchronization signal is stably detected from the binary data output from the register 21, the frame synchronization signal detection circuit 31 determines that the binary data is in a state with few errors. In the state where the frame synchronization signal is not detected from the binary data output from the register 21, it is determined that the binary data is in a state with many errors. An L-level synchronization state flag signal is generated.

When the frame synchronization signal detection circuit 31 is generating the H-level synchronization state flag signal, a slice level is generated based on the output of the addition circuit 38, and the frame synchronization signal detection circuit 31 outputs the L level. In the state where the synchronization state flag signal is generated, the slice level is generated based on the output of the adder circuit 30.

Here, the DSV of the binary data output from the level comparison circuit 17 obtained from the addition circuit 30
Is because the noise on the transmission line is added to the transmission code sequence to the DSV offset amount included in the transmission code sequence described above.
The DSV deviation amount, which is an error generated in the slice level generated from the received signal, is added. Therefore, when the slice level is controlled based on the DSV output from the adding circuit 30, the following inconvenience occurs.

That is, FIG. 4A shows a transmission code string, and FIG. 4B shows the reception signal. In FIG. 4B, the level SL4 indicates an optimum slice level, and the level SL5 indicates an incorrect slice level. FIG. 4C shows an incorrect slice level S.
L5 shows binarized data obtained by level-slicing the received signal, and FIG. 4D shows a channel clock in a synchronized state.
FIG. 6E shows the binarized data obtained by sampling the binarized data with the channel clock.

In this case, within the time range shown in FIG. 4, the transmission code string has a DSV offset amount of +4 (the unit is a half cycle length of the channel clock). However, the DSV of the binary data obtained by level-slicing the received signal at the wrong slice level SL5 is 0. In other words, even though the slice level is incorrect, the DSV of the binarized data after level slicing becomes 0, and it becomes impossible to correct the incorrect slice level SL5. The reason for this is that the DSV offset amount of the transmission code string is equal to the DSV deviation amount due to the slice level error by sign inversion.

For this reason, when a transmission code string for which DC suppression is not sufficiently performed is received, controlling the slice level only by the DSV of the binary data output from the level comparison circuit 17 requires sufficient accuracy. You can't expect it.

On the other hand, the DSV of the binary data output from the register 21 is the DSV offset amount itself included in the transmission code sequence only when the binary data does not cause an error in the transmission code sequence. Becomes For this reason,
Only when the frame synchronization signal detection circuit 31 determines that the binary data output from the register 21 is in a state with few errors, the addition circuit 38 causes the addition circuit 3
The result of subtracting the output of the adder 37 from the output of 0 is only the DSV deviation amount due to the slice level error.

Thus, the frame synchronization signal detection circuit 3
When a selection signal of 1 to H level is output, by controlling the slice level based on the DSV deviation amount due to the slice level error output from the adding circuit 38,
An optimum slice level can be obtained with high accuracy for a code string for which DC suppression is not sufficient. Further, the addition circuit 3
Since the DSV deviation amount, which is the output of No. 8, is accurately proportional to the slice level error amount, high-speed control is possible, and even when the received signal level fluctuates greatly, the optimum slice level can be quickly obtained. .

Next, FIG. 5 shows a second embodiment of the present invention. 5, the same parts as those in FIG. 1 are denoted by the same reference numerals. The second embodiment shown in FIG. 5 differs from the first embodiment shown in FIG. 1 in that the frame synchronization signal detection circuit 31 is replaced with an error detection circuit 46, That is, it is determined whether the binarized data has many errors or not.

That is, if a predetermined error detection code is added to the transmission code string in advance, the error detection circuit 46
Detects an occurrence state of a data error based on the error detection code, and outputs an H-level selection signal when the error occurrence rate is equal to or less than a predetermined value, and generates an L-level selection signal otherwise. With such a configuration, the same effect as in the above-described first embodiment can be obtained.

FIG. 6 shows a third embodiment of the present invention. In FIG. 6, the same parts as those in FIG. 1 are denoted by the same reference numerals. The third shown in FIG.
The third embodiment differs from the first embodiment shown in FIG. 1 in that the frame synchronization signal detection circuit 31 is replaced with a data rate detection circuit 47. The data rate detection circuit 47 measures the data rate of the received signal from the binary data obtained from the level comparison circuit 17 and also measures the rate of the channel clock output from the PLL circuit 20.

The data rate detection circuit 47 compares the data rate of the received signal with the rate of the channel clock, and outputs an H-level selection signal when the error is equal to or less than a predetermined value. Generate a level selection signal. With such a configuration, the same effect as in the above-described first embodiment can be obtained.

Next, FIG. 7 shows an example of a reproducing apparatus for reproducing an optical disk such as a DVD as a data reproducing apparatus using the above-mentioned data slice circuit.
That is, reference numeral 48 in the figure denotes an optical disk, which is rotationally driven by a spindle motor 49. The information recorded on the optical disc 48 is read by the optical pickup 50 and output as a reproduction signal.

The reproduced signal output from the optical pickup 50 is supplied to an RF (Radio Frequency) amplifier circuit 51.
After being supplied to the data slice circuit 52, the focus servo circuit 53a and the tracking servo circuit 5a constituting the servo processing unit 53.
3b.

The data slice circuit 52 converts the input reproduction signal into binary data as described above, and then demodulates the demodulation circuit 54a constituting the reproduction signal processing section 54.
And the PLL circuit 54b. Then, the PLL circuit 54b generates a bit synchronization signal synchronized with the basic period of the binary data, and
And to the spindle servo circuit 53c.

The synchronization detection and protection unit 54c detects and protects a synchronization signal included in the binary data output from the data slice circuit 52 based on the input bit synchronization signal, and converts the detected synchronization signal. The signal is output to the demodulation circuit 54a. Then, at this time, the synchronization detection protection unit 5
The frame synchronization signal detected by 4c is output to the spindle servo circuit 53c.

Here, the demodulation circuit 54a demodulates the input binary data based on the synchronization signal output from the synchronization detection protection section 54c, and outputs this demodulated signal to the error correction circuit 54d. doing. The error correction circuit 54d performs an error detection process and a correction process on the input demodulated signal, and outputs the demodulated signal to the video / audio separation unit 56 using the cache memory 55. This cache memory 5
Reference numeral 5 performs an operation of temporarily storing data after error correction and an operation as a track buffer.

The video / sound separation unit 26 separates the demodulated signal sequence after error correction into a video signal and an audio signal.
The separated video signal is converted into an analog signal by a D / A (Digital / Analogue) converter 57 and is taken out as a video output. The separated audio signal is D
The signal is converted into an analog signal by the / A converter 58, and is taken out as an audio output.

On the other hand, the focus servo circuit 53a
Generates a focus control signal based on a reproduction signal output from the RF amplification circuit 51 in accordance with a control command from the servo control unit 59. The focus control signal drives the focus actuator 53e via the drive amplifier 53d, so that the focus (optical axis) direction of the objective lens (not shown) built in the optical pickup 50 is controlled. Become like

The tracking servo circuit 53b
Generates a tracking control signal based on a reproduction signal output from the RF amplification circuit 51 in accordance with a control command from the servo control unit 59. Then, the tracking control signal drives the tracking actuator 53g via the drive amplifier 53f, whereby the objective lens is controlled in the tracking (diameter of the optical disk 48) direction.

Further, the servo control section 59 controls the seek servo circuit 53h. The seek servo circuit 53h generates a seek control signal based on the tracking control signal output from the drive amplifier 53f. The seek control signal is supplied to the drive amplifier 5
By driving the pickup feed motor 53j through the optical pickup 3i, the optical pickup 50
8 in the tracking direction.

The spindle servo circuit 53c
Generates a spindle control signal based on a bit synchronization signal output from the PLL circuit 54b and a frame synchronization signal output from the synchronization detection protection unit 54c according to a control command from the servo control unit 59. The spindle control signal drives the spindle motor 49 via the drive amplifier 53k, whereby the rotation speed of the optical disk 48 is controlled.

Then, the servo control section 59 for controlling the servo processing section 53 and the reproduction signal processing section 54 form an MPU (Micro Process Control Unit) for totally controlling the operation of the entire reproduction apparatus.
ng Unit) 60 controls its operation.
It should be noted that the present invention is not limited to the above-described embodiments, and can be implemented with various modifications without departing from the scope of the present invention.

[0079]

As described in detail above, according to the present invention,
An extremely good data slice that can obtain an optimum slice level for a code string with insufficient DC suppression and can quickly control the optimum slice level even when a received signal level fluctuates greatly. A circuit and a data reproducing device using the circuit can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram showing a DSV detection operation in the first embodiment.

FIG. 3 is a view showing an operation of detecting a frame synchronization signal in the first embodiment.

FIG. 4 is a diagram showing a reason for detecting a frame synchronization signal in the first embodiment.

FIG. 5 is a block diagram showing a second embodiment of the present invention.

FIG. 6 is a block diagram showing a third embodiment of the present invention.

FIG. 7 is a block diagram showing an example of a data reproducing apparatus to which the present invention is applied.

FIG. 8 is a block diagram showing a conventional data slice circuit.

FIG. 9 is a diagram showing a slice level control operation in the conventional circuit.

FIG. 10 is a view for explaining a problem in the conventional circuit.

[Explanation of symbols]

 11: input terminal, 12: level comparison circuit, 13: integration circuit, 14: output terminal, 15: input terminal, 16: input terminal, 17: level comparison circuit, 18: DAC circuit, 19: output terminal, 20: PLL Circuit, 21 register, 22 counter, 23 knot circuit, 24 counter, 25, 26 input terminal, 27, 28 register, 29 input terminal, 30 addition circuit, 31 frame synchronization signal detection circuit, 32 counter, 33 knot circuit, 34 counter, 35, 36 register, 37, 38 addition circuit, 39 selector, 40 multiplication circuit, 41 input terminal, 42 addition circuit, 43 register, 44 ... Input terminal, 45 ... Smoothing circuit, 46 ... Error detection circuit, 47 ... Data rate detection circuit, 48 ... Optical disk, 49 ... Spindle mode 50, an optical pickup, 51, an RF amplifier circuit, 52, a data slice circuit, 53, a servo processing unit, 54, a reproduction signal processing unit, 55, a cache memory, 56, a video sound separation unit, 57, 58, D / A converter, 59: servo controller, 60: MPU.

Claims (8)

[Claims] 1. A data slice circuit for receiving a digital bit stream controlled so that one polarity period is substantially equal to the other polarity period, and converting the received signal into binary data. Level comparing means for comparing the level with a predetermined slice level to generate first binary data; and a clock for generating a clock phase-synchronized with the first binary data output from the level comparing means. Generating means; sampling means for sampling first binary data output from the level comparing means with a clock output from the clock generating means to generate second binary data; The difference between one polarity period and the other polarity period of the first binary data output from the means is detected, and the first binary data is detected.
A first difference value detecting means for outputting a difference value between the first and second polarity data, and a difference between one polarity period and the other polarity period of the second binarized data outputted from the sampling means. A second difference value detecting means that outputs the first difference value, and a difference between a first difference value output from the first difference value detecting means and a second difference value output from the second difference value detecting means. Calculating means for calculating the difference value and outputting the result as a third difference value; detecting means for detecting the amount of error in the second binarized data output from the sampling means; Selecting means for selecting a first difference value output from the first difference value detecting means and a third difference value output from the calculating means, and selecting the first or second signal selected by the selecting means. Level comparing means for smoothing the difference value Data slice circuit characterized by comprising comprises a smoothing means for generating a slice level to provide. 2. The method according to claim 1, wherein the selecting unit outputs the error from the arithmetic unit when an error occurrence amount of the second binarized data output from the sampling unit detected by the detecting unit is equal to or less than a predetermined value. Select a third difference value, and if not, select a first difference value output from the first difference value detecting means.
2. The data slice circuit according to claim 1, wherein the difference value is selected. 3. The detecting means according to claim 1, wherein a ratio between a state in which the synchronization signal included in the second binarized data output from the sampling means is stably obtained at a prescribed period and a state in which the synchronization signal is not obtained. 2. The data slice circuit according to claim 1, wherein an error occurrence amount of the second binarized data is detected based on the following equation. 4. The detection means detects an error occurrence amount of the second binary data based on an error detection code included in the second binary data output from the sampling means. The data slice circuit according to claim 1, wherein: 5. The sampling means compares the data rate of the first binarized data output from the level comparison means with the rate of a clock output from the clock generation means. The second output from
2. The data slice circuit according to claim 1, wherein the amount of error in the binarized data is detected. 6. The method according to claim 1, wherein the first difference value detecting means outputs a count clock having a constant frequency for a predetermined period.
The value counted during only one polarity period of the first binarized data output from the level comparing means, and the count clock during the fixed period, are output by the first binary data output from the level comparing means. 2. The data slice circuit according to claim 1, wherein a difference between the value data and a value counted only during the other polarity period is detected. 7. The method according to claim 6, wherein the second difference value detecting means is configured to output a count clock having a constant frequency for a predetermined period.
The value counted during only one polarity period of the second binarized data output from the sampling means, and the count clock during the fixed period is changed to the second binary data output from the sampling means. 2. The data slice circuit according to claim 1, wherein a difference from a value counted during only the other polarity period of the data is detected. 8. The data slice circuit according to claim 1,
A data reproducing apparatus comprising: a demodulating means for demodulating the first binary data outputted from the level comparing means of the data slice circuit.