JPH1167938A - Manufacturing method of semiconductor nonvolatile memory device - Google Patents

Abstract

(57) [Summary] A gate insulating film of a memory transistor and a gate insulating film of a select transistor having different film thicknesses can be formed by shortening a processing step of the gate insulating film, and a pattern density can be reduced. And a method for manufacturing a semiconductor nonvolatile memory device. In a memory transistor formation region and a selection transistor formation region, gate insulating films (20a, 20b) are formed above a channel formation region formed in a semiconductor substrate (10).
Are formed thereon, charge storage layers 30a and 30b are formed thereon, control gates 31a and 31b are formed thereon, and a mask layer 23 covering at least a memory transistor formation region is formed. The thickness of the gate insulating film 20c in the select transistor formation region is increased, and source / drain regions are formed in the memory transistor formation region and the select transistor formation region.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor nonvolatile memory device and a method of manufacturing the same, and more particularly, to a semiconductor nonvolatile memory device having a charge storage layer between a gate electrode of a transistor and a channel forming region, and a method of manufacturing the same. .

[0002]

2. Description of the Related Art Instead of a magnetic storage device such as a floppy disk, an electrically rewritable semiconductor nonvolatile storage device (EEPROM: Electrically Erasable and Prog
rammable ROM) has begun to be used. As an EEPROM, a floating gate type, MNOS type or M
Structures having various features such as an ONOS type and a TEXTURED POLY type have been developed.

FIG. 6 shows a plan view of a NAND type semiconductor nonvolatile memory device having a floating gate structure, which is one of the EEPROMs. For example, an active region of a silicon semiconductor substrate separated by an element isolation insulating film I such as a LOCOS film and a control gate CG serving as a word line
At the intersection (shaded portion in FIG. 6) of the floating gate FG as a charge storage layer between the control gates CG1, CG2, CG3 and the channel formation region of the silicon semiconductor substrate. Source / drain diffusion layers SD are formed in the substrate on both sides of the control gates CG1, CG2, and CG3, thereby forming memory transistors MT1, MT2, and MT3, which are field-effect transistors.

The above-mentioned control gates CG1, CG
2, a selection gate SG is formed in parallel with CG3,
NA formed by connecting memory transistors in series
At the end of the ND column, a selection transistor ST is formed at an intersection with the active region of the silicon semiconductor substrate.
Here, as the source / drain diffusion layer of the selection transistor ST, the concentration of the conductive impurity in the source / drain diffusion layer SD on the memory transistor side in the internal region surrounded by MSD in FIG. The concentration is the same as that of the drain diffusion layer SD, and is set lower than that of the source / drain diffusion layer SD ′ which is not on the memory transistor side. Further, the selection gate SG is connected to an upper layer wiring or the like through a word shunt contact, and is processed to form a peripheral circuit using the mask MOC as a mask, for example.

In FIG. 6, in a region where a memory transistor is formed, which is an inner region surrounded by MGO, charge is injected from a semiconductor layer to a floating gate through a gate insulating film, or a semiconductor is transferred from a floating gate to a semiconductor. The thickness of the gate insulating film is designed to be thin so that data can be stored by discharging charges to the layer, and a Fowler-Nordheim tunnel current is generated. On the other hand, in the region where the select transistor and the like are formed (the region outside the MGO in the figure), the above-mentioned Fowler-Nordheim tunnel current occurs, and charges are injected into the floating gate formed below the select gate. The thickness of the gate insulating film is designed to be large so as not to be performed.

[0006] Regarding the above-mentioned semiconductor nonvolatile memory device,
FIG. 7 is a sectional view taken along line YY ′ of FIG. Memory transistors MT1 and MT2 are formed in a region on the right side in the drawing. A gate insulating film (tunnel insulating film) 20a made of, for example, a thin silicon oxide is formed on the silicon semiconductor substrate 10, and a floating gate 30a made of, for example, polysilicon is formed thereon. An intermediate insulating film 21a made of, for example, an ONO film (a stacked insulating film of an oxide film-nitride film-oxide film) is formed thereon, and a control gate 31a made of, for example, polysilicon is formed thereover. The floating gate 30a, the intermediate insulating film 21a, and the control gate 31a are covered with an upper insulating film 22 made of, for example, silicon oxide. In the semiconductor substrate 10 on both sides of the control gate 31a,
A source / drain diffusion layer 11 is formed. As described above, the floating gate 30a covered with the insulating film is provided between the control gate 31a and the channel formation region.
Are formed, and the memory transistors MT1 and MT2 can store data by storing charges in the floating gate 30a.

On the other hand, a select transistor ST is formed in a left area in the drawing. Silicon semiconductor substrate 10
A gate insulating film 25a made of, for example, silicon oxide and having a thickness greater than that of the gate insulating film (tunnel oxide film) of the memory transistor is formed thereon, and a floating gate 30b made of, for example, polysilicon is formed thereon. . An intermediate insulating film 21b made of, for example, an ONO film (a stacked insulating film of an oxide film-nitride film-oxide film) is formed thereon, and a control gate 31b made of, for example, polysilicon is formed thereover. The floating gate 30b, the intermediate insulating film 21b, and the control gate 31b are covered with an upper insulating film 22 made of, for example, silicon oxide. The semiconductor substrate 10 on the memory transistor side of the control gate 31b has a source / drain containing the same concentration of conductive impurities as the source / drain diffusion layers of the memory transistor.
A drain diffusion layer 11 is formed, and a source / drain diffusion layer 12 containing a conductive impurity having a higher concentration than the source / drain diffusion layer of the memory transistor is formed in a semiconductor substrate 10 opposite to the memory transistor. Is formed. As described above, the field effect transistor having the floating gate 30b covered with the insulating film between the control gate 31b and the channel formation region is formed. However, since the gate insulating film 25a is thick,
It is difficult to generate a Filer-Nordheim type tunnel current, and it is difficult to inject charges into the floating gate 30b through the gate insulating film 25a or to release charges from the floating gate 30b. However, the selection transistor ST performs the same function as a normal MOS transistor.

A method for manufacturing a semiconductor nonvolatile memory device having the above structure will be described with reference to the drawings. First, as shown in FIG.
Then, an element isolation insulating film (not shown) made of silicon oxide is formed by, for example, the LOCOS method. Next, a silicon oxide layer 24 is formed on the entire surface by covering the active region serving as a channel formation region separated by the element isolation insulating film, for example, by a thermal oxidation method. Here, in the drawing, the right region indicates a memory transistor formation region, and the left region indicates a selection transistor formation region. The thickness is set to a thickness corresponding to the difference between the thicknesses of the gate insulating film (tunnel insulating film) of the memory transistor and the gate insulating film of the select transistor.

Next, a resist film having a gate insulating film forming pattern MGO shown in FIG. 6 and protecting a selection transistor forming region and the like is formed, and etching such as RIE (reactive ion etching) is performed. As shown in b), the silicon oxide layer 24a in the select transistor formation region
To remove the silicon oxide layer in the memory transistor formation region. At this time, since the end of the pattern MGO is a boundary between the memory transistor and the select transistor, the distance C ′ from the end of the select gate SG to the end of the pattern MGO and the pattern MGO are shown in FIGS.
Are formed such that the distance D ′ from the end of the control gate CG1 to the end of the control gate CG1 falls within a predetermined range.

Next, as shown in FIG. 8C, a silicon oxide layer is formed on the entire surface by, for example, a thermal oxidation method, and a gate insulating film (tunnel insulating film) 20 is formed in a memory transistor forming region and selected. The thickness of the silicon oxide layer 24a is increased in the transistor formation region, and a gate insulating film 25 for a select transistor is formed.

Next, as shown in FIG.
Polysilicon is deposited on the entire surface of the gate insulating film (tunnel insulating film) 20 and the gate insulating film 25 by the VD method to form a floating gate layer 30, and the floating gate pattern mask MFG shown in FIG. 6 is used as a mask. Etching such as RIE is performed to remove the floating gate layer in the upper layer of the element isolation insulating film to form a floating gate layer separated in the control gate direction. Next, an ONO film (a stacked insulating film of an oxide film, a nitride film, and an oxide film) is deposited on the floating gate layer 30 by, for example, a CVD method, and the intermediate insulating film 21 is formed.
To form Next, polysilicon is deposited by, for example, a CVD method to form a control gate layer. Next, a resist film R of a control gate and a select gate pattern is formed by a photolithography process.

Next, as shown in FIG. 9 (e), etching such as RIE is performed along the resist film R to form floating gates 30a and 30b having control gate and select gate patterns, and intermediate insulating films 21a and 21.
b and control gates 31a and 31b are formed. Next, silicon oxide is deposited on the entire surface by, for example, a CVD method, and an upper insulating film 22 is formed.

Next, conductive impurities are ion-implanted using the mask layer formed along the source / drain diffusion layer formation pattern MSD in FIG. 6 as a mask to form a source / drain diffusion layer 11 of the memory transistor. Next, conductive impurities are ion-implanted using the mask layer formed by inverting the negative / positive characteristics along the pattern MSD as a mask to form the source / drain diffusion layer 12 on the side other than the memory transistor side of the selection transistor. Here, as shown in FIGS. 6 and 7, the end of the source / drain diffusion layer formation pattern MSD is formed on the selection gate SG. For this purpose, the distance A ′ from the end of the select gate on the side other than the memory transistor side to the pattern MSD,
The distance B ′ from the end of the select gate on the memory transistor side to the pattern MSD is formed to fall within a predetermined range. At this time, the source / drain diffusion layer 11 of the memory transistor is formed with a low concentration of conductive impurities in order to keep the transistor characteristics constant. Is preferably small, and the conductive impurities are formed at a high concentration. As described above, a semiconductor nonvolatile memory device having the memory transistors MT1 and MT2 and the selection transistor ST as shown in FIG. 7 can be formed.

In the above-described conventional method for forming a semiconductor nonvolatile memory device, a structure having a floating gate below the select gate is used because the gate electrode of the memory transistor and the select gate of the select transistor are processed in the same step. Becomes Thereby, the arrangement density can be increased. In addition, if charge injection occurs to the floating gate below the select gate, the memory cell cannot be selected by the select gate, so the gate insulating film under the floating gate is made thicker and a Fowler-Nordheim tunnel current is generated. I try not to.

[0015]

However, in the above-mentioned conventional method of forming a semiconductor nonvolatile memory device,
Gate insulating film of memory transistor (tunnel insulating film)
Since the gate insulating film of the select transistor is formed with a different thickness, the process of processing the gate insulating film is lengthened, which is one of the causes of an increase in manufacturing cost.

Further, in order to make the thicknesses of the gate insulating film (tunnel insulating film) of the memory transistor and the gate insulating film of the select transistor different, a gate insulating film forming pattern M
A resist film having GO and protecting a selection transistor formation region and the like is formed. At this time, it is necessary to form the end of the pattern MGO so as to be a boundary between the memory transistor and the selection transistor. 6 and 7, a distance C ′ from the end of the selection gate SG to the end of the pattern MGO and a distance D ′ from the end of the pattern MGO to the end of the control gate CG1 are respectively within predetermined ranges. It must be formed to fit within. For this reason, alignment accuracy of a mask or the like is required, and an alignment margin is required, which is an obstacle to reduction in pattern density and miniaturization of an apparatus.

The present invention has been made in view of the above-mentioned problems, and accordingly, the present invention provides a gate insulating film (tunnel insulating film) for memory transistors having different film thicknesses by shortening the processing steps of the gate insulating film. Semiconductor that can form a gate insulating film for a select transistor and a select transistor, and does not require a margin for pattern alignment for forming a gate insulating film to make the film thickness different, enabling a reduction in pattern density and miniaturization of devices. An object of the present invention is to provide a method for manufacturing a nonvolatile memory device.

[0018]

In order to achieve the above object, a semiconductor nonvolatile memory device according to the present invention comprises a memory transistor having a charge storage layer and a selection transistor for selecting the memory transistor. A method of manufacturing a storage device, comprising: forming a gate insulating film on a channel formation region formed in a semiconductor substrate in a memory transistor formation region and a selection transistor formation region; and forming the memory transistor formation region and the selection transistor formation Forming a charge storage layer above the gate insulating film in the region; and forming the charge transistor in the memory transistor forming region and the select transistor forming region.
Forming a control gate above the charge storage layer; forming a mask layer covering at least the memory transistor formation region; and forming a thick gate insulating film in the select transistor formation region using the mask layer as a mask. And forming a source / drain region in the memory transistor formation region and the select transistor formation region.

According to the method of manufacturing a semiconductor nonvolatile memory device of the present invention, a gate insulating film is formed on a semiconductor layer having a channel forming region formed on a substrate in a memory transistor forming region and a select transistor forming region. Then, a charge storage layer is formed thereon, and a control gate is formed thereabove. Next, a mask layer covering at least the memory transistor formation region is formed, and the gate insulating film in the selection transistor formation region is thickened using the mask layer as a mask. Next, in the memory transistor formation region and the selection transistor formation region, the source
Forming a drain region; As described above, in the memory transistor formation region, a memory transistor having a charge storage layer between the channel formation region and the control gate and storing data by storing charge in the charge storage layer can be formed. In the select transistor formation region, a charge storage layer is provided between the channel formation region and the control gate, but charge injection or discharge is performed by having a gate insulating film thicker than the gate insulating film of the memory transistor. Is difficult and practically
A selection transistor which performs the same function as the S transistor can be formed.

According to the method of manufacturing a semiconductor nonvolatile memory device of the present invention, the gate electrode of the memory transistor having the charge storage layer and the select gate of the select transistor are processed in the same step. A structure having a charge storage layer (for example, a floating gate) underneath is provided, and the arrangement density can be increased. The gate insulating film of the select transistor is thickened after forming each gate electrode. As a result, the gate insulating film (tunnel insulating film) of the memory transistor and the gate insulating film of the select transistor having different thicknesses can be formed by shortening the processing steps of the gate insulating film, and the gate insulating films having different thicknesses can be formed. Since it is not necessary to form a pattern for the formation, a margin for the alignment is not necessary, so that the pattern density can be reduced and the device can be downsized.

In the above method of manufacturing a semiconductor nonvolatile memory device according to the present invention, preferably, the step of increasing the thickness of the gate insulating film in the select transistor formation region performs a thermal oxidation process using the mask layer as a mask. It is a process. This allows
The thickness of the gate insulating film in the select transistor formation region can be increased, and the gate insulating film processing step can be shortened to reduce the gate insulating film (tunnel insulating film) of the memory transistor and the gate insulating film of the select transistor having different film thicknesses. Can be formed.

In the method of manufacturing a semiconductor non-volatile memory device according to the present invention, the step of forming the mask layer preferably includes the step of: This is a step of covering and forming the entire memory transistor formation region. As a result, the mask layer formation pattern and the source
The drain region formation pattern can also be used, so that the number of masks can be reduced and the number of steps can be reduced.

In the method of manufacturing a semiconductor non-volatile memory device according to the present invention, preferably, the step of forming the mask layer includes the same pattern as a layer serving as a mask for forming the source / drain regions. This is the step of forming. Thus, the number of masks can be reduced, and the number of steps can be further reduced.

In the method of manufacturing a semiconductor nonvolatile memory device according to the present invention, preferably, the step of forming the charge storage layer is a step of forming a floating gate using a conductive material. After the forming step, before the step of forming the control gate, the method further includes a step of forming an intermediate insulating film. As a result, a floating gate type semiconductor nonvolatile memory device that accumulates charges in the floating gate can be formed.

In the method for manufacturing a semiconductor nonvolatile memory device according to the present invention, preferably, the step of forming the charge storage layer is a step of forming an insulating film having a charge trap level. As an insulating film having this charge trap level,
A laminated insulating film composed of a silicon nitride layer and a silicon oxide layer,
It can be an insulating film made of a silicon nitride layer. This makes it possible to provide a semiconductor non-volatile memory device that accumulates charges in an insulating film of a MONOS type or an MNOS type.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a semiconductor nonvolatile memory device and a method of manufacturing the same according to the present invention will be described below with reference to the drawings.

First Embodiment FIG. 1 is a plan view showing a NAND type semiconductor nonvolatile memory device according to this embodiment having a floating gate structure. For example, an active region of a silicon semiconductor substrate separated by an element isolation insulating film I such as a LOCOS film;
Control gates CG1, CG2, C that become word lines
At the intersection with G3 (the hatched portion in FIG. 1), a floating gate FG is formed as a charge storage layer between the control gates CG1, CG2, CG3 and the channel formation region of the silicon semiconductor substrate. Source / drain diffusion layers SD are formed in the substrate on both sides of the control gates CG1, CG2, and CG3.
Memory transistor MT which is a field effect transistor
1, MT2 and MT3 are formed.

The above control gates CG1, CG
2, a selection gate SG is formed in parallel with CG3,
NA formed by connecting memory transistors in series
At the end of the ND column, a selection transistor ST is formed at an intersection with the active region of the silicon semiconductor substrate.
Here, as the source / drain diffusion layer of the selection transistor ST, the concentration of the conductive impurity of the source / drain diffusion layer SD on the memory transistor side in the internal region surrounded by MSD in FIG. The concentration is the same as that of the drain diffusion layer SD, and is set lower than that of the source / drain diffusion layer SD ′ which is not on the memory transistor side. Further, the selection gate SG is connected to an upper layer wiring or the like through a word shunt contact, and is processed to form a peripheral circuit using the mask MOC as a mask, for example.

In FIG. 1, in a region where a memory transistor is formed, data is injected by passing a charge from a semiconductor layer to a floating gate through a gate insulating film or discharging a charge from the floating gate to a semiconductor layer. The thickness of the gate insulating film is designed to be thin so that it can be stored, and a Fowler-Nordheim tunnel current is generated. On the other hand, in the region where the select transistor is formed, the gate insulating film is formed so that the above-mentioned Fowler-Nordheim tunnel current does not occur and charges are injected into the floating gate formed below the select gate. Is designed to be thick.

With respect to the above semiconductor nonvolatile memory device,
FIG. 2 is a sectional view taken along line XX ′ of FIG. Memory transistors MT1 and MT2 are formed in a region on the right side in the drawing. A gate insulating film (tunnel insulating film) 20a made of, for example, a thin silicon oxide is formed on the silicon semiconductor substrate 10, and a floating gate 30a made of, for example, polysilicon is formed thereon. An intermediate insulating film 21a made of, for example, an ONO film (a stacked insulating film of an oxide film-nitride film-oxide film) is formed thereon, and a control gate 31a made of, for example, polysilicon is formed thereover. The floating gate 30a, the intermediate insulating film 21a, and the control gate 31a are covered with an upper insulating film 22 made of, for example, silicon oxide. In the semiconductor substrate 10 on both sides of the control gate 31a,
A source / drain diffusion layer 11 is formed. As described above, the floating gate 30a covered with the insulating film is provided between the control gate 31a and the channel formation region.
Are formed, and the memory transistors MT1 and MT2 can store data by storing charges in the floating gate 30a.

On the other hand, a select transistor ST is formed in a left area in the drawing. Silicon semiconductor substrate 10
A gate insulating film 20c made of, for example, silicon oxide and having a thickness greater than that of the gate insulating film (tunnel oxide film) of the memory transistor is formed thereon, and a floating gate 30b made of, for example, polysilicon is formed thereon. . An intermediate insulating film 21b made of, for example, an ONO film (a stacked insulating film of an oxide film-nitride film-oxide film) is formed thereon, and a control gate 31b made of, for example, polysilicon is formed thereover. The floating gate 30b, the intermediate insulating film 21b, and the control gate 31b are covered with an upper insulating film 22 made of, for example, silicon oxide. The semiconductor substrate 10 on the memory transistor side of the control gate 31b has a source / drain containing the same concentration of conductive impurities as the source / drain diffusion layers of the memory transistor.
A drain diffusion layer 11 is formed, and a source / drain diffusion layer 12 containing a conductive impurity having a higher concentration than the source / drain diffusion layer of the memory transistor is formed in the semiconductor substrate 10 opposite to the memory transistor. Is formed. As described above, the field effect transistor having the floating gate 30b covered with the insulating film between the control gate 31b and the channel formation region is formed. However, since the thickness of the gate insulating film 20c is large,
It is difficult to generate a Filer-Nordheim type tunnel current, and it is difficult to inject charges into the floating gate 30b through the gate insulating film 20c or to release charges from the floating gate 30b. However, the selection transistor ST performs the same function as a normal MOS transistor.

A method for manufacturing a semiconductor nonvolatile memory device having the above structure will be described with reference to the drawings. Here, in the drawing, the right region indicates a memory transistor formation region, and the left region indicates a selection transistor formation region. First, as shown in FIG. 3A, an element isolation insulating film (not shown) made of silicon oxide is formed on the silicon semiconductor substrate 10 by, for example, the LOCOS method. next,
A gate insulating film (tunnel insulating film) 20 is formed on the entire surface by covering the active region serving as a channel formation region separated by the element isolation insulating film by, for example, a thermal oxidation method. Next, a gate insulating film (tunnel insulating film) 20 is formed by, for example, a CVD method.
Polysilicon is deposited on the entire surface of the upper layer to form a floating gate layer 30, and RIE is performed using the floating gate pattern mask MFG shown in FIG. 1 as a mask.
(Reactive ion etching)
The floating gate layer 30 separated in the control gate direction is formed by removing the floating gate layer in the upper layer of the element isolation insulating film.

Next, an ONO film (oxide film-nitride film) is formed on the floating gate layer 30 by, for example, a CVD method.
Then, an intermediate insulating film 21 is formed. Next, polysilicon is deposited by, for example, a CVD method to form a control gate layer. Next, a resist film R of a control gate and a select gate pattern is formed by a photolithography process.

Next, as shown in FIG. 3B, etching such as RIE is performed along the resist film R, and floating gates 30a and 30b having control gate and select gate patterns, and intermediate insulating films 21a and 21 are formed.
b and control gates 31a and 31b are formed. Next, silicon oxide is deposited on the entire surface by, for example, a CVD method, and an upper insulating film 22 is formed.

Next, as shown in FIG.
Silicon nitride is deposited on the entire surface by a VD method to a thickness of 10 nm, and the source / drain diffusion layer forming pattern M
By patterning along the SD, a mask layer 23 covering a part of the control gate of the select transistor on the memory transistor formation region side and the entire memory transistor formation region is formed.

Next, as shown in FIG. 4D, thermal oxidation treatment is performed, for example, in steam at 900 ° C. for 15 minutes to form a thicker gate insulating film 20c in the select transistor formation region. Since thermal oxidation is performed using the mask layer 23 as a mask, the memory transistor formation region is protected and thermal oxidation is not performed. On the other hand, in the select transistor formation region, oxidation gradually progresses from the outside of the mask layer, the gate insulating film in the select transistor formation region becomes thicker, and the thickened tip portion becomes a bird's beak BB. The length of the bird's beak BB varies depending on the thickness of the mask layer, but is, for example, 100 nm. At this time,
It is sufficient until the bird's beak BB reaches the memory transistor side end of the floating gate 30b of the selection transistor so that at least the gate insulating film of the selection transistor formation region does not remain as thin as the gate insulating film 20a of the memory transistor formation region. Is oxidized.
At this time, the upper insulating film of the select transistor formation region also becomes thicker.

Next, conductive impurities are ion-implanted using the layer formed along the source / drain diffusion layer formation pattern MSD in FIG. 1 as a mask to form the source / drain diffusion layer 11 of the memory transistor. Using the layer formed by inverting the negative / positive characteristics along the pattern MSD as a mask, conductive impurities are ion-implanted to form the source / drain diffusion layer 12 which is not on the memory transistor side of the selection transistor. At this time, the source / drain diffusion layer 11 of the memory transistor is formed with a low concentration of conductive impurities in order to keep the transistor characteristics constant. Is preferably small, and the conductive impurities are formed at a high concentration. At this time, as a mask, the layer of the source / drain diffusion layer forming pattern MSD is formed on the select gate SG as shown in FIGS. As described above, a semiconductor nonvolatile memory device having the memory transistors MT1 and MT2 and the selection transistor ST shown in FIG. 2 can be formed.

According to the method of manufacturing the semiconductor nonvolatile memory device of the present embodiment, the gate electrode of the memory transistor having the floating gate and the select gate of the select transistor are processed in the same step. It has a structure with a floating gate at the bottom,
The arrangement density can be increased. Since the gate insulating film of the select transistor is thickened after each gate electrode is formed, the process of processing the gate insulating film is shortened, and the gate insulating film (tunnel insulating film) of the memory transistor having a different thickness is formed.
And a gate insulating film of the select transistor. Further, since it is not necessary to form a pattern for forming a gate insulating film having a different film thickness as in the related art, a margin for the alignment is not required, and the pattern density can be reduced and the device can be downsized. In addition, by using both the pattern for forming the mask layer and the pattern for forming the source and drain regions when the thickness of the gate insulating film in the select transistor formation region is increased, the number of masks can be reduced, and the number of steps can be further reduced. can do.

Second Embodiment A plan view of a semiconductor nonvolatile memory device of this embodiment is substantially the same as that of the first embodiment. FIG. 5 is a cross-sectional view of the semiconductor nonvolatile memory device according to the present embodiment. Although substantially the same as the cross-sectional view of the semiconductor nonvolatile memory device of the first embodiment, the mask layer 23 covers the memory transistor region but is formed so as not to reach the select gate of the select transistor. It is. For this reason, when thickening the gate insulating film of the select transistor, bird's beaks enter from both the memory transistor side of the select transistor and the opposite side, and finally the floating gate 30b
The gate insulating film 20c having a uniform thickness is formed under the lower layer. For this reason, the bird's beak BB is formed below the end of the mask layer 23 formed in the region between the memory transistor and the select transistor.

The semiconductor nonvolatile memory device according to the present embodiment can be manufactured substantially in the same manner as in the first embodiment. Accordingly, since the gate electrode of the memory transistor having the floating gate and the select gate of the select transistor are processed in the same step, the structure has the floating gate below the select gate, and the arrangement density can be increased. . Since the gate insulating film of the select transistor is thickened after forming each gate electrode,
By shortening the processing steps of the gate insulating film, the gate insulating films (tunnel insulating films) of the memory transistors having different thicknesses and the gate insulating films of the select transistors can be formed. Further, since it is not necessary to form a pattern for forming a gate insulating film having a different film thickness as in the related art, a margin for the alignment is not required, and the pattern density can be reduced and the device can be downsized.

The semiconductor nonvolatile memory device and the method of manufacturing the same according to the present invention are not limited to the above embodiment. For example, the control gate electrode has a single layer, but may have a multilayer structure such as polycide. As the charge storage layer, in addition to a floating gate, an MNOS type, MON, which stores charge in a charge trap level in a silicon nitride layer or a stacked insulating film of a silicon nitride layer and a silicon oxide layer,
It may be an OS type or the like. The floating gate may have a single-layer structure or a multilayer structure. Further, the source / drain diffusion layers may have various structures such as an LDD structure. The semiconductor memory device is not limited to the NAND type, but may be a NOR type.
And DINOR type. The injection of charges into the charge storage layer may be performed in any case of writing or erasing data. In addition, various changes can be made without departing from the gist of the present invention.

[0042]

According to the method for manufacturing a semiconductor nonvolatile memory device of the present invention, the gate insulating film (tunnel insulating film) of the memory transistor and the gate of the select transistor having different film thicknesses are shortened by shortening the processing steps of the gate insulating film. A semiconductor non-volatile memory device that can form an insulating film, does not require a margin for pattern alignment for forming a gate insulating film having a different thickness, and can reduce the pattern density and the size of the device. Can be manufactured.

[Brief description of the drawings]

FIG. 1 is a plan view of a semiconductor nonvolatile memory device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of the semiconductor nonvolatile memory device according to the first embodiment of the present invention.

FIGS. 3A and 3B are cross-sectional views showing a manufacturing process of the method for manufacturing the semiconductor nonvolatile memory device shown in FIGS. 2A and 2B; FIG. 3A is a diagram up to a resist film forming process; FIG. The process is shown.

FIG. 4 is a cross-sectional view showing a step subsequent to that of FIG. 3; (c) shows up to a mask layer forming step; and (d) shows a gate insulating film thickening step in a select transistor formation region. Is shown.

FIG. 5 is a sectional view of a semiconductor nonvolatile memory device according to a second embodiment of the present invention.

FIG. 6 is a plan view of a semiconductor nonvolatile memory device according to a conventional method.

FIG. 7 is a sectional view of a semiconductor nonvolatile memory device according to a conventional method.

8A and 8B are cross-sectional views illustrating a manufacturing process of the method for manufacturing the semiconductor non-volatile memory device shown in FIG. 7; FIG. 8A is a diagram up to a silicon oxide layer forming process; (C) up to the step of forming the gate insulating film.

FIG. 9 (d) shows the process up to the step of forming a resist film.
(E) shows the process up to the step of forming the upper insulating film.

[Explanation of symbols]

Reference Signs List 10: semiconductor substrate, 11 (SD): source / drain diffusion layer, 12 (SD '): high-concentration source / drain diffusion layer, 20, 20a, 20b, 20c, 25, 25a: gate insulating film, 21, 21a, 21b ... intermediate insulating film, 2
2, 22a: Upper insulating film, 23: Mask layer, 24, 24
a: silicon oxide layer, 30: floating gate layer, 30a, 30b (FG): floating gate,
31 ... Control gate layer, 31a, 31b (CG
1, CG2, CG3): control gate, R: resist film, BB: bird's beak, MT1, MT2: memory transistor, ST: select transistor, I: element isolation insulating film.

Claims (8)

[Claims] 1. A method for manufacturing a semiconductor nonvolatile memory device having a memory transistor having a charge storage layer and a selection transistor for selecting the memory transistor, wherein a semiconductor substrate is formed in a memory transistor formation region and a selection transistor formation region. Forming a gate insulating film in an upper layer of a channel forming region formed in the memory transistor; forming a charge storage layer in an upper layer of the gate insulating film in the memory transistor forming region and the select transistor forming region; Forming a control gate above the charge storage layer in the formation region and the selection transistor formation region; forming a mask layer covering at least the memory transistor formation region; and using the mask layer as a mask to form the selection transistor. Forming area A step of the gate insulating film thicker, the in the selection transistor formation region and the memory transistor forming region, a manufacturing method of a semiconductor nonvolatile memory device having a step of forming the source and drain regions. 2. The method according to claim 1, wherein the step of increasing the thickness of the gate insulating film in the select transistor formation region is a step of performing a thermal oxidation process using the mask layer as a mask. 3. The step of forming the mask layer is a step of forming a portion of a control gate of the select transistor on a side of the memory transistor forming region and covering the whole of the memory transistor forming region. Item 1
The manufacturing method of the semiconductor nonvolatile memory device described in the above. 4. The method according to claim 1, wherein the step of forming the mask layer is a step of forming the same pattern as a layer serving as a mask for forming the source / drain regions. Method. 5. The step of forming the charge storage layer is a step of forming a floating gate by using a conductive material. After the step of forming the charge storage layer and before the step of forming the control gate, 2. The method according to claim 1, further comprising a step of forming an intermediate insulating film. 6. The method according to claim 1, wherein the step of forming the charge storage layer is a step of forming an insulating film having a charge trap level. 7. The method for manufacturing a nonvolatile semiconductor memory device according to claim 6, wherein said step of forming said insulating film is a step of forming a laminated insulating film comprising a silicon nitride layer and a silicon oxide layer. 8. The method according to claim 6, wherein the step of forming the insulating film is a step of forming an insulating film made of a silicon nitride layer.