JPH1139256A - Communication control apparatus, communication control method, and storage medium storing computer-readable program - Google Patents

Abstract

(57) [Problem] To provide a data receiving side in which a clock for reliably storing a data signal is automatically generated and a large amount of data signal is received and processed in a short time. SOLUTION: A latch circuit 18 detects a change in an arbitrary data signal of a printer parallel port 16 and generates a clock signal, and a FIFO is generated based on the generated clock signal.
The memory 19 stores the coded data signal received via the printer parallel port 16, and a receivable state signal indicating whether or not there is a predetermined free area from the FIFO memory 19 is output from the state signal line of the printer parallel port 16. The present invention is characterized in that a configuration for outputting to a data signal line is provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication control device and a communication control method for mutually performing data communication processing via a predetermined communication medium, and a storage medium storing a computer-readable program.

[0002]

2. Description of the Related Art Conventionally, when data transfer processing is performed between various data processing devices via a general-purpose parallel port, a control signal nStrobe and a state signal Busy are used.
It is common to perform handshake using According to this method, every time one byte of data is transferred, the state signal Busy is confirmed to be in the “L” state, the data is output, and after the control signal nStrobe outputs the “L” state, the control signal "H" level must be output to nStrobe.

[0003] In a general personal computer, this handshake cannot be performed by hardware, so that it is performed by software, and high-speed data transfer cannot be performed.

[0004] In order to solve this problem, there is a method of performing high-speed data transfer by performing a handshake by hardware, such as ECP mode transfer specified in the IEEE standard "IEEE Std 1284-1994".

[0005]

However, a general personal computer does not always have this hardware, so that there is a problem that the number of computers that can be connected is limited.

Further, as shown in Japanese Utility Model Application No. 4-34147 (computer printer port and laser engine interface conversion device), one bit of 8-bit data is used as a clock bit, and There is a method that enables high-speed transfer by omitting the handshake for each byte.

However, in this method, since one bit is used as a clock bit, only seven bits can be transmitted in one transfer.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to store a data signal from a parallel data signal of a predetermined number of bits which is encoded and transferred. By sequentially storing the data signals while generating the clock of
A data signal capable of receiving a large amount of data in a short time and accurately through the entire data bit width of a general-purpose parallel port can be encoded. On the data receiving side, a clock that reliably stores the data signal is automatically generated. It is another object of the present invention to provide a communication control device and a communication control method capable of receiving and processing a large amount of data signals in a short time, and a storage medium storing a computer-readable program.

[0009]

According to a first aspect of the present invention, there is provided a parallel port having a plurality of data signal lines, at least one control signal line, and at least one state signal line; Clock generation means for detecting a change in a data signal to generate a clock signal; storage means for storing an encoded data signal received via the parallel port by the clock signal generated by the clock generation means; Means for outputting a receivable state signal indicating whether or not there is a predetermined free area to a state signal line or a data signal line of the parallel port.

A second invention according to the present invention has a decoding means for decoding the data signal stored in the storage means.

According to a third aspect of the present invention, there is provided a parallel port having a plurality of data signal lines, at least one control signal line, and at least one state signal line, and an output to be transferred to the outside via the parallel port. Encoding means for analyzing the code of the data so as to perform encoding so that the codes arranged side by side are at least one bit different from each other to generate data, and a receivable state signal output from an external device connected to the parallel port Communication means for outputting the data encoded by the encoding means to the data signal line of the parallel port when indicates that data of a predetermined size can be received.

According to a fourth aspect of the present invention, the encoding means inserts a code that does not represent data when the codes arranged next to each other are the same.

In a fifth aspect according to the present invention, the encoding means encodes a code representing a smaller length when the codes arranged side by side are the same.

In a sixth aspect according to the present invention, the encoding means encodes another code having the same meaning when the codes arranged next to each other are the same.

According to a seventh aspect of the present invention, a code for output data to be transferred to the outside via a parallel port having a plurality of data signal lines, at least one control signal line, and at least one state signal line is analyzed. An encoding step of encoding data so that the codes arranged side by side differ by at least one bit to generate data; and a receivable state signal output from an external device connected to the parallel port has a predetermined size. And a communication step of outputting the data encoded in the encoding step to a data signal line of the parallel port when it indicates that the data can be received.

An eighth invention according to the present invention analyzes the sign of output data to be transferred to the outside via a parallel port having a plurality of data signal lines, at least one control signal line, and at least one state signal line. An encoding step of encoding data so that the codes arranged side by side differ by at least one bit to generate data; and a receivable state signal output from an external device connected to the parallel port has a predetermined size. And a communication step of outputting the data encoded in the encoding step to a data signal line of the parallel port when the data can be received. Is stored in.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION

[First Embodiment] FIG. 1 is a block diagram illustrating the configuration of a communication control apparatus according to a first embodiment of the present invention.

In FIG. 1, reference numeral 1 denotes a host computer, which includes a CPU 2, a memory 3, a hard disk 4, a floppy drive 5, and a host parallel port 6, and is connected to the printer 7 via the host parallel port 6.

Reference numeral 2 denotes a CPU which executes various control programs and application programs stored in the memory 3. Reference numeral 3 denotes a memory, which stores a program read from the hard disk 4 or the floppy drive 5 and data required by the program.

Reference numeral 4 denotes a hard disk, which stores programs such as an operating system 10, an application program (application) 11, a printer driver program 12, an encoding program 13, and a communication program 14, which will be described later with reference to FIG.

Reference numeral 5 denotes a floppy drive, on which a floppy disk such as an installation disk 8 can be mounted, and which reads a program stored in the mounted floppy disk. Reference numeral 6 denotes a host parallel port that can send data and control signals to the printer 7 and receive status signals from the printer 7. Reference numeral 7 denotes a printer which receives data and control signals from the host parallel port 6, performs printing, and sends various statuses of the engine unit to the host parallel port 6 as status signals.

An installation disk 8 stores a printer driver program 12, an encoding program 13, a communication program 14, and an installation program shown in FIG.

In a normal installation operation, when an operator sets the installation disk 8 in the floppy drive 5 (or a CD-ROM drive not shown) and starts an installation program (including a setup program), the installation program is replaced with a printer driver program. 12, the encoding program 13, and the communication program 14 are read from the installation disk 8 and written into a predetermined area of the hard disk 4.

The installation program uses a function provided by the operating system 10 to set the printer driver program 12 so that the application program 11 can use the printer driver program 12.

FIG. 2 is a block diagram showing the configuration of a printing system to which the communication control device according to the present invention can be applied.

In FIG. 1, reference numeral 10 denotes an operating system (OS) which manages hardware resources such as a CPU 2, a memory 3, a hard disk 4, a floppy drive 5, a host parallel port 6, an application program 11, and a printer driver program 12. ,
The software such as the encoding program 13 and the communication program 14 is managed.

Reference numeral 11 denotes an application program which creates print data in accordance with an operator's instruction and issues a print command to the printer driver program 12 via the operating system 10. A printer driver program 12 creates bitmap data for the printer 7 to perform printing based on a print command issued from the application program 11.

Reference numeral 13 denotes an encoding program, which generates encoded data from the bitmap data created by the printer driver program 12 such that identical data bytes do not continue. Reference numeral 14 denotes a communication program which issues a print command to the printer 7 and outputs encoded data generated by the encoding program 13 to the printer 7.

Reference numeral 6 denotes a host parallel port, which is an IEEE parallel port.
8-bit data signals Data1 to Dat specified by the E standard "IEEE Std 1284-1994"
a8, a 4-bit control signal nSt for controlling the printer 7
probe, nAutoFd, nSelectIn, nI
nit, a 5-bit status signal n indicating the status of the printer 7
Ack, Busy, PError, Select, nF
By default, the printer parallel port 16 is connected. Reference numeral 16 denotes a printer parallel port, which is connected to the host parallel port 6 by the above-described signal.

Reference numeral 17 denotes a control circuit, for example, one chip C
A PU is used to control the printer parallel port 16 and transmit an engine command and receive an engine status with the printer engine 22 using a serial signal.

A latch circuit 18 generates a clock from a data signal and latches the data when receiving the code string data output from the communication program 14. A first-in first-out memory (FIFO memory) 19 stores data latched by the latch circuit 18 and decodes the stored data in a first-in first-out order in a decoding circuit 20.
Output to

The FIFO memory 19 has a free space of 8
A signal FULL indicating whether it is equal to or larger than KB is output to the printer parallel port 16. The decoding circuit 20
The code string data stored in the O memory 19 is decoded and output to the shift register 21.

When the shift register 21 receives the BD signal for notifying the start of the main scanning from the printer engine 22, the shift register 21 converts the parallel data output from the decoding circuit 20 into serial data, and outputs the serial data to the printer engine 22.

The printer engine 22 is a laser beam printer engine. The printer engine 22 receives an engine command and transmits an engine status using a serial signal with the control circuit 17, and receives a PRINT command from the control circuit 17 so that one page is output. When the sheet reaches a predetermined position, a BD signal notifying the start of main scanning is output to the shift register 21 and printing is performed according to the serial data output from the shift register 21.

The data transfer operation during the printing process will be described below.

When the operator operates the application program 11 on the host computer 1 side to generate print data and gives a print instruction, a print command is passed from the application program 11 to the printer driver program 12 via the operating system 10. It is.
The printer driver program 12 creates bitmap data based on a print command issued from the application program 11.

The encoding program 13 executes the printer driver program 1 based on an encoding procedure described later.
2 generates encoded data such that the same data byte is not consecutive from the bitmap data created by the second unit.

The communication program 14 first transmits a command “0x01” for instructing the start of printing via the host parallel port 6. The control circuit 17 receives this via the printer parallel port 16. Command “0x01” that the received command instructs to start printing
If so, the control circuit 17 transmits a PRINT command to the printer engine 22. Printer engine 22
Starts printing upon receiving the PRINT command.

Then, the communication program 14 transmits the encoded data generated by the encoding program 13 via the host parallel port 6 based on a communication procedure described later. The latch circuit 18 receives the data via the printer parallel port 16, detects a change in data by a circuit described later, latches the data with a clock generated, and stores the data in the FIFO memory 19.

The decoding circuit 20 decodes the encoded data stored in the FIFO memory 19 and outputs the decoded data to the shift register 21 based on a decoding procedure described later. The shift register 21 has a counter for counting the length of the main scanning. Each time the start of the main scanning is notified by the BD signal output from the printer engine 22, a predetermined value is set in the counter, and then the counter is set to "0". During this period, the parallel data output from the decoding circuit 20 at a predetermined timing is converted into serial data, which is output to the printer engine 22 and decrements the counter. When the paper reaches a predetermined position, the printer engine 22 outputs a BD signal each time main scanning starts, thereby notifying that data output is necessary, and based on the serial data output by the shift register 21. Perform printing.

Next, referring to the table shown in FIG.
The code generated by the encoding program 13 shown in FIG. Note that the code used in the present embodiment is a type of run-length code.

FIG. 3 shows the encoding program 1 shown in FIG.
FIG. 3 is a diagram illustrating an example of an encoding table generated by No. 3;

As shown in FIG. 3, when the command code C is from "0" to "0x7F", it is a raw data command, and specifies that raw data having a length determined by the command code C follows. I do.

When the command code C is “0” or “1”, the length of the raw data ranges from “1”, “2” to “0x”.
"C" up to "7F". For example, codes “0” and “0x44” are 1-byte data “0x44”.
To express. Further, reference numerals “2”, “0x55”, “0x
66 ”is 2-byte data“ 0x55 ”,“ 0x66 ”
To express.

When the command code C is "0x80", it is a "NOP" command and represents empty data. When the command code C is from “0x81” to “0xFF”, it is a run command, and the following 1-byte data is the length of the run determined by the command code C,
In other words, it is specified to have the number of times to be repeated.

As for the length of the run, when the command code C is "0x
81 ”or“ 0x82 ”, 2,“ 0x83 ”
To (0xFF) is (C-0x80).

For example, the codes "0x82", "0x55"
Represents 2-byte data "0x55" and "0x55". The codes “0x83” and “0x66” are 3-byte data “0x66”, “0x66”, “0x66”
To express.

Hereinafter, a characteristic configuration of the present embodiment will be described with reference to FIG.

A communication control device configured as described above, comprising: a parallel port (printer parallel port 16) having a plurality of data signal lines, at least one control signal line, and at least one status signal line; Clock generation means (latch circuit 1) for detecting a change in an arbitrary data signal of a port and generating a clock signal
8) and storage means (FIFO memory 1) for storing the encoded data signal received via the parallel port by the clock signal generated by the clock generation means.
9) and a receivable state signal output means for outputting a receivable state signal indicating whether or not a predetermined free area is present in the storage means to a state signal line or a data signal line of the parallel port. Output to the printer parallel port 16), a transfer clock can be automatically generated from the parallel data received via the general-purpose parallel port, and the transfer bit width is reduced by allocating clock bits in advance as in the related art. Thus, desired output data can be transferred at high speed by using all transferable bits to the maximum.

Further, since there is provided a decoding means (decoding circuit 20) for decoding the coded data signal stored in the storage means, intended output data can be received at high speed with a small storage capacity from the coded and received data. Can be processed.

Furthermore, a parallel port (host parallel port 6) having a plurality of data signal lines, at least one control signal line, and at least one status signal line
And a code for generating data by analyzing the code of output data to be transferred to the outside (the printer 7 in the present embodiment) via the parallel port and performing encoding so that the adjacent codes are different by at least one bit. The encoding means (encoding program 13) and the reception enable signal output from the external device connected to the parallel port indicate that the data of a predetermined size can be received. Communication means (communication program 14) for outputting data encoded by the conversion means to the data signal line of the parallel port, so that the data signal can be stored at the transfer destination from the data signals continuously transferred. Can be encoded as data that can be reliably generated.

Next, the encoding procedure of the encoding program 13 shown in FIG. 2 will be described in detail with reference to the program list shown in FIG.

FIG. 4 shows the encoding program 1 shown in FIG.
FIG. 4 is a diagram for explaining the details of the encoding procedure of No. 3; for example, a program is configured by a function described in C language.

In the figure, line 1 defines a function name, an argument, and a return value type. The function name of this function is encode
e, receives from the caller the start address src of the bitmap data, the start address dst of the buffer for storing the encoded data, and the number of bytes size of the bitmap data, encodes the bitmap data, and stores the encoded data in the buffer. Store and return the number of stored bytes as the return value.

During the encoding process, the start address sr
c, the start address dst, and the number of bytes size are updated to indicate the start address of the unprocessed bitmap data, the start address of the unprocessed buffer, and the number of bytes of the unprocessed bitmap data, respectively.

Lines 3 to 5 are temporary variables dstop, c
md and len are defined. dstop is a function enco
The start address dst of the buffer that stores the encoded data when de is called is stored. The cmd stores the command of the code being processed. len stores the length of the raw data being processed or the length of the run.

When the function encode is called, line 3
Stores the value of the start address dst of the buffer in dststop, and stores 1 byte 0 in the buffer pointed to by dst in row 6.
x80, that is, the NOP command is stored, and dst is advanced by one. Next, until the number of bytes size of the unprocessed bitmap data becomes 0, “whi” in rows 7 to 56
Repeat the le loop.

In the while loop from row 7 to row 56, it is first determined in row 8 whether the number of bytes size of unprocessed bitmap data is greater than one. If it is greater than 1, the process proceeds to row 9 to determine whether * src, ie, the first byte of unprocessed bitmap data, and * (src + 1), ie, the next byte, are the same. If they are the same, it is a case of encoding to a run command, so by repeating the for loop from row 10 to row 12 until the maximum run length 127 or the number of bytes of unprocessed bitmap data reaches size Find the length of the run.

In the for loop, when * src and * (src + len) are not equal in row 11, the same data is no longer continuous, so the for loop ends. At the end of the for loop, len stores the length of the run.

Next, at line 13, it is determined whether or not the length len of the run is greater than 2. If greater than 2, row 14
To store the run command in cmd.

Next, in line 15, the command cmd and the run data * src are compared, and if they are the same, the same data will be continuous. To avoid this, the run length len is set to 1 Reduce and command cmd accordingly
To reset. Next, in line 16, the run length len is 2
Determine if it is greater. If greater than 2, row 1
7 and * (dst-1), that is, if the command cmd is the same as the data last stored in the buffer, the same data will be continuous. 1x0x80
That is, the NOP command is stored and the dst is advanced by one. Next, in line 18, the command c is stored in the buffer pointed to by dst.
md is stored and dst is advanced by one. Next, in line 19, the run data * src is stored in the buffer pointed to by dst, and the dst is advanced by one.

Next, in row 20, the run length len is added to the start address src of the unprocessed bitmap data, and the run length len is subtracted from the number of bytes size of the unprocessed bitmap data. Next, in the row 20
The statement returns to line 7 which is the head of the while loop.

In row 13 or row 16, the run length le
If n is 2, proceed to line 24 and enter the command cmd
0x81, that is, the first command indicating that the run length is 2. Next, in line 25, if the run data * src is the same as the command cmd, the same data will be continuous. To avoid this, the command cmd contains 0x82, ie, the run length is 2
Is stored.

Next, in line 26, if * (dst-1), that is, the last data stored in the buffer and the command cmd are the same, the same data will be continuous, so that it is avoided. To the buffer pointed to by dst
Byte 0x80, that is, the NOP command is stored and d
Advance st by one. Next, in line 27, the command cmd is stored in the buffer pointed to by dst, and the dst is advanced by one.

Next, in line 28, the run data * src is stored in the buffer pointed to by dst, and the dst is advanced by one. Next, in line 29, the run length 2 is added to the head address src of the unprocessed bitmap data, and the run length 2 is subtracted from the number of bytes size of the unprocessed bitmap data.
Next, the continuation statement in line 30 returns to line 7 which is the head of the while loop.

In line 9, if * src, ie, the first byte of the unprocessed bitmap data, and * (src + 1), ie, the next byte, are not the same, it is a case to encode a row command. The length of raw data is determined by repeating the for loop from line 32 to line 35. In the for loop, at line 33,
If the length len of the raw data reaches one less than the maximum value 127 of the run length or one less than the number of bytes size of the unprocessed bitmap data, it is the last byte of the raw data. In this case, 1 is added to the length len of the raw data without performing comparison, and the for loop ends.

In line 34, * (src + len)
If * and (* src + len + 1) are equal, it means that adjacent data is the same, and the for loop ends. At the end of the for loop, len stores the length of raw data.

Next, in line 36, the length len of the raw data
Is greater than one. If it is greater than 1,
Proceeding to line 37, the raw data command is stored in cmd.
Next, at line 38, the command cmd is compared with the first byte * src of the raw data, and if the two are the same, the same data will be continuous. Is reduced by 1 and the command c
Reset md.

Next, at line 39, it is determined whether or not the length len of the raw data is greater than one. If it is greater than 1, the process proceeds to line 40, and if * (dst-1), that is, the last data stored in the buffer and the command cmd are the same, the same data will be continuous. 1x 0x80 in the buffer pointed to by dst to avoid
That is, the NOP command is stored and dst is advanced by one.

Next, in the line 41, the command cmd is stored in the buffer pointed to by dst, and the dst is advanced by one. Next, in line 42, the number of bytes of unprocessed bitmap data si
The length len of the raw data is subtracted from ze.

Next, in the while loop of the row 43, the raw data indicated by the raw data length len is transferred from the head address src of the unprocessed bitmap data to the head address dst of the unprocessed buffer. , The start address sr of the unprocessed bitmap data
c and the start address dst of the unprocessed buffer are advanced by the number of transferred bytes. Next, the row 44
Returning to line 7 which is the head of the while loop from the “nu” statement.

When the size size of the unprocessed bitmap data in row 8 is 1, or when row 36 or row 3
In step 9, if the length len of the raw data is 1, the process proceeds to line 49, and the command cmd stores 0, that is, the first command indicating that the length of the raw data is 1. Next, in line 50, if the first byte * src of the raw data is the same as the command cmd, the same data will be continuous.
1 indicating that the length of the raw data is 1.
To store the command. Next, at line 51, * (dst-
1) That is, if the command cmd is the same as the data last stored in the buffer, the same data will be continuous. To avoid this, 1-byte 0x80, that is, a NOP command is stored in the buffer pointed to by dst. Store and advance dst by one. Next, at line 52, dst
Cmd is stored in the buffer pointed to by
Go forward.

Next, in line 53, the run data * src is stored in the buffer pointed to by dst, and src and dst are set to 1
Go forward. Next, in line 54, the raw data length 1 is subtracted from the number of bytes size of the unprocessed bitmap data. Next, the process returns to line 7 which is the head of the while loop.

When the processing of all data is completed and the number of bytes of unprocessed bitmap data becomes 0,
The while loop from line 7 to line 55 ends, and line 5
At dst, ds from the end address of the buffer
ttop, that is, the number of bytes stored in the buffer is obtained by subtracting the head address of the buffer, and the function is terminated using the number as the return value.

Hereinafter, the characteristic configuration of the present embodiment will be further described with reference to FIG.

A storage medium storing a communication control method or a computer readable program configured as described above, comprising a plurality of data signal lines, at least one control signal line, and at least one state signal line. An encoding step of analyzing the code of output data to be transferred to the outside via the host parallel port 6 and encoding the encoded data so that the aligned codes are different from each other by at least one bit (rows 1 to 4 in FIG. 4) 57) and when the receivable state signal output from the external device connected to the host parallel port 6 indicates that data of a predetermined size can be received, Communication step of outputting the data encoded in the conversion step to the data signal line of the host parallel port 6 (communication processing (Step (not shown) according to RAM 14), a transfer clock can be automatically generated from parallel data received via a general-purpose parallel port, and a clock bit is allocated in advance and a transfer bit width is not reduced as in the related art. Thus, desired output data can be transferred to an external device at a high speed by making full use of all transferable bits.

Next, a data communication processing procedure between the host computer 1 and the printer 7 shown in FIG. 2 will be described with reference to FIG.

FIG. 5 is a timing chart for explaining data communication processing between the host computer 1 and the printer 7 shown in FIG.

In the figure, when the communication program 14 receives, from the encoding program 13, a code string encoded so that adjacent data bytes do not become the same, it indicates to the host parallel port 6 the start of transmission of the code string. After outputting the command “0x00”, “L” is output to the control signal nStrobe.

The printer parallel port 16 outputs a control signal n
The falling edge of the probe is detected, and the data output from the host computer 1 is received.

If the received data is a command “0x00” indicating the start of transmission of a code string,
If the IFO memory 19 has a free space of 8 KB or more, which is the maximum value of the transfer block size, the Busy is kept at "L".
"H" is output to the state signal Busy within microseconds.

The communication program 14 controls the control signal nStro
After outputting "L" to be, wait for 1 microsecond or more, and read the status signal Busy. If the status signal Busy is "H", it is the maximum value of the transfer block size in the FIFO memory 19. Since there is no space of 8 KB or more, wait until the status signal Busy becomes "L".

When the status signal Busy is "H", the communication program 14 can return the control signal nStrobe to "H" to cancel the transmission of the code string. Before the communication program 14 returns the control signal nStrobe to “H”, the printer parallel port 16 sets the status signal Busy to “L” when an empty space of 8 KB or more, which is the maximum value of the transfer block size, is created in the FIFO memory 19. Is output.

When the communication program 14 detects that the status signal Busy is "L", it sequentially transmits code string data at intervals of 1 microsecond or more within a range not exceeding the maximum transfer block size of 8 KB. I do. At this time, since only the data signal is changed without changing the control signal, data can be transmitted at a very high speed.

The data of the code string is supplied to the latch circuit 18 via the printer parallel port 16. When detecting any change in the 8-bit data signal, the latch circuit 18 generates a clock and latches the data.

Since the rise time and the fall time of a data signal usually differ from each other, erroneous data may be latched if data is latched immediately upon detection of a change in the data signal. To avoid this, the data latch is set to 0.
Perform after 5 microseconds.

The data latched by the latch circuit 18 is FI
The data is written to the FO memory 19. When the communication program 14 finishes transferring one block of data, the control signal nSt
The probe is returned to “H”. Printer parallel port 16
Responds to this by changing nAck to “L” and “H”, and outputs “L” if the status signal Busy is “H”.

Next, the configuration and operation of the latch circuit 18 shown in FIG. 2 will be described in detail with reference to FIG.

FIG. 6 is a circuit diagram showing details of latch circuit 18 shown in FIG.

In the figure, reference numeral 30 denotes an 8-bit D flip-flop, which is a data signal Da from the printer parallel port 16 added to the input D11 to the input D18.
From ta1, the data signal Data8 is sampled and latched at the rising edge of the system clock SCLK having a period of, for example, 0.1 microsecond, and output Q11 to output Q1
8 is output.

Reference numeral 31 denotes an 8-bit D flip-flop, which outputs an output Q1 applied from an input D21 to an input D28.
The signals from 1 to Q18 are sampled and latched at the rising edge of the system clock SCLK having a period of, for example, 0.1 microsecond, and output from the outputs Q21 to Q28.

Reference numerals 32 to 39 denote exclusive OR circuits (EXOR circuits), which are the signals of the output Q11 to the output Q18 of the 8-bit D flip-flop 30 and the output Q21 to the output Q28 of the 8-bit D flip-flop 31.
Perform an exclusive OR operation (EXOR operation) with the signal of
The calculation result is output from the output X1 to the output X8.

Reference numeral 40 denotes an 8-input OR circuit.
The logical sum of the output X1 to the output X8, which is the output of the circuit 39, is performed, and the result is output to the output Y. Reference numeral 41 denotes an AND circuit which outputs a signal BLK indicating that a code string supplied from the printer parallel port 16 is being received, and the output Y
And an output Q which is the output of the SR flip-flop 43, and outputs the operation result to the output Z.

Reference numeral 42 denotes a shift register which delays the signal of the output Z by, for example, 0.5 microsecond, and outputs a clock CLK.
Output to The clock CLK is supplied to the FIFO memory 19 as a write signal WR.

An SR flip-flop 43 samples the output Z and the clock CLK at the rising edge of ZCLK. If the sampled Z signal is "H", the output Q is set to L, and the sampled CLK signal is set to "H". Then, the output Q is set to “H”.

The SR flip-flop 43 is set to "H" in the initial state. Reference numeral 44 denotes an 8-bit D flip-flop, which samples the signals from the output Q11 to the output Q18 applied to the input D31 to the input D38 at the rising edge of the system clock SCLK, latches them, and outputs the signals from the output Q31 to the output Q38. , FIFO memory 19.

Next, an operation example of the latch circuit 18 shown in FIG. 6 will be described with reference to FIG.

FIG. 7 is a timing chart showing the operation of latch circuit 18 shown in FIG.

In the figure, when the data signal Data1 changes from “H” to “L”, the output Q11 changes from “H” to “L” in synchronization with the next rising edge of the system clock SCLK, and the output of the next system clock SCLK changes. SCL
The output Q21 changes from “H” to “L” in synchronization with the rising edge of K. While the output Q11 changes to “L” after the output Q21 changes to “L”, the output X1 becomes H. Similarly, when the data signal Data2 changes from "L" to "H" after the change of the data signal Data1 due to the difference between the rise time and the fall time, the data signal Data2 is synchronized with the next rising edge of the system clock SCLK. The output Q12 changes from "L" to "H", and the output Q2 is synchronized with the next rising edge of the system clock SCLK.
2 changes from “L” to “H”. Output Q12 is "H"
, The output X2 becomes “H” while the output Q22 changes to “H”. Accordingly, the output Y becomes “H” while either the output X1 or the output X2 is “H”.

If the signal BLK indicating that the code string is being received is "H", the output Q of the SR flip-flop 43 is initially "H", and the outputs X1 and Y change to "H". Accordingly, the output Z of the AND circuit 41 changes to “H”. When the output Z changes to H, the output Q of the SR flip-flop 43 changes to "L" in synchronization with the next rising edge of the system clock SCLK.

When the output Q of the SR flip-flop 43 is at "L", the output Z of the AND circuit 41 is at "L" regardless of the state of the output Y of the OR circuit 40. Even if Y changes to "H",
The state of "L" is maintained. When the clock CLK changes from “L” to “H” with a delay of 0.5 microsecond from the output Z by the shift register 42, the D flip-flop 4
4 latches the signal of output Q11 to output Q18 to
While being supplied to the FO memory 19, the output Q of the SR flip-flop 43 changes to “H” in synchronization with the next rising edge of the system clock SCLK. Since the clock CLK changes from "H" to "L" with a delay of 0.5 microsecond from the output Z, the clock CLK returns to the original state and is ready for the detection of the next data signal change.

In the above description, first, the data signal Dat
a1 changes from “H” to “L”,
Change from "L" to "H" or data signal Dat
The same operation is performed even when a data signal other than a1 changes. Therefore, if any data signal changes, it can be detected and the clock CLK can be generated.

Next, details of the decoding procedure of the decoding circuit 20 shown in FIG. 2 will be described.

When data is requested from the shift register 21, the decoding circuit 20 reads a 1-byte command from the FIFO memory 19. If the read command is a NOP command “0x80”, it is empty data and is ignored.

On the other hand, if the read command is a run command, the run length is calculated from the command code and set in the counter, and the next one byte of data is read from the FIFO memory 19 and stored in the data register. Thereafter, while the counter is greater than "0", the data stored in the data register is output every time data is requested from the shift register 21, and "1" is subtracted from the counter.

On the other hand, if the read command is a raw data command, the raw data length is calculated from the command code and set in the counter. Thereafter, while the counter is greater than "0", every time data is requested from the shift register 21, one byte of data is read from the FIFO memory 19 and the data is output.
Is subtracted.

[Second Embodiment] In the first embodiment, a plurality of command codes are assigned only to the raw data command having the length "1" and the run command having the length "2". Therefore, there is a problem that the size of the encoded data rarely greatly exceeds the original data size depending on the data.

Therefore, in order to reduce the above problem, the number of commands to which a plurality of command codes are assigned may be increased. For example, three types of raw data commands of length "1"
By assigning three types of raw data commands of length "2", three types of raw data commands of length "3", and three types of run commands of length "2", this problem can be greatly reduced. it can.

In the first embodiment described above, the commands expressing data are limited to raw data commands and run commands indicating repetition of arbitrary data. However, some of these commands are replaced with other commands, For example, data 0
May be assigned to a run command indicating repetition of the above or a command referring to data of the immediately preceding scan.

Further, in the above-described first embodiment, the transmission of the code string is started by outputting the command 0x00 and then nStr.
The notification is made by outputting L to be, but instead of this, an arbitrary method, for example, the IEEE standard “IEEE S
The notification may be made by entering an extended link mode defined in “td 1284-1994”.

Further, in the above-described embodiment, whether or not there is a free space of 8 KB or more, which is the maximum value of the transfer block size, is notified to the host computer by using the Busy signal. For example, the notification may be made by transferring data from the printer to the host computer by nibble mode transfer or ECP mode transfer specified in the IEEE standard "IEEE Std 1284-1994".

Hereinafter, the configuration of a data processing program that can be read by a printing system to which the communication control device according to the present invention can be applied will be described with reference to a memory map shown in FIG.

FIG. 8 is a diagram for explaining a memory map of a storage medium for storing various data processing programs that can be read by a printing system to which the communication control device according to the present invention can be applied.

Although not shown, information for managing a group of programs stored in the storage medium, for example, version information, a creator and the like are also stored, and information dependent on the OS or the like on the program reading side, for example, a program is stored. An icon or the like for identification display may also be stored.

Further, data dependent on various programs is also managed in the directory. In addition, a program for installing various programs on a computer or a program for decompressing a program to be installed when the program to be installed is compressed may be stored.

The functions shown in FIG. 4 in this embodiment may be executed by a host computer by a program installed from the outside. In this case, the present invention is applied even when a group of information including a program is supplied to the output device from a storage medium such as a CD-ROM, a flash memory, or an FD, or from an external storage medium via a network. Things.

As described above, the storage medium storing the program codes of the software for realizing the functions of the above-described embodiments is supplied to the system or the apparatus, and the computer (or CPU or MP) of the system or the apparatus is supplied.
It goes without saying that the object of the present invention is also achieved when U) reads and executes the program code stored in the storage medium.

In this case, the program code itself read from the storage medium realizes a novel function of the present invention, and the storage medium storing the program code constitutes the present invention.

Examples of the storage medium for supplying the program code include a floppy disk, hard disk, optical disk, magneto-optical disk, CD-ROM,
DR, magnetic tape, nonvolatile memory card, RO
M, EEPROM and the like can be used.

When the computer executes the readout program code, not only the functions of the above-described embodiment are realized, but also the OS (Operating System) running on the computer based on the instruction of the program code. ) And the like perform part or all of the actual processing, and the processing realizes the functions of the above-described embodiments.

Further, after the program code read from the storage medium is written into a memory provided in a function expansion board inserted into the computer or a function expansion unit connected to the computer, based on the instruction of the program code, The CPU provided in the function expansion board or function expansion unit performs part or all of the actual processing,
It goes without saying that a case where the function of the above-described embodiment is realized by the processing is also included.

[0122]

As described above, the first embodiment according to the present invention is described.
According to the invention, a parallel port having a plurality of data signal lines, at least one control signal line, and at least one state signal line, and detecting a change in an arbitrary data signal of the parallel port to generate a clock signal A clock generation unit, a storage unit for storing an encoded data signal received via the parallel port by a clock signal generated by the clock generation unit, and indicating whether or not a predetermined free area exists in the storage unit. Since there is provided a receivable state signal output means for outputting a receivable state signal to a state signal line or a data signal line of the parallel port, a transfer clock can be automatically generated from parallel data received via a general-purpose parallel port. The clock bits are allocated in advance as in All bits possible to maximize the available transfer the desired output data at high speed.

Since the second invention has decoding means for decoding the coded data signal stored in the storage means, the desired output data can be processed at a high speed with a small storage capacity from the coded and received data. can do.

The third to sixth inventions are directed to a parallel port having a plurality of data signal lines, at least one control signal line, and at least one state signal line, and output data to be transferred to the outside via the parallel port. An encoding means for analyzing the codes and encoding the data so that the codes arranged next to each other are different by at least one bit to generate data, and a receivable state signal output from an external device connected to the parallel port. Communication means for outputting the data encoded by the encoding means to the data signal line of the parallel port when indicating that data of a predetermined size can be received, A clock for storing a data signal at a transfer destination from a transferred data signal can be encoded as data that can be reliably generated.

The seventh and eighth inventions analyze the sign of output data to be transferred to the outside via a parallel port having a plurality of data signal lines, at least one control signal line, and at least one state signal line. An encoding step of encoding data so that the codes arranged in sequence are different by at least one bit to generate data; and a receivable state signal output from an external device connected to the parallel port having a predetermined magnitude. And a communication step of outputting the data encoded in the encoding step to the data signal line of the parallel port when it indicates that the data can be received. The transfer clock can be automatically generated from the parallel data to be transferred, and the transfer bit width can be reduced by assigning clock bits in advance as in the past. No, it transfers the desired output data at a high speed all the bits capable of transferring and maximum use.

Therefore, at the data transmission source, a data signal capable of receiving a large amount of data in a short time and accurately through the entire data bit width of the general-purpose parallel port can be encoded. It is possible to automatically generate a clock for surely storing a signal and to receive a large amount of data signal in a short time.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a communication control device according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a printing system to which a communication control device according to the present invention can be applied.

FIG. 3 is a diagram showing an example of an encoding table generated by the encoding program shown in FIG. 2;

FIG. 4 is a diagram illustrating details of an encoding procedure of the encoding program shown in FIG. 2;

FIG. 5 is a timing chart illustrating a data communication process between the host computer and the printer illustrated in FIG. 2;

FIG. 6 is a circuit diagram showing details of a latch circuit shown in FIG. 2;

FIG. 7 is a timing chart illustrating an operation of the latch circuit illustrated in FIG. 6;

FIG. 8 is a diagram illustrating a memory map of a storage medium that stores various data processing programs that can be read by a printing system to which the communication control device according to the present invention can be applied.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Host computer 2 CPU 6 Host parallel port 7 Printer 11 Application program 12 Printer driver program 13 Encoding program 14 Communication program 16 Printer parallel port 17 Control circuit 18 Latch circuit 19 FIFO memory 20 Decoding circuit 21 Cyst register 22 Printer engine

Claims (8)

[Claims] 1. A parallel port having a plurality of data signal lines, at least one control signal line, and at least one state signal line, and a clock for generating a clock signal by detecting a change in an arbitrary data signal of the parallel port. Generating means; storing means for storing an encoded data signal received via the parallel port based on the clock signal generated by the clock generating means; and receiving indicating whether or not a predetermined free area exists in the storing means. Receivable state signal output means for outputting a possible state signal to a state signal line or a data signal line of the parallel port,
A communication control device comprising: 2. The communication control device according to claim 1, further comprising decoding means for decoding the data signal stored in said storage means. 3. A parallel port having a plurality of data signal lines, at least one control signal line, and at least one state signal line, and analyzing the sign of output data to be transferred to the outside via the parallel port. Encoding means for encoding and generating data so that the arranged codes are different from each other by at least one bit; and a receivable state signal output from an external device connected to the parallel port converts data of a predetermined size. A communication control unit that outputs data encoded by the encoding unit to a data signal line of the parallel port when it indicates that reception is possible. 4. The communication control device according to claim 3, wherein the encoding unit inserts a code that does not represent data when the codes arranged side by side are the same. 5. The communication control device according to claim 3, wherein the encoding unit encodes the code having a smaller length when the codes arranged in a row are the same. 6. The communication control apparatus according to claim 3, wherein said encoding means encodes, when the codes arranged side by side are identical, another code having the same meaning. 7. The code of output data to be transferred to the outside via a parallel port having a plurality of data signal lines, at least one control signal line, and at least one status signal line is analyzed, and at least codes arranged in parallel are analyzed. An encoding step of performing encoding so as to generate data by one bit differently; and a receivable state signal output from an external device connected to the parallel port can receive data of a predetermined size. A communication step of outputting data encoded in the encoding step to a data signal line of the parallel port. 8. Analyzing the codes of output data to be transferred to the outside via a parallel port having a plurality of data signal lines, at least one control signal line, and at least one state signal line, and determining that at least two codes are aligned. An encoding step of performing encoding so as to generate data by one bit differently; and a receivable state signal output from an external device connected to the parallel port can receive data of a predetermined size. A communication step of outputting data encoded by the encoding step to a data signal line of the parallel port, wherein a computer-readable program is stored. .