JPH11354793A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a self-alignment contact to be used for an integrated circuit, by forming the channel of a power semiconductor device in a self-alignment manner while maintaining the characteristics of a CMOS circuit when manufacturing an intelligent power IC. SOLUTION: Before the gate electrode formation of the LDMOS part of an intelligent power IC, the channel of the LDMOS can be determined in a self-alignment manner using a dielectric layer, thus simultaneously forming the gate electrode of a CMOS part and the LDMOS part without changing the characteristics of the CMOS part in the intelligent power IC. Also, before the gate electrode of the LDMOS part is formed, the channel of the CMOS part is determined and then the gate electrode of the LDMOS part can be formed, thus forming a self-alignment contact at the LDMOS part easily and reducing process and costs and achieving high integration.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which a channel is formed by self-aligned diffusion.

[0002]

2. Description of the Related Art
Conventionally, when manufacturing a semiconductor device (generally called an intelligent power IC) having both a power semiconductor device and a CMOS (complementary metal oxide semiconductor),
The channel of the power semiconductor device is formed in a self-aligned manner. When a channel of a power semiconductor device is formed in a self-aligned manner by a conventional method, the power semiconductor device and
After forming the gate electrode of the CMOS circuit in the same process step (FIG. 6)
A) It is necessary to perform a high-temperature and long-time heat treatment to form a channel of the power semiconductor device. This heat process is CM
Since the concentration of the channel of the OS element changes, CMOS
This significantly changes the characteristics of the circuit (FIG. 6B). To solve it, adapt the characteristics of the CMOS circuit again or
Requires redesign of CMOS circuits. However, in order to adapt the characteristics of the CMOS circuit again, additional manufacturing process steps are required. That is, for example, when an LDMOS is used as a power semiconductor device, after the heat treatment for forming the gate electrode in the LDMOS portion and the channel in the LDMOS portion, the concentration of the channel portion in the CMOS portion is readjusted,
A gate electrode for the OS portion must be formed. That is, the gate electrodes of the LDMOS part and the CMOS part are separately
In addition, the gate electrode must be formed in the order of the gate electrode of the LDMOS part and the gate electrode of the CMOS part. This is accompanied by an increase in cycle time and an increase in manufacturing cost. Furthermore, in a situation where the degree of circuit integration is very high, as in recent years,
Redesign of CMOS circuits is almost impossible, and the desired miniaturization has not been possible with the conventional self-aligned method.

On the other hand, when a channel of a power semiconductor device is formed by a non-self-aligning method, the channel length of the power semiconductor device, the distance between the channel and the drain, and the like vary, thereby deteriorating the characteristics of the semiconductor device. For example, the withstand voltage between the drain and the source varies, and the on-resistance is deteriorated or varies. Typically, for products with a drain-source breakdown voltage of 50-60V, ± 10-15V
A degree of variation in breakdown voltage occurs. Therefore, in a product in which the drain-source withstand voltage is set low (for example, 20 V or less), a leak such as punch-through may occur, so that the withstand voltage cannot be set low.

In general, there has been a manufacturing method that utilizes a self-aligned contact when providing a contact in a method of manufacturing a power semiconductor device. The self-aligned contact can reduce the cell size of the semiconductor device and can achieve high integration. The use of a self-aligned contact in a power semiconductor device portion having a large occupation ratio of a die area is very useful for high integration, and it has been possible to reduce on-resistance. Conventionally, however, the use of self-aligned contacts in the manufacture of intelligent power ICs required a very complicated process. This is because the characteristics of the CMOS circuit cannot be maintained unless a gate electrode is individually formed for each of the power semiconductor device portion and the CMOS circuit portion.

[0005] The present invention provides a method for re-optimizing the characteristics of a CMOS circuit or CMOS when manufacturing an intelligent power IC.
It is an object of the present invention to provide a method of manufacturing a semiconductor device, in which a channel of a power semiconductor device can be formed in a self-aligned manner without the need for circuit redesign, and the cycle time is not increased and the manufacturing cost is not increased. Do one.

Further, when a self-aligned contact is used in the manufacture of an intelligent power IC, by utilizing the above-described self-aligned channel formation, the power can be controlled in the same process while maintaining the state where the characteristics of the CMOS circuit are adapted. Provided is a method of manufacturing a semiconductor circuit capable of forming a gate in a semiconductor device portion and a CMOS circuit portion. This can greatly contribute to high integration of circuits, shortening of processes, reduction of cycle time, and reduction of die cost.

Therefore, according to the present invention, when manufacturing an intelligent power IC, a channel of a power semiconductor device can be formed in a self-aligned manner while maintaining the characteristics of a CMOS circuit, and a self-aligned contact is formed in the integrated circuit. Make it available.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the preferred embodiment, an n-channel LD
MOS is used as an embodiment of the power semiconductor device.
In the present invention, the power semiconductor device is not limited to an n-channel LDMOS.

FIG. 1 schematically shows an LDMOS manufacturing method according to the present invention for each step. 1A, a dielectric layer (preferably a silicon oxide film) 120 is formed on a main surface 110 of a semiconductor substrate 100 to a predetermined thickness. Photoresist 13 on the dielectric layer 120
0 is placed and patterning is performed. Thereafter, the dielectric layer 120
Is etched (A-1, A-2 in FIG. 1), or a dielectric material is deposited on the dielectric layer 120 (A-3, A- in FIG. 1).
4) Accordingly, the dielectric portions 122 and 121 having different thicknesses from each other on the region of the substrate 100 where the patterned photoresist 130 is present and on the region of the substrate 100 where the photoresist 130 is not present. 123
Are formed respectively. In the embodiment of FIG. 1B,
The thickness of the dielectric portion 122 is
And dielectric portions 121 and 123
Are equal. Also, a dielectric portion 122 exists between the dielectric portions 121 and 123, and the dielectric portion 121
And 123 are separated from each other. Further, a source region 111 exists below the dielectric portion 121, a channel region 112 exists below the dielectric portion 122, and a drain region 113 exists below the dielectric portion 123. Further, there is a boundary 124 between the dielectric part 121 and the dielectric part 122, and a boundary 125 between the dielectric part 123 and the dielectric part 122. Later, a source diffusion layer and a channel region 11
2 and a drain diffusion layer is formed in the drain region 113.

FIG. 1C is a cross-sectional view of the LDMOS portion at the stage when the photoresist 135 is formed on the dielectric portion 123. A p-type conductive impurity (for example, boron) is implanted into the substrate in a self-aligned manner with an implant energy that does not penetrate the dielectric portion 122 and the photoresist 135 and penetrates the dielectric portion 121. Thereby, a p-type impurity is implanted only in source region 111. That is, on the boundary 124,
A p-type impurity is implanted only in the source region 111. After the photoresist 135 on the dielectric layer is removed, the p-type conductive impurities are diffused in a thermal diffusion process,
A p base diffusion layer 131 is formed.

In FIG. 1D, a p-type conductive impurity is
FIG. 14 shows a cross-sectional view of the LDMOS portion at a stage after diffusion near the surface of No. 00. Preferably, an n-type well is formed in the substrate 100 in advance. Then, the diffusion layer 131
Is formed in its n-type well and has a depth of about 1.5-2.0 microns and a concentration of about 10E17-5 x 10E17ions / cm3.

Next, n-type conductive impurities (for example, phosphorus, phosphorus, etc.) are implanted at such an implant energy that penetrates the dielectric portions 121 and 123 but does not penetrate the dielectric portion 122.
(Arsenic) is implanted into the substrate 100 in a self-aligned manner.
In this case, no photoresist is required for the LDMOS region, and the source region 111 and the drain region 113 are not required.
Then, an n-type conductive impurity is implanted. That is, the source region 111 is divided by the boundary 124 and the boundary 125.
And an n-type conductive impurity is implanted in drain region 113. Thereafter, the n-type conductive impurities are diffused in a diffusion step to form diffusion layers 141 and 143. In this embodiment, the diffusion layer 141 is a source region diffusion layer, and the diffusion layer 143 is a drain region diffusion layer. The diffusion layers 141 and 143 are typically an n + diffusion layer or n −
It is a diffusion layer. When the diffusion layers 141 and 143 are n-diffusion layers, this n-diffusion layer forms a gentle concentration gradient in the source and drain regions to reduce the concentration of the electric field in the source and drain regions during operation. Help.

2D and 2E, the diffusion layers 131, 1
Although it has been described that each of the forming steps 41 is individually diffused, after implanting a p-type conductive impurity, an n-type conductive impurity is also implanted, and p-type and n-type conductive impurities are diffused in the same diffusion step. It is also possible.

In FIG. 2E, the n-type conductive impurity is
FIG. 4 shows a cross-sectional view of an LDMOS portion at a stage after diffusion near the surface of the substrate 100. The p-type and n-type conductive impurities are
Since implanted at the boundary 124, its p
The channel is determined in the channel region 112 in a self-aligned manner due to the difference in the diffusion of the type and n-type conductive impurities. Preferably, the n-type conductive impurities are diffused to a depth of about 0.2-0.6 microns and a concentration of about 10E17.
An n-type diffusion layer 141 of 1010E18 ions / cm 3 can be formed in the diffusion layer 131. As a result, a p base portion sandwiched between the n-type well and the diffusion layer 140 is formed near the surface of the channel region 112. The p base portion near the surface of the channel region 112 becomes an LDMOS channel. It should be noted here that the LDMOS channel is determined in a self-aligned manner, so that a semiconductor device with a short channel can be accurately determined.
It can be manufactured without variation. Further, at the time of determining the channel, the gate electrode of the LDMOS is not formed. Conventionally, after the gate electrode of LDMOS was formed, thermal diffusion processing for forming the p base portion was performed.
In this case, the channel concentration and the like of the CMOS portion change, so that the channel concentration and the like must be determined again. However, according to the present embodiment, since the gate electrode is formed after the channel of the LDMOS is determined, the gate electrodes of the CMOS portion and the LDMOS portion in the intelligent power IC can be formed at the same time.

FIG. 2F shows a dielectric layer 121,
A cross-sectional view of the LDMOS portion at the stage where 122 and 123 have been removed is shown. Here, the source surface region 151 on the diffusion layer 141, the drain surface region 153 on the diffusion layer 143,
And a source surface region 151 and a drain surface region 153.
There is a channel surface region 152 on the channel and drift region between. Source surface region 151 and drain surface region 153 have substantially the same impurity concentration. The wafer surface regions 151 and 153 have a higher impurity concentration than the wafer surface region 152.

In FIG. 2G, the main surface 11 is formed such that a dielectric layer having a predetermined thickness is formed on the wafer surface region 152.
A dielectric layer is formed on 0. Preferably, the dielectric layer is a silicon thermal oxide film. Surface 110 includes a source surface region 151, a channel surface region 152, and a drain surface region 153. The source surface region 151 and the drain surface region 15 are larger than the channel surface region 152.
3 has a higher impurity concentration.
On the first and drain surface regions 153, a thermal oxide film thicker than the thermal oxide film formed on the channel surface region 152 is formed. Therefore, a step portion 160 is formed between the source surface region 151 and the drain surface region 153 and the channel surface region 152, and the step portion 160 is formed.
Serves for photo alignment for forming the gate electrode. That is, the step portion 160 allows the gate electrode to be accurately positioned at a predetermined position.

FIG. 2H is a cross-sectional view of the LDMOS portion after the gate electrode 170 is formed. Preferably,
Although polysilicon is used as the gate material, a metal material (for example, Al—Si 2, Al—Si—Cu, or silicide) may be used. Here, it should be noted that the gate electrode 170
Is formed after the p-base diffusion step. Conventionally, when the gate electrode 170 is formed before the p-base diffusion step, at the time of the p-base diffusion, impurities in the gate electrode 170 penetrate through the silicon gate oxide film and enter the p-base diffusion layer 131 to form the channel region 112. However, according to the present invention, the concentration of
When the gate electrode 170 is formed after the p-base diffusion step, such a problem does not occur during the p-base diffusion because the gate electrode 170 has not been formed yet.

FIG. 2I shows a cross-sectional view after the n + source / drain diffusion layer is formed in a self-aligned manner using the gate electrode 170. The source diffusion layer is 161 and the drain diffusion layer is 163. Here, once
After forming the low concentration diffusion layers 141 and 143, a high concentration n + source / drain diffusion layer is formed. In order to increase the junction breakdown voltage, the source / drain diffusion layers are formed in a double structure. This is for reducing the density difference. Further, in order to increase the breakdown voltage of the junction of the drain diffusion layer, the drain diffusion layer 163 may be formed so as not to overlap below the poly 170 (not shown). If a dual source / drain diffusion layer is not required, it is possible to increase the concentration of the diffusion layers 141 and 143 and use them instead as n + source / drain diffusion layers. In this case, the n + source / drain diffusion layer 161,
163 may not be formed. More specifically, as shown in FIG. 5, when the LDMOS gate electrode 470 is formed after the CMOS gate electrode 410 is formed, the CMOS gate electrode 4
The n + source / drain diffusion layers of the CMOS portion and the LDMOS portion may be formed in the same implant process step using the dielectric layer 420 on the LDMOS side and the LDMOS side (FIG. 5).
C). That is, the diffusion layers 401, 403, 405, and 407 may form a double-layer diffusion layer, or may have a single-layer structure of an n + diffusion layer.

The operation of the electric field relaxation effect will be described with reference to FIG. FIG. 3A is a cross-sectional view of the LDMOS portion after the gate electrode is formed. The component numbers in FIG. 3 correspond to the component numbers in H in FIG. In operation, typically, when a voltage is applied to the gate electrode 170 and the source region (diffusion layer 141) is grounded, the silicon oxide film between the gate electrode 170 and the diffusion layer 141 has a higher thickness than other portions. A large electric field is applied. As the thickness of the silicon oxide film between the gate electrode 170 and the diffusion layer 141 decreases, the electric field increases and the withstand voltage of the dielectric layer decreases, so that the silicon oxide film is easily broken. According to the conventional method, the thickness is almost equal to the thickness of the silicon oxide film on the channel surface region 152, so that it is easily broken. On the other hand, according to the present invention, as described above, the thickness of the silicon oxide film on the source surface region 151 is larger than the thickness of the silicon oxide film on the channel surface region 152. The electric field between the diffusion layer 141 can be reduced (electric field relaxation effect). The silicon gate oxide film manufactured according to the present invention is not easily broken. This electric field relaxation effect also exists between the gate electrode 170 and the drain region (diffusion layer 143). According to the present invention, an LDMOS having a structure as shown in FIG. 3B can also be formed. In this case, the above-described electric field relaxation effect is provided by using a field oxide film of LOCOS.

As described above, according to the present invention, a self-aligned channel forming method using the thickness of the dielectric layer is used instead of the gate electrode.
A gate electrode can be formed. Thereby,
CMOS part and LDMO in intelligent power IC
The gate electrode of the S portion can be formed at the same time.

Next, as an embodiment from the formation of a self-aligned channel to the formation of a self-aligned contact, an LDMOS portion and a C
In order to make both MOS parts easy to understand, they are schematically shown side by side. Hereinafter, in FIGS.
Although the shape of the diffusion layer is different from that of FIG. 1, it is a result of simplification of the drawing and is not different in content.

FIG. 4A shows an LDMOS portion where a self-aligned channel is formed as described above and a CMOS portion next to the LDMOS portion. After the channel of the LDMOS portion is determined by diffusion for forming the channel of the LDMOS portion, the dielectric layers on both the channels of the LDMOS portion and the CMOS portion are removed, and a thermal oxide film having a predetermined thickness is formed. Here, the channel concentration may be adjusted before removing the dielectric layer or after forming the thermal oxide film.

In FIG. 4B, after forming the thermal oxide film and adjusting the channel concentration, a gate electrode layer is deposited over the wafer. Typically, the gate electrode layer is polysilicon, and after the deposition, the polysilicon is doped with a predetermined conductivity type impurity. Thereafter, a cap dielectric layer is deposited on the polysilicon. Typically, the cap dielectric layer is PS
G.

In FIG. 4C, the cap dielectric layer is etched, and the polysilicon is etched, leaving the gate electrode 370 and the cap dielectric portion 375 so as to overlap over the gate electrode 370. According to this embodiment, the gate electrode 370 and the cap dielectric portion 3
75 is formed simultaneously on both the LDMOS portion and the CMOS portion. Thereafter, when the diffusion layers 341 and 343 in the LDMOS portion are n − diffusion layers, the gate electrode 370 is formed as described above.
The n + diffusion layer is formed in the n- diffusion layer and in the CMOS part by utilizing the source, the source of the LDMOS part and the CMOS part,
The drain layers 301, 303, 305, 307 are formed in a self-aligned manner. The portion of the n-diffusion layer of the LDMOS portion forms a gentle concentration gradient in the source and drain regions, and helps to reduce the concentration of the electric field in the source and drain regions during operation.

As shown in FIGS. 4D and 4E, an intermediate dielectric layer is deposited, and the intermediate dielectric layer is etched (typically, anisotropic or quasi-anisotropic etching by RIE).
An intermediate dielectric portion 378 is formed on a side surface of the gate electrode 370. Thereby, the dielectric cap 375 and the intermediate dielectric portion 378 allow insulation between the gate electrode 370 and the metal used for the interconnect (FIG. 4F).

Therefore, the intelligent power IC CMO
The channel of the power semiconductor device was formed in a self-aligned manner while maintaining the characteristics of the S circuit, and a self-aligned contact was made available for the intelligent power IC.

Conventionally, after forming the gate electrode in the LDMOS portion, the LDMOS
The channel of the portion must be determined, and then the channel of the CMOS portion and the gate electrode must be formed. Therefore, when a self-aligned contact is used for an intelligent power IC according to the conventional technology, it has to go through a very complicated process, and the cycle time is long and the manufacturing cost is high. According to the present invention, the channel of the LDMOS portion can be determined before the gate electrode of the LDMOS portion is formed.
The gate electrodes of both the LDMOS part and the CMOS part can be formed simultaneously. Therefore, the intelligent power IC can be formed without separately forming the gate electrodes of the LDMOS portion and the CMOS portion, thereby reducing the number of manufacturing steps, the cycle time, and the cost.
Also, self-aligned contact technology can be used for intelligent power ICs.

FIG. 5 shows an embodiment in which the gate electrode of the CMOS portion is formed first, and the gate electrode of the LDMOS portion is formed thereafter.

FIG. 5A is a cross-sectional view after the p base diffusion layer 431 in the LDMOS portion is formed in a self-aligned manner as described above.

In FIG. 5B, a gate electrode is formed in the CMOS portion. Preferably, the gate electrode layer is polysilicon, and after the deposition, the polysilicon is doped with a predetermined conductivity type impurity. Next, the polysilicon is etched to form a gate electrode 410 in a CMOS portion.

In FIG. 5C, the gate electrode 41 in the CMOS portion
The source and drain diffusion layers 401, 403, and 40 are formed by utilizing the dielectric layer 420 in the 0 and LDMOS portions as described above.
5, 407 are formed.

In FIG. 5D, after removing the dielectric layer in the LDMOS portion, a dielectric layer having a predetermined thickness is formed, on which a gate electrode 470 and a dielectric used for forming a self-aligned contact are formed. The cap 475 is formed so as to overlap with the gate electrode 470.

Referring to FIG. 5E, intermediate dielectric layers 478 and 479 are formed on the side surfaces of the gate electrode 470. Intermediate dielectric layer 478 is used to form a self-aligned contact. In this embodiment, a self-aligned contact is formed only in the LDMOS portion. However, a self-aligned contact may be formed in the CMOS portion by using a dielectric cap. As a result, LDMO accounts for a large proportion of the chip area
The size of the S portion can be effectively reduced.

In this embodiment, the CMO shown in FIG.
The source and drain diffusion layers of the S part are formed, but CMOS
A part of the intermediate dielectric layer 479 (which is not used or may not be formed in this embodiment) may be used as a spacer. Such an embodiment is illustrated in FIG.
Then, the channel length of the CMOS portion is determined by implanting a shallow conductive impurity that is not easily diffused using the gate electrode 410. Then, in FIG.
At E, the source diffusion layer and the drain diffusion layer are implanted using the spacer 479 so as to be formed at positions farther apart from each other, and at least the drain diffusion layer has a double diffusion layer structure (LDD). This has the effect of reducing the electric field associated with the drain diffusion layer.

Conventionally, the gate electrode of the LDMOS portion is formed,
After forming the channel by forming the base diffusion layer and the source and drain diffusion layers in the DMOS portion, the formation of the gate electrode and the formation of the source and drain diffusion layers in the CMOS portion had to be performed. Therefore, if an attempt is made to form a self-aligned contact in the LDMOS portion, an additional step will be added, and the process and cycle time will be prolonged. According to this embodiment, after forming the gate electrode of the CMOS portion, the source and drain diffusion layers are formed in the same process by using the gate electrode of the CMOS portion and the dielectric layer having the step of the LDMOS portion. (C in FIG. 5). Therefore, the process and the cycle time are not lengthened, the self-aligned contact can be formed in the LDMOS portion, and the readjustment of the CMOS channel is not required.

According to the present invention, when manufacturing an intelligent power IC, a channel of a power semiconductor device can be formed in a self-aligned manner while maintaining the characteristics of a CMOS circuit, and a self-aligned contact can be used for the integrated circuit. did. This reduces the number of steps in the gate electrode formation stage,
This makes it possible to reduce the number of processes in the contact formation stage and to reduce the chip size by using self-aligned contacts in the intelligent power IC. The use of self-aligned contacts for power semiconductor devices that occupy a large percentage of the chip area, thereby enabling a reduction in chip size, is particularly effective. As a result, cost reduction, improvement of characteristics (particularly, reduction of on-resistance), and stabilization of characteristics can be realized at the same time. For example, the length of one unit cell of LDMOS is usually about 12.
Although it is about 6 μm, according to the present invention, it is about 9.6 μm, which is a reduction of the chip size by 24% compared to the normal case. Also, LD
MOS on-resistance is typically about 0.35 mohm-cm ² , but can be reduced to about 0.26 mohm-cm ² by the present invention.

[Brief description of the drawings]

FIG. 1 is a process flow of a schematic cross-sectional view of an LDMOS according to the present invention.

FIG. 2 is a continuation of the process flow diagram 1 of a schematic cross-sectional view of an LDMOS according to the present invention.

FIG. 3 is a schematic cross-sectional view of an LDMOS according to the present invention.

FIG. 4 is a schematic cross-sectional process flow of an intelligent power IC according to the present invention.

FIG. 5 is a schematic cross-sectional process flow of an intelligent power IC according to the present invention.

FIG. 6: LDMOS and CMO in the same process in the prior art
4 is a process flow of a schematic cross-sectional view of an intelligent power IC when an S gate electrode is formed.

[Explanation of symbols]

Reference Signs List 100 semiconductor wafer substrate 110 main surface 111 source region 112 channel region 113 drain region 120, 121, 122, 123, 420 dielectric layer 124, 125 step 131, 431 base diffusion layer 141, 341 source diffusion layer 143, 343 drain diffusion layer 151 Source surface region 152 Channel surface region 153 Drain surface region 160 Step 161, 301, 305, 401, 405 Source diffusion layer 163, 303, 307, 403, 407 Drain diffusion layer 170, 370, 410, 470 Gate electrode 375, 475 Dielectric cap 378, 478 Intermediate dielectric part 479 Spacer

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[Procedure amendment]

[Submission date] June 15, 1998

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claim 10

[Correction method] Change

[Correction contents]

──────────────────────────────────────────────────の Continued on front page (51) Int.Cl. ⁶ Identification code FI H01L 27/092

Claims (11)

[Claims] 1. A method of manufacturing a semiconductor device, comprising: a first dielectric portion having a first thickness on a first region on a main surface of a semiconductor substrate; Forming a dielectric layer having a second dielectric portion (122) having a second thickness greater than the first thickness over an adjacent second region (112); And does not pass through the body portion (122) and does not pass through the first dielectric portion (12).
Implanting a first conductivity type impurity into the first region with an implant energy passing through 1); the first dielectric portion not passing through the second dielectric portion and not passing through the second dielectric portion; Implanting a second conductivity type impurity into the first region with the implant energy passing through (121); and diffusing the first conductivity type impurity and the second conductivity type impurity to a degree of diffusion. Forming a base diffusion layer (131) and a source or drain diffusion layer (141) according to the difference, and determining a channel in the base diffusion layer (131) in a self-aligned manner;
A method characterized by comprising: 2. A method for manufacturing a semiconductor device, comprising: a first dielectric portion having a first thickness on a first region on a main surface of a semiconductor substrate; Forming a dielectric layer having a second dielectric portion (122) having a second thickness greater than the first thickness over an adjacent second region (112); And does not pass through the body portion (122) and does not pass through the first dielectric portion (12).
Implanting a first conductivity type impurity into the first region with the implant energy passing through 1); forming a base diffusion layer by diffusing the first conductivity type impurity; Implanting a second conductivity type impurity into the first region (111) with an implant energy that does not pass through the second dielectric portion (122) and passes through the first dielectric portion (121). Forming a source or drain diffusion layer (141) by diffusing the second conductivity type impurity;
Determining a channel in the base diffusion layer (131) in a self-aligned manner. 3. A method of manufacturing an integrated circuit having a first type semiconductor device and a second type semiconductor device, the method comprising:
Forming the channel of the second type semiconductor device; self-aligning the channel of the second type semiconductor device; determining the concentration of the channel of the second type semiconductor device; forming the gate electrode of the second type semiconductor device; Forming a channel in a self-aligned manner; and forming a gate electrode of the first type semiconductor device; and adjusting the concentration of the channel of the second type semiconductor device after forming the gate electrode is not required. A method characterized by the following. 4. A method of manufacturing an integrated circuit having a first type semiconductor device and a second type semiconductor device, the method comprising:
Forming a base diffusion layer of a type semiconductor device in a self-aligned manner; determining a channel concentration of the second type semiconductor device; forming a gate electrode of the second type semiconductor device; Forming a channel of the second type semiconductor device in a self-aligned manner; and forming a gate electrode of the first type semiconductor device;
A method, which does not require adjusting the concentration of the channel of the second type semiconductor device after forming the gate electrode of the second type semiconductor device. 5. A method for manufacturing an integrated circuit having a first type semiconductor device and a second type semiconductor device, the method comprising:
Forming a channel of the type semiconductor device in a self-aligned manner; determining a channel concentration of the second type semiconductor device; and simultaneously forming both gate electrodes of the first and second type semiconductor devices; Forming a channel of the second type semiconductor device in a self-aligned manner; and after the formation of both gate electrodes, it is not necessary to adjust the concentration of both channels of the first type and second type semiconductor device. A method characterized by the following. 6. A method for manufacturing an integrated circuit according to claim 3 or 5, wherein a channel of the first type semiconductor device is determined in a self-aligned manner by the method according to claim 1. A method comprising the steps of: 7. A method for manufacturing an integrated circuit according to claim 4, wherein the method according to claim 2 forms a base diffusion layer of the first type semiconductor device; the second type semiconductor device. Determining the concentration of the second channel;
Forming a gate electrode of a type semiconductor device;
Implanting the second conductivity type impurity according to the method described in the above, wherein the implant energy is:
3. The method according to claim 2, further comprising the step of not passing through a gate electrode of the second type semiconductor device and being able to pass through a gate dielectric layer of the second type semiconductor device. Determining the channels of the first and second type semiconductor devices in a self-aligned manner. 8. The method of manufacturing an integrated circuit according to claim 3, wherein in the step of forming a channel of the first type semiconductor device in a self-aligned manner, forming a source or drain diffusion layer (401, 403). Forming a second gate electrode (410) on the channel of the second type semiconductor device after determining the concentration of the channel of the second type semiconductor device; The first gate electrode (470) and the first dielectric cap (4
75), wherein the first dielectric cap (475) overlaps over the first gate electrode (470); the first gate electrode (47).
0) forming an intermediate dielectric portion (478) on the side surface, wherein at least the side surface of the gate electrode (470) is not exposed, and the source or drain diffusion layer (40) is formed.
1, 403) exposing to a sufficient extent to form a contact; forming an interconnect that is in self-aligned contact with said source or drain diffusion layer (401, 403); Wherein said interconnect is electrically insulated from said gate electrode (470) by said dielectric cap (475) and said intermediate dielectric portion (478). how to. 9. The method of manufacturing an integrated circuit according to claim 4, wherein: in the step of forming the channels of the first type and second type semiconductor devices in a self-aligned manner, a source or drain diffusion layer (401, 403, 405, 407); forming on the channel of the first type semiconductor device;
Forming a first gate electrode (470) and a first dielectric cap (475), wherein the first dielectric cap (475) overlaps over the first gate electrode (470). Forming an intermediate dielectric portion (478) on a side surface of the first gate electrode (470), wherein at least a side surface of the gate electrode (470) is not exposed and a source or drain diffusion layer (478) is formed. 401, 403) exposing to a sufficient extent to form a contact; forming an interconnect in self-aligned contact with said source or drain diffusion layer (401, 403); The interconnect is connected to the gate electrode (47) by the dielectric cap (475) and the intermediate dielectric portion (478).
0) electrically insulated from 0). 10. A step of simultaneously forming both gate electrodes of the first and second type semiconductor devices, wherein a gate electrode (3) is formed on a channel of the first and second type semiconductor devices.
70) and forming a dielectric cap (375), wherein the dielectric cap (375) overlaps over the gate electrode (370); side surfaces of the gate electrode (370) The intermediate dielectric part (37
8) forming the gate electrode (37).
0) wherein at least the side surfaces are not exposed and the source or drain diffusion layers (301, 303, 305, 307) are exposed to an extent sufficient to form a contact; (30
1, 303, 305, 307) in self-aligned contact, said interconnect being formed by said dielectric cap (375) and said intermediate dielectric portion (378). The gate electrode (37
0) electrically insulated from 0). 11. The method of manufacturing an integrated circuit according to claim 8, 9 or 10, wherein at least a drain diffusion layer is formed into a double structure by using the intermediate dielectric portion as a spacer. Relieving the electric field in the drain diffusion layer portion.